Lines Matching refs:rt
322 Register rt; in GetRtReg() local
323 rt.reg_code = (instr & kRtFieldMask) >> kRtShift; in GetRtReg()
324 return rt; in GetRtReg()
530 uint32_t rt = GetRtField(instr); in IsBeqc() local
531 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0 in IsBeqc()
538 uint32_t rt = GetRtField(instr); in IsBnec() local
539 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0 in IsBnec()
596 uint32_t rt = GetRt(instr); in IsNop() local
608 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) && in IsNop()
994 Register rt, in GenInstrRegister() argument
998 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
999 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
1007 Register rt, in GenInstrRegister() argument
1011 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); in GenInstrRegister()
1012 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrRegister()
1046 Register rt, in GenInstrRegister() argument
1050 DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid()); in GenInstrRegister()
1051 Instr instr = opcode | fmt | (rt.code() << kRtShift) in GenInstrRegister()
1059 Register rt, in GenInstrRegister() argument
1062 DCHECK(fs.is_valid() && rt.is_valid()); in GenInstrRegister()
1064 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; in GenInstrRegister()
1071 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt, in GenInstrImmediate() argument
1074 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); in GenInstrImmediate()
1075 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) in GenInstrImmediate()
1270 void Assembler::beq(Register rs, Register rt, int16_t offset) { in beq() argument
1272 GenInstrImmediate(BEQ, rs, rt, offset); in beq()
1284 void Assembler::bgezc(Register rt, int16_t offset) { in bgezc() argument
1286 DCHECK(!(rt.is(zero_reg))); in bgezc()
1287 GenInstrImmediate(BLEZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgezc()
1291 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { in bgeuc() argument
1294 DCHECK(!(rt.is(zero_reg))); in bgeuc()
1295 DCHECK(rs.code() != rt.code()); in bgeuc()
1296 GenInstrImmediate(BLEZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgeuc()
1300 void Assembler::bgec(Register rs, Register rt, int16_t offset) { in bgec() argument
1303 DCHECK(!(rt.is(zero_reg))); in bgec()
1304 DCHECK(rs.code() != rt.code()); in bgec()
1305 GenInstrImmediate(BLEZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgec()
1324 void Assembler::bgtzc(Register rt, int16_t offset) { in bgtzc() argument
1326 DCHECK(!(rt.is(zero_reg))); in bgtzc()
1327 GenInstrImmediate(BGTZL, zero_reg, rt, offset, in bgtzc()
1339 void Assembler::blezc(Register rt, int16_t offset) { in blezc() argument
1341 DCHECK(!(rt.is(zero_reg))); in blezc()
1342 GenInstrImmediate(BLEZL, zero_reg, rt, offset, in blezc()
1347 void Assembler::bltzc(Register rt, int16_t offset) { in bltzc() argument
1349 DCHECK(!rt.is(zero_reg)); in bltzc()
1350 GenInstrImmediate(BGTZL, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltzc()
1354 void Assembler::bltuc(Register rs, Register rt, int16_t offset) { in bltuc() argument
1357 DCHECK(!(rt.is(zero_reg))); in bltuc()
1358 DCHECK(rs.code() != rt.code()); in bltuc()
1359 GenInstrImmediate(BGTZ, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltuc()
1363 void Assembler::bltc(Register rs, Register rt, int16_t offset) { in bltc() argument
1366 DCHECK(!rt.is(zero_reg)); in bltc()
1367 DCHECK(rs.code() != rt.code()); in bltc()
1368 GenInstrImmediate(BGTZL, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltc()
1387 void Assembler::bne(Register rs, Register rt, int16_t offset) { in bne() argument
1389 GenInstrImmediate(BNE, rs, rt, offset); in bne()
1394 void Assembler::bovc(Register rs, Register rt, int16_t offset) { in bovc() argument
1396 if (rs.code() >= rt.code()) { in bovc()
1397 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bovc()
1399 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bovc()
1404 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { in bnvc() argument
1406 if (rs.code() >= rt.code()) { in bnvc()
1407 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnvc()
1409 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnvc()
1414 void Assembler::blezalc(Register rt, int16_t offset) { in blezalc() argument
1416 DCHECK(!(rt.is(zero_reg))); in blezalc()
1417 GenInstrImmediate(BLEZ, zero_reg, rt, offset, in blezalc()
1422 void Assembler::bgezalc(Register rt, int16_t offset) { in bgezalc() argument
1424 DCHECK(!(rt.is(zero_reg))); in bgezalc()
1425 GenInstrImmediate(BLEZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); in bgezalc()
1438 void Assembler::bltzalc(Register rt, int16_t offset) { in bltzalc() argument
1440 DCHECK(!(rt.is(zero_reg))); in bltzalc()
1441 GenInstrImmediate(BGTZ, rt, rt, offset, CompactBranchType::COMPACT_BRANCH); in bltzalc()
1445 void Assembler::bgtzalc(Register rt, int16_t offset) { in bgtzalc() argument
1447 DCHECK(!(rt.is(zero_reg))); in bgtzalc()
1448 GenInstrImmediate(BGTZ, zero_reg, rt, offset, in bgtzalc()
1453 void Assembler::beqzalc(Register rt, int16_t offset) { in beqzalc() argument
1455 DCHECK(!(rt.is(zero_reg))); in beqzalc()
1456 GenInstrImmediate(ADDI, zero_reg, rt, offset, in beqzalc()
1461 void Assembler::bnezalc(Register rt, int16_t offset) { in bnezalc() argument
1463 DCHECK(!(rt.is(zero_reg))); in bnezalc()
1464 GenInstrImmediate(DADDI, zero_reg, rt, offset, in bnezalc()
1469 void Assembler::beqc(Register rs, Register rt, int16_t offset) { in beqc() argument
1471 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in beqc()
1472 if (rs.code() < rt.code()) { in beqc()
1473 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1475 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in beqc()
1487 void Assembler::bnec(Register rs, Register rt, int16_t offset) { in bnec() argument
1489 DCHECK(rs.code() != rt.code() && rs.code() != 0 && rt.code() != 0); in bnec()
1490 if (rs.code() < rt.code()) { in bnec()
1491 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1493 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); in bnec()
1564 void Assembler::jic(Register rt, int16_t offset) { in jic() argument
1566 GenInstrImmediate(POP66, zero_reg, rt, offset); in jic()
1570 void Assembler::jialc(Register rt, int16_t offset) { in jialc() argument
1572 GenInstrImmediate(POP76, zero_reg, rt, offset); in jialc()
1580 void Assembler::addu(Register rd, Register rs, Register rt) { in addu() argument
1581 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); in addu()
1590 void Assembler::subu(Register rd, Register rs, Register rt) { in subu() argument
1591 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); in subu()
1595 void Assembler::mul(Register rd, Register rs, Register rt) { in mul() argument
1597 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH); in mul()
1599 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); in mul()
1604 void Assembler::muh(Register rd, Register rs, Register rt) { in muh() argument
1606 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH); in muh()
1610 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu() argument
1612 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U); in mulu()
1616 void Assembler::muhu(Register rd, Register rs, Register rt) { in muhu() argument
1618 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U); in muhu()
1622 void Assembler::dmul(Register rd, Register rs, Register rt) { in dmul() argument
1624 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH); in dmul()
1628 void Assembler::dmuh(Register rd, Register rs, Register rt) { in dmuh() argument
1630 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH); in dmuh()
1634 void Assembler::dmulu(Register rd, Register rs, Register rt) { in dmulu() argument
1636 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U); in dmulu()
1640 void Assembler::dmuhu(Register rd, Register rs, Register rt) { in dmuhu() argument
1642 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U); in dmuhu()
1646 void Assembler::mult(Register rs, Register rt) { in mult() argument
1648 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT); in mult()
1652 void Assembler::multu(Register rs, Register rt) { in multu() argument
1654 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); in multu()
1663 void Assembler::div(Register rs, Register rt) { in div() argument
1664 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV); in div()
1668 void Assembler::div(Register rd, Register rs, Register rt) { in div() argument
1670 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1674 void Assembler::mod(Register rd, Register rs, Register rt) { in mod() argument
1676 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD); in mod()
1680 void Assembler::divu(Register rs, Register rt) { in divu() argument
1681 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); in divu()
1685 void Assembler::divu(Register rd, Register rs, Register rt) { in divu() argument
1687 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1691 void Assembler::modu(Register rd, Register rs, Register rt) { in modu() argument
1693 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U); in modu()
1697 void Assembler::daddu(Register rd, Register rs, Register rt) { in daddu() argument
1698 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU); in daddu()
1702 void Assembler::dsubu(Register rd, Register rs, Register rt) { in dsubu() argument
1703 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU); in dsubu()
1707 void Assembler::dmult(Register rs, Register rt) { in dmult() argument
1708 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT); in dmult()
1712 void Assembler::dmultu(Register rs, Register rt) { in dmultu() argument
1713 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU); in dmultu()
1717 void Assembler::ddiv(Register rs, Register rt) { in ddiv() argument
1718 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV); in ddiv()
1722 void Assembler::ddiv(Register rd, Register rs, Register rt) { in ddiv() argument
1724 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
1728 void Assembler::dmod(Register rd, Register rs, Register rt) { in dmod() argument
1730 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD); in dmod()
1734 void Assembler::ddivu(Register rs, Register rt) { in ddivu() argument
1735 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU); in ddivu()
1739 void Assembler::ddivu(Register rd, Register rs, Register rt) { in ddivu() argument
1741 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
1745 void Assembler::dmodu(Register rd, Register rs, Register rt) { in dmodu() argument
1747 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U); in dmodu()
1753 void Assembler::and_(Register rd, Register rs, Register rt) { in and_() argument
1754 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); in and_()
1758 void Assembler::andi(Register rt, Register rs, int32_t j) { in andi() argument
1760 GenInstrImmediate(ANDI, rs, rt, j); in andi()
1764 void Assembler::or_(Register rd, Register rs, Register rt) { in or_() argument
1765 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); in or_()
1769 void Assembler::ori(Register rt, Register rs, int32_t j) { in ori() argument
1771 GenInstrImmediate(ORI, rs, rt, j); in ori()
1775 void Assembler::xor_(Register rd, Register rs, Register rt) { in xor_() argument
1776 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); in xor_()
1780 void Assembler::xori(Register rt, Register rs, int32_t j) { in xori() argument
1782 GenInstrImmediate(XORI, rs, rt, j); in xori()
1786 void Assembler::nor(Register rd, Register rs, Register rt) { in nor() argument
1787 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); in nor()
1793 Register rt, in sll() argument
1800 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); in sll()
1801 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL); in sll()
1805 void Assembler::sllv(Register rd, Register rt, Register rs) { in sllv() argument
1806 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
1810 void Assembler::srl(Register rd, Register rt, uint16_t sa) { in srl() argument
1811 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL); in srl()
1815 void Assembler::srlv(Register rd, Register rt, Register rs) { in srlv() argument
1816 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); in srlv()
1820 void Assembler::sra(Register rd, Register rt, uint16_t sa) { in sra() argument
1821 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRA); in sra()
1825 void Assembler::srav(Register rd, Register rt, Register rs) { in srav() argument
1826 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); in srav()
1830 void Assembler::rotr(Register rd, Register rt, uint16_t sa) { in rotr() argument
1832 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); in rotr()
1834 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) in rotr()
1840 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() argument
1842 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in rotrv()
1844 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in rotrv()
1850 void Assembler::dsll(Register rd, Register rt, uint16_t sa) { in dsll() argument
1851 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL); in dsll()
1855 void Assembler::dsllv(Register rd, Register rt, Register rs) { in dsllv() argument
1856 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV); in dsllv()
1860 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) { in dsrl() argument
1861 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL); in dsrl()
1865 void Assembler::dsrlv(Register rd, Register rt, Register rs) { in dsrlv() argument
1866 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV); in dsrlv()
1870 void Assembler::drotr(Register rd, Register rt, uint16_t sa) { in drotr() argument
1871 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); in drotr()
1872 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) in drotr()
1877 void Assembler::drotr32(Register rd, Register rt, uint16_t sa) { in drotr32() argument
1878 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); in drotr32()
1879 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) | in drotr32()
1884 void Assembler::drotrv(Register rd, Register rt, Register rs) { in drotrv() argument
1885 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); in drotrv()
1886 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) in drotrv()
1892 void Assembler::dsra(Register rd, Register rt, uint16_t sa) { in dsra() argument
1893 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA); in dsra()
1897 void Assembler::dsrav(Register rd, Register rt, Register rs) { in dsrav() argument
1898 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV); in dsrav()
1902 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) { in dsll32() argument
1903 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL32); in dsll32()
1907 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) { in dsrl32() argument
1908 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRL32); in dsrl32()
1912 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) { in dsra32() argument
1913 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSRA32); in dsra32()
1917 void Assembler::lsa(Register rd, Register rt, Register rs, uint8_t sa) { in lsa() argument
1918 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in lsa()
1921 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift | in lsa()
1927 void Assembler::dlsa(Register rd, Register rt, Register rs, uint8_t sa) { in dlsa() argument
1928 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid()); in dlsa()
1931 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift | in dlsa()
2074 void Assembler::aui(Register rt, Register rs, int32_t j) { in aui() argument
2078 GenInstrImmediate(LUI, rs, rt, j); in aui()
2082 void Assembler::daui(Register rt, Register rs, int32_t j) { in daui() argument
2085 GenInstrImmediate(DAUI, rs, rt, j); in daui()
2237 void Assembler::tge(Register rs, Register rt, uint16_t code) { in tge() argument
2240 | rt.code() << kRtShift | code << 6; in tge()
2245 void Assembler::tgeu(Register rs, Register rt, uint16_t code) { in tgeu() argument
2248 | rt.code() << kRtShift | code << 6; in tgeu()
2253 void Assembler::tlt(Register rs, Register rt, uint16_t code) { in tlt() argument
2256 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tlt()
2261 void Assembler::tltu(Register rs, Register rt, uint16_t code) { in tltu() argument
2265 | rt.code() << kRtShift | code << 6; in tltu()
2270 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() argument
2273 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in teq()
2278 void Assembler::tne(Register rs, Register rt, uint16_t code) { in tne() argument
2281 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; in tne()
2303 void Assembler::slt(Register rd, Register rs, Register rt) { in slt() argument
2304 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); in slt()
2308 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() argument
2309 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); in sltu()
2313 void Assembler::slti(Register rt, Register rs, int32_t j) { in slti() argument
2314 GenInstrImmediate(SLTI, rs, rt, j); in slti()
2318 void Assembler::sltiu(Register rt, Register rs, int32_t j) { in sltiu() argument
2319 GenInstrImmediate(SLTIU, rs, rt, j); in sltiu()
2324 void Assembler::movz(Register rd, Register rs, Register rt) { in movz() argument
2325 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
2329 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() argument
2330 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); in movn()
2335 Register rt; in movt() local
2336 rt.reg_code = (cc & 0x0007) << 2 | 1; in movt()
2337 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movt()
2342 Register rt; in movf() local
2343 rt.reg_code = (cc & 0x0007) << 2 | 0; in movf()
2344 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movf()
2405 void Assembler::seleqz(Register rd, Register rs, Register rt) { in seleqz() argument
2407 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); in seleqz()
2412 void Assembler::selnez(Register rd, Register rs, Register rt) { in selnez() argument
2414 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); in selnez()
2439 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ins_() argument
2443 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
2447 void Assembler::dins_(Register rt, Register rs, uint16_t pos, uint16_t size) { in dins_() argument
2451 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, DINS); in dins_()
2455 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in ext_() argument
2459 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); in ext_()
2463 void Assembler::dext_(Register rt, Register rs, uint16_t pos, uint16_t size) { in dext_() argument
2467 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT); in dext_()
2471 void Assembler::dextm(Register rt, Register rs, uint16_t pos, uint16_t size) { in dextm() argument
2475 GenInstrRegister(SPECIAL3, rs, rt, size - 1 - 32, pos, DEXTM); in dextm()
2479 void Assembler::dextu(Register rt, Register rs, uint16_t pos, uint16_t size) { in dextu() argument
2483 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos - 32, DEXTU); in dextu()
2487 void Assembler::bitswap(Register rd, Register rt) { in bitswap() argument
2489 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, BSHFL); in bitswap()
2493 void Assembler::dbitswap(Register rd, Register rt) { in dbitswap() argument
2495 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, 0, DBSHFL); in dbitswap()
2507 void Assembler::align(Register rd, Register rs, Register rt, uint8_t bp) { in align() argument
2511 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, BSHFL); in align()
2515 void Assembler::dalign(Register rd, Register rs, Register rt, uint8_t bp) { in dalign() argument
2519 GenInstrRegister(SPECIAL3, rs, rt, rd, sa, DBSHFL); in dalign()
2522 void Assembler::wsbh(Register rd, Register rt) { in wsbh() argument
2524 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, WSBH, BSHFL); in wsbh()
2527 void Assembler::dsbh(Register rd, Register rt) { in dsbh() argument
2529 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSBH, DBSHFL); in dsbh()
2532 void Assembler::dshd(Register rd, Register rt) { in dshd() argument
2534 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, DSHD, DBSHFL); in dshd()
2537 void Assembler::seh(Register rd, Register rt) { in seh() argument
2539 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEH, BSHFL); in seh()
2542 void Assembler::seb(Register rd, Register rt) { in seb() argument
2544 GenInstrRegister(SPECIAL3, zero_reg, rt, rd, SEB, BSHFL); in seb()
2591 void Assembler::mtc1(Register rt, FPURegister fs) { in mtc1() argument
2592 GenInstrRegister(COP1, MTC1, rt, fs, f0); in mtc1()
2596 void Assembler::mthc1(Register rt, FPURegister fs) { in mthc1() argument
2597 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
2601 void Assembler::dmtc1(Register rt, FPURegister fs) { in dmtc1() argument
2602 GenInstrRegister(COP1, DMTC1, rt, fs, f0); in dmtc1()
2606 void Assembler::mfc1(Register rt, FPURegister fs) { in mfc1() argument
2607 GenInstrRegister(COP1, MFC1, rt, fs, f0); in mfc1()
2611 void Assembler::mfhc1(Register rt, FPURegister fs) { in mfhc1() argument
2612 GenInstrRegister(COP1, MFHC1, rt, fs, f0); in mfhc1()
2616 void Assembler::dmfc1(Register rt, FPURegister fs) { in dmfc1() argument
2617 GenInstrRegister(COP1, DMFC1, rt, fs, f0); in dmfc1()
2621 void Assembler::ctc1(Register rt, FPUControlRegister fs) { in ctc1() argument
2622 GenInstrRegister(COP1, CTC1, rt, fs); in ctc1()
2626 void Assembler::cfc1(Register rt, FPUControlRegister fs) { in cfc1() argument
2627 GenInstrRegister(COP1, CFC1, rt, fs); in cfc1()
2687 void Assembler::movz_s(FPURegister fd, FPURegister fs, Register rt) { in movz_s() argument
2689 GenInstrRegister(COP1, S, rt, fs, fd, MOVZ_C); in movz_s()
2693 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) { in movz_d() argument
2695 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C); in movz_d()
2731 void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) { in movn_s() argument
2733 GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C); in movn_s()
2737 void Assembler::movn_d(FPURegister fd, FPURegister fs, Register rt) { in movn_d() argument
2739 GenInstrRegister(COP1, D, rt, fs, fd, MOVN_C); in movn_d()