Lines Matching refs:rreg
1201 void genSpill_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genSpill_TILEGX() argument
1206 vassert(!hregIsVirtual(rreg)); in genSpill_TILEGX()
1210 switch (hregClass(rreg)) { in genSpill_TILEGX()
1212 *i1 = TILEGXInstr_Store(8, am, rreg); in genSpill_TILEGX()
1215 *i1 = TILEGXInstr_Store(4, am, rreg); in genSpill_TILEGX()
1218 ppHRegClass(hregClass(rreg)); in genSpill_TILEGX()
1223 void genReload_TILEGX ( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, in genReload_TILEGX() argument
1227 vassert(!hregIsVirtual(rreg)); in genReload_TILEGX()
1230 switch (hregClass(rreg)) { in genReload_TILEGX()
1232 *i1 = TILEGXInstr_Load(8, rreg, am); in genReload_TILEGX()
1235 *i1 = TILEGXInstr_Load(4, rreg, am); in genReload_TILEGX()
1238 ppHRegClass(hregClass(rreg)); in genReload_TILEGX()