148 } simulator;  variable
1068     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I0D()
1093     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);  in log_2I0D()
1095     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);  in log_2I0D()
1126     Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);  in log_3I0D()
1128     Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);  in log_3I0D()
1130     Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);  in log_3I0D()
1165     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I1Dr()
1166     DrRes = (*simulator.D1_Read)(data_addr, data_size);  in log_1I1Dr()
1201     DrRes = (*simulator.D1_Read)(data_addr, data_size);  in log_0I1Dr()
1228     IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);  in log_1I1Dw()
1229     DwRes = (*simulator.D1_Write)(data_addr, data_size);  in log_1I1Dw()
1261     DwRes = (*simulator.D1_Write)(data_addr, data_size);  in log_0I1Dw()
1389       simulator.I1_Read  = cacheuse_I1_doRead;  in cachesim_post_clo_init()
1390       simulator.D1_Read  = cacheuse_D1_doRead;  in cachesim_post_clo_init()
1391       simulator.D1_Write = cacheuse_D1_doRead;  in cachesim_post_clo_init()
1399       simulator.I1_Read  = prefetch_I1_Read;  in cachesim_post_clo_init()
1400       simulator.D1_Read  = prefetch_D1_Read;  in cachesim_post_clo_init()
1401       simulator.D1_Write = prefetch_D1_Write;  in cachesim_post_clo_init()
1404       simulator.I1_Read  = prefetch_I1_ref;  in cachesim_post_clo_init()
1405       simulator.D1_Read  = prefetch_D1_ref;  in cachesim_post_clo_init()
1406       simulator.D1_Write = prefetch_D1_ref;  in cachesim_post_clo_init()
1413       simulator.I1_Read  = cachesim_I1_Read;  in cachesim_post_clo_init()
1414       simulator.D1_Read  = cachesim_D1_Read;  in cachesim_post_clo_init()
1415       simulator.D1_Write = cachesim_D1_Write;  in cachesim_post_clo_init()
1418       simulator.I1_Read  = cachesim_I1_ref;  in cachesim_post_clo_init()
1419       simulator.D1_Read  = cachesim_D1_ref;  in cachesim_post_clo_init()
1420       simulator.D1_Write = cachesim_D1_ref;  in cachesim_post_clo_init()