1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __SRAM_MAP_H__ 33 #define __SRAM_MAP_H__ 34 35 /* 36 * SRAM Memory Region Layout 37 * 38 * +-----------------------+ 39 * | Low Power Mode | 7KB 40 * +-----------------------+ 41 * | Secure OS | 64KB 42 * +-----------------------+ 43 * | Software Flag | 1KB 44 * +-----------------------+ 45 * 46 */ 47 48 #define SOC_SRAM_OFF_BASE_ADDR (0xFFF80000) 49 50 /* PM Section: 7KB */ 51 #define SRAM_PM_ADDR (SOC_SRAM_OFF_BASE_ADDR) 52 #define SRAM_PM_SIZE (0x00001C00) 53 54 /* TEE OS Section: 64KB */ 55 #define SRAM_TEEOS_ADDR (SRAM_PM_ADDR + SRAM_PM_SIZE) 56 #define SRAM_TEEOS_SIZE (0x00010000) 57 58 /* General Use Section: 1KB */ 59 #define SRAM_GENERAL_ADDR (SRAM_TEEOS_ADDR + SRAM_TEEOS_SIZE) 60 #define SRAM_GENERAL_SIZE (0x00000400) 61 62 /* 63 * General Usage Section Layout: 64 * 65 * +-----------------------+ 66 * | AP boot flag | 64B 67 * +-----------------------+ 68 * | DICC flag | 32B 69 * +-----------------------+ 70 * | Soft flag | 256B 71 * +-----------------------+ 72 * | Thermal flag | 128B 73 * +-----------------------+ 74 * | CSHELL | 4B 75 * +-----------------------+ 76 * | Uart Switching | 4B 77 * +-----------------------+ 78 * | ICC | 1024B 79 * +-----------------------+ 80 * | Memory Management | 1024B 81 * +-----------------------+ 82 * | IFC | 32B 83 * +-----------------------+ 84 * | HIFI | 32B 85 * +-----------------------+ 86 * | DDR capacity | 4B 87 * +-----------------------+ 88 * | Reserved | 89 * +-----------------------+ 90 * 91 */ 92 93 /* App Core Boot Flags */ 94 #define MEMORY_AXI_ACPU_START_ADDR (SRAM_GENERAL_ADDR) 95 #define MEMORY_AXI_ACPU_START_SIZE (64) 96 97 #define MEMORY_AXI_SRESET_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0000) 98 #define MEMORY_AXI_SECOND_CPU_BOOT_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0004) 99 #define MEMORY_AXI_READY_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0008) 100 #define MEMORY_AXI_FASTBOOT_ENTRY_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x000C) 101 #define MEMORY_AXI_PD_CHARGE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0010) 102 #define MEMORY_AXI_DBG_ALARM_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0014) 103 #define MEMORY_AXI_CHIP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0018) 104 #define MEMORY_AXI_BOARD_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x001C) 105 #define MEMORY_AXI_BOARD_ID_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0020) 106 #define MEMORY_AXI_CHARGETYPE_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0024) 107 #define MEMORY_AXI_COLD_START_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0028) 108 #define MEMORY_AXI_ANDROID_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x002C) 109 #define MEMORY_AXI_ACPU_WDTRST_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0030) 110 #define MEMORY_AXI_ABNRST_BITMAP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0034) 111 #define MEMORY_AXI_32K_CLK_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0038) 112 #define AXI_MODEM_PANIC_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x003C) 113 #define AXI_MODEM_PANIC_FLAG (0x68697369) 114 #define MEMORY_AXI_ACPU_END_ADDR (AXI_MODEM_PANIC_FLAG_ADDR + 4) 115 116 /* DICC Flags */ 117 #define MEMORY_AXI_DICC_ADDR (MEMORY_AXI_ACPU_START_ADDR + MEMORY_AXI_ACPU_START_SIZE) 118 #define MEMORY_AXI_DICC_SIZE (32) 119 120 #define MEMORY_AXI_SOFT_FLAG_ADDR (MEMORY_AXI_DICC_ADDR + MEMORY_AXI_DICC_SIZE) 121 #define MEMORY_AXI_SOFT_FLAG_SIZE (256) 122 123 /* Thermal Flags */ 124 #define MEMORY_AXI_TEMP_PROTECT_ADDR (MEMORY_AXI_SOFT_FLAG_ADDR + MEMORY_AXI_SOFT_FLAG_SIZE) 125 #define MEMORY_AXI_TEMP_PROTECT_SIZE (128) 126 127 /* CSHELL */ 128 #define MEMORY_AXI_USB_CSHELL_ADDR (MEMORY_AXI_TEMP_PROTECT_ADDR + MEMORY_AXI_TEMP_PROTECT_SIZE) 129 #define MEMORY_AXI_USB_CSHELL_SIZE (4) 130 131 /* Uart and A/C Shell Switch Flags */ 132 #define MEMORY_AXI_UART_INOUT_ADDR (MEMORY_AXI_USB_CSHELL_ADDR + MEMORY_AXI_USB_CSHELL_SIZE) 133 #define MEMORY_AXI_UART_INOUT_SIZE (4) 134 135 /* IFC Flags */ 136 #define MEMORY_AXI_IFC_ADDR (MEMORY_AXI_UART_INOUT_ADDR + MEMORY_AXI_UART_INOUT_SIZE) 137 #define MEMORY_AXI_IFC_SIZE (32) 138 139 /* HIFI Data */ 140 #define MEMORY_AXI_HIFI_ADDR (MEMORY_AXI_IFC_ADDR + MEMORY_AXI_IFC_SIZE) 141 #define MEMORY_AXI_HIFI_SIZE (32) 142 143 /* CONFIG Flags */ 144 #define MEMORY_AXI_CONFIG_ADDR (MEMORY_AXI_HIFI_ADDR + MEMORY_AXI_HIFI_SIZE) 145 #define MEMORY_AXI_CONFIG_SIZE (32) 146 147 /* DDR Capacity Flags */ 148 #define MEMORY_AXI_DDR_CAPACITY_ADDR (MEMORY_AXI_CONFIG_ADDR + MEMORY_AXI_CONFIG_SIZE) 149 #define MEMORY_AXI_DDR_CAPACITY_SIZE (4) 150 151 /* USB Shell Flags */ 152 #define MEMORY_AXI_USB_SHELL_FLAG_ADDR (MEMORY_AXI_DDR_CAPACITY_ADDR + MEMORY_AXI_DDR_CAPACITY_SIZE ) 153 #define MEMORY_AXI_USB_SHELL_FLAG_SIZE (4) 154 155 /* MCU WDT Switch Flag */ 156 #define MEMORY_AXI_MCU_WDT_FLAG_ADDR (MEMORY_AXI_USB_SHELL_FLAG_ADDR + MEMORY_AXI_USB_SHELL_FLAG_SIZE) 157 #define MEMORY_AXI_MCU_WDT_FLAG_SIZE (4) 158 159 /* TLDSP Mailbox MNTN */ 160 #define SRAM_DSP_MNTN_INFO_ADDR (MEMORY_AXI_MCU_WDT_FLAG_ADDR + MEMORY_AXI_MCU_WDT_FLAG_SIZE) 161 #define SRAM_DSP_MNTN_SIZE (32) 162 163 /* TLDSP ARM Mailbox Protect Flag */ 164 #define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR (SRAM_DSP_MNTN_INFO_ADDR + SRAM_DSP_MNTN_SIZE) 165 #define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE (4) 166 167 /* RTT Sleep Flag */ 168 #define SRAM_RTT_SLEEP_FLAG_ADDR (SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR + SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE) 169 #define SRAM_RTT_SLEEP_FLAG_SIZE (32) 170 171 /* LDSP Awake Flag */ 172 #define MEMORY_AXI_LDSP_AWAKE_ADDR (SRAM_RTT_SLEEP_FLAG_ADDR + SRAM_RTT_SLEEP_FLAG_SIZE) 173 #define MEMORY_AXI_LDSP_AWAKE_SIZE (4) 174 175 #define NVUPDATE_SUCCESS 0x5555AAAA 176 #define NVUPDATE_FAILURE 0xAAAA5555 177 178 /* 179 * Low Power Mode Region 180 */ 181 #define PWRCTRL_ACPU_ASM_SPACE_ADDR (SRAM_PM_ADDR) 182 #define PWRCTRL_ACPU_ASM_SPACE_SIZE (SRAM_PM_SIZE) 183 184 #define PWRCTRL_ACPU_ASM_MEM_BASE (PWRCTRL_ACPU_ASM_SPACE_ADDR) 185 #define PWRCTRL_ACPU_ASM_MEM_SIZE (PWRCTRL_ACPU_ASM_SPACE_SIZE) 186 #define PWRCTRL_ACPU_ASM_CODE_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0x200) 187 #define PWRCTRL_ACPU_ASM_DATA_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0xE00) 188 #define PWRCTRL_ACPU_ASM_DATA_SIZE (0xE00) 189 190 #define PWRCTRL_ACPU_ASM_D_C0_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE) 191 #define PWRCTRL_ACPU_ASM_D_C0_MMU_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0) 192 #define PWRCTRL_ACPU_ASM_D_ARM_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0x20) 193 194 #define PWRCTRL_ACPU_ASM_D_COMM_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE + 0x700) 195 196 #define PWRCTRL_ACPU_REBOOT (PWRCTRL_ACPU_ASM_D_COMM_ADDR) 197 #define PWRCTRL_ACPU_REBOOT_SIZE (0x200) 198 #define PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR (PWRCTRL_ACPU_REBOOT + PWRCTRL_ACPU_REBOOT_SIZE) 199 #define PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE (4) 200 #define PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR (PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR + PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE) 201 #define PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE (4) 202 #define EXCH_A_CORE_POWRCTRL_CONV_ADDR (PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR + PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE) 203 #define EXCH_A_CORE_POWRCTRL_CONV_SIZE (4) 204 205 /* 206 * Below region memory mapping is: 207 * 4 + 12 + 16 + 28 + 28 + 16 + 28 + 12 + 24 + 20 + 64 + 208 * 4 + 4 + 4 + 4 + 12 + 4 + 4 + 4 + 4 + 16 + 4 + 0x2BC + 209 * 24 + 20 + 12 + 16 210 */ 211 212 #define MEMORY_AXI_CPU_IDLE_ADDR (EXCH_A_CORE_POWRCTRL_CONV_ADDR + EXCH_A_CORE_POWRCTRL_CONV_SIZE) 213 #define MEMORY_AXI_CPU_IDLE_SIZE (4) 214 215 #define MEMORY_AXI_CUR_FREQ_ADDR (MEMORY_AXI_CPU_IDLE_ADDR + MEMORY_AXI_CPU_IDLE_SIZE) 216 #define MEMORY_AXI_CUR_FREQ_SIZE (12) 217 218 #define MEMORY_AXI_ACPU_FREQ_VOL_ADDR (MEMORY_AXI_CUR_FREQ_ADDR + MEMORY_AXI_CUR_FREQ_SIZE) 219 #define MEMORY_AXI_ACPU_FREQ_VOL_SIZE (16 + 28 + 28) 220 221 #define MEMORY_AXI_DDR_FREQ_VOL_ADDR (MEMORY_AXI_ACPU_FREQ_VOL_ADDR + MEMORY_AXI_ACPU_FREQ_VOL_SIZE) 222 #define MEMORY_AXI_DDR_FREQ_VOL_SIZE (16 + 28) 223 224 #define MEMORY_AXI_ACPU_FIQ_TEST_ADDR (MEMORY_AXI_DDR_FREQ_VOL_ADDR + MEMORY_AXI_DDR_FREQ_VOL_SIZE) 225 #define MEMORY_AXI_ACPU_FIQ_TEST_SIZE (12) 226 227 #define MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_TEST_ADDR + MEMORY_AXI_ACPU_FIQ_TEST_SIZE) 228 #define MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE (24) 229 230 #define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE) 231 #define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE (20) 232 233 #define MEMORY_FREQDUMP_ADDR (MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE) 234 #define MEMORY_FREQDUMP_SIZE (64) 235 236 #define MEMORY_AXI_CCPU_LOG_ADDR (MEMORY_FREQDUMP_ADDR + MEMORY_FREQDUMP_SIZE) 237 #define MEMORY_AXI_CCPU_LOG_SIZE (4) 238 239 #define MEMORY_AXI_MCU_LOG_ADDR (MEMORY_AXI_CCPU_LOG_ADDR + MEMORY_AXI_CCPU_LOG_SIZE) 240 #define MEMORY_AXI_MCU_LOG_SIZE (4) 241 242 #define MEMORY_AXI_SEC_CORE_BOOT_ADDR (MEMORY_AXI_MCU_LOG_ADDR + MEMORY_AXI_MCU_LOG_SIZE) 243 #define MEMORY_AXI_SEC_CORE_BOOT_SIZE (4) 244 245 #define MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR (MEMORY_AXI_SEC_CORE_BOOT_ADDR + MEMORY_AXI_SEC_CORE_BOOT_SIZE) 246 #define MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE (0x4) 247 248 #define POLICY_AREA_RESERVED (MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR + MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE) 249 #define POLICY_AREA_RESERVED_SIZE (12) 250 251 #define DDR_POLICY_VALID_MAGIC (POLICY_AREA_RESERVED + POLICY_AREA_RESERVED_SIZE) 252 #define DDR_POLICY_VALID_MAGIC_SIZE (4) 253 254 #define DDR_POLICY_MAX_NUM (DDR_POLICY_VALID_MAGIC + DDR_POLICY_VALID_MAGIC_SIZE) 255 #define DDR_POLICY_MAX_NUM_SIZE (4) 256 257 #define DDR_POLICY_SUPPORT_NUM (DDR_POLICY_MAX_NUM + DDR_POLICY_MAX_NUM_SIZE) 258 #define DDR_POLICY_SUPPORT_NUM_SIZE (4) 259 260 #define DDR_POLICY_CUR_POLICY (DDR_POLICY_SUPPORT_NUM + DDR_POLICY_SUPPORT_NUM_SIZE) 261 #define DDR_POLICY_CUR_POLICY_SIZE (4) 262 263 #define ACPU_POLICY_VALID_MAGIC (DDR_POLICY_CUR_POLICY + DDR_POLICY_CUR_POLICY_SIZE) 264 #define ACPU_POLICY_VALID_MAGIC_SIZE (4) 265 266 #define ACPU_POLICY_MAX_NUM (ACPU_POLICY_VALID_MAGIC + ACPU_POLICY_VALID_MAGIC_SIZE) 267 #define ACPU_POLICY_MAX_NUM_SIZE (4) 268 269 #define ACPU_POLICY_SUPPORT_NUM (ACPU_POLICY_MAX_NUM + ACPU_POLICY_MAX_NUM_SIZE) 270 #define ACPU_POLICY_SUPPORT_NUM_SIZE (4) 271 272 #define ACPU_POLICY_CUR_POLICY (ACPU_POLICY_SUPPORT_NUM + ACPU_POLICY_SUPPORT_NUM_SIZE) 273 #define ACPU_POLICY_CUR_POLICY_SIZE (4) 274 275 #define LPDDR_OPTION_ADDR (ACPU_POLICY_CUR_POLICY + ACPU_POLICY_CUR_POLICY_SIZE) 276 #define LPDDR_OPTION_SIZE (4) 277 278 #define MEMORY_AXI_DDR_DDL_ADDR (LPDDR_OPTION_ADDR + LPDDR_OPTION_SIZE) 279 #define MEMORY_AXI_DDR_DDL_SIZE (0x2BC) 280 281 #define DDR_TEST_DFS_ADDR (MEMORY_AXI_DDR_DDL_ADDR + MEMORY_AXI_DDR_DDL_SIZE) 282 #define DDR_TEST_DFS_ADDR_SIZE (4) 283 284 #define DDR_TEST_DFS_TIMES_ADDR (DDR_TEST_DFS_ADDR + DDR_TEST_DFS_ADDR_SIZE) 285 #define DDR_TEST_DFS_TIMES_ADDR_SIZE (4) 286 287 #define DDR_TEST_QOS_ADDR (DDR_TEST_DFS_TIMES_ADDR + DDR_TEST_DFS_TIMES_ADDR_SIZE) 288 #define DDR_TEST_QOS_ADDR_SIZE (4) 289 290 #define DDR_TEST_FUN_ADDR (DDR_TEST_QOS_ADDR + DDR_TEST_QOS_ADDR_SIZE) 291 #define DDR_TEST_FUN_ADDR_SIZE (4) 292 293 #define BOARD_TYPE_ADDR (DDR_TEST_FUN_ADDR + DDR_TEST_FUN_ADDR_SIZE) 294 #define BOARD_ADDR_SIZE (4) 295 #define DDR_DFS_FREQ_ADDR (BOARD_TYPE_ADDR + BOARD_ADDR_SIZE) 296 #define DDR_DFS_FREQ_SIZE (4) 297 298 #define DDR_PASR_ADDR (DDR_DFS_FREQ_ADDR + DDR_DFS_FREQ_SIZE) 299 #define DDR_PASR_SIZE (20) 300 301 #define ACPU_DFS_FREQ_ADDR (DDR_PASR_ADDR + DDR_PASR_SIZE) 302 #define ACPU_DFS_FREQ_ADDR_SIZE (12) 303 304 #define ACPU_CHIP_MAX_FREQ (ACPU_DFS_FREQ_ADDR + ACPU_DFS_FREQ_ADDR_SIZE) 305 #define ACPU_CHIP_MAX_FREQ_SIZE (4) 306 307 #define MEMORY_MEDPLL_STATE_ADDR (ACPU_CHIP_MAX_FREQ + ACPU_CHIP_MAX_FREQ_SIZE) 308 #define MEMORY_MEDPLL_STATE_SIZE (8) 309 310 #define MEMORY_CCPU_LOAD_FLAG_ADDR (MEMORY_MEDPLL_STATE_ADDR + MEMORY_MEDPLL_STATE_SIZE) 311 #define MEMORY_CCPU_LOAD_FLAG_SIZE (4) 312 313 314 #define ACPU_CORE_BITS_ADDR (MEMORY_CCPU_LOAD_FLAG_ADDR + MEMORY_CCPU_LOAD_FLAG_SIZE) 315 #define ACPU_CORE_BITS_SIZE (4) 316 317 #define ACPU_CLUSTER_IDLE_ADDR (ACPU_CORE_BITS_ADDR + ACPU_CORE_BITS_SIZE) 318 #define ACPU_CLUSTER_IDLE_SIZE (4) 319 320 #define ACPU_A53_FLAGS_ADDR (ACPU_CLUSTER_IDLE_ADDR + ACPU_CLUSTER_IDLE_SIZE) 321 #define ACPU_A53_FLAGS_SIZE (4) 322 323 #define ACPU_POWER_STATE_QOS_ADDR (ACPU_A53_FLAGS_ADDR+ACPU_A53_FLAGS_SIZE) 324 #define ACPU_POWER_STATE_QOS_SIZE (4) 325 326 #define ACPU_UNLOCK_CORE_FLAGS_ADDR (ACPU_POWER_STATE_QOS_ADDR+ACPU_POWER_STATE_QOS_SIZE) 327 #define ACPU_UNLOCK_CORE_FLAGS_SIZE (8) 328 329 #define ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR (ACPU_UNLOCK_CORE_FLAGS_ADDR + ACPU_UNLOCK_CORE_FLAGS_SIZE) 330 #define ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE (4) 331 332 #define ACPU_CORE_POWERDOWN_FLAGS_ADDR (ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR + ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE) 333 #define ACPU_CORE_POWERDOWN_FLAGS_SIZE (4) 334 335 #define ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR (ACPU_CORE_POWERDOWN_FLAGS_ADDR + ACPU_CORE_POWERDOWN_FLAGS_SIZE) 336 #define ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE (4) 337 338 #define ACPU_ARM64_FLAGA (ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR + ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE) 339 #define ACPU_ARM64_FLAGA_SIZE (4) 340 341 #define ACPU_ARM64_FLAGB (ACPU_ARM64_FLAGA + ACPU_ARM64_FLAGA_SIZE) 342 #define ACPU_ARM64_FLAGB_SIZE (4) 343 344 #define MCU_EXCEPTION_FLAGS_ADDR (ACPU_ARM64_FLAGB + ACPU_ARM64_FLAGB_SIZE) 345 #define MCU_EXCEPTION_FLAGS_SIZE (4) 346 347 #define ACPU_MASTER_CORE_STATE_ADDR (MCU_EXCEPTION_FLAGS_ADDR + MCU_EXCEPTION_FLAGS_SIZE) 348 #define ACPU_MASTER_CORE_STATE_SIZE (4) 349 350 #define PWRCTRL_AXI_RESERVED_ADDR (ACPU_MASTER_CORE_STATE_ADDR + ACPU_MASTER_CORE_STATE_SIZE) 351 352 #endif /* __SRAM_MAP_H__ */ 353