1 /*
2  * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
3  * Copyright (c) Imagination Technologies Limited, UK
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial portions
15  * of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 
27 /*!
28 ******************************************************************************
29 @file   : /work/sim/msvdx/register_includes/msvdx_dmac_regs_io2.h
30 
31 @brief
32 
33 @Author <Autogenerated>
34 
35 <b>Description:</b>\n
36                 This file contains the MSVDX_DMAC_REGS_IO2_H Defintions.
37 
38 <b>Platform:</b>\n
39                 ?
40 
41 @Version
42                 1.0
43 
44 ******************************************************************************/
45 
46 #if !defined (__MSVDX_DMAC_REGS_IO2_H__)
47 #define __MSVDX_DMAC_REGS_IO2_H__
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
53 
54 #define DMAC_DMAC_SETUP_OFFSET          (0x0000)
55 #define DMAC_DMAC_SETUP_STRIDE          (32)
56 #define DMAC_DMAC_SETUP_NO_ENTRIES              (4)
57 
58 // DMAC     DMAC_SETUP     START_ADDRESS
59 #define DMAC_DMAC_SETUP_START_ADDRESS_MASK              (0xFFFFFFFF)
60 #define DMAC_DMAC_SETUP_START_ADDRESS_LSBMASK           (0xFFFFFFFF)
61 #define DMAC_DMAC_SETUP_START_ADDRESS_SHIFT             (0)
62 
63 #define DMAC_DMAC_COUNT_OFFSET          (0x0004)
64 #define DMAC_DMAC_COUNT_STRIDE          (32)
65 #define DMAC_DMAC_COUNT_NO_ENTRIES              (4)
66 
67 // DMAC     DMAC_COUNT     LIST_IEN
68 #define DMAC_DMAC_COUNT_LIST_IEN_MASK           (0x80000000)
69 #define DMAC_DMAC_COUNT_LIST_IEN_LSBMASK                (0x00000001)
70 #define DMAC_DMAC_COUNT_LIST_IEN_SHIFT          (31)
71 
72 // DMAC     DMAC_COUNT     BSWAP
73 #define DMAC_DMAC_COUNT_BSWAP_MASK              (0x40000000)
74 #define DMAC_DMAC_COUNT_BSWAP_LSBMASK           (0x00000001)
75 #define DMAC_DMAC_COUNT_BSWAP_SHIFT             (30)
76 
77 // DMAC     DMAC_COUNT     TRANSFER_IEN
78 #define DMAC_DMAC_COUNT_TRANSFER_IEN_MASK               (0x20000000)
79 #define DMAC_DMAC_COUNT_TRANSFER_IEN_LSBMASK            (0x00000001)
80 #define DMAC_DMAC_COUNT_TRANSFER_IEN_SHIFT              (29)
81 
82 // DMAC     DMAC_COUNT     PW
83 #define DMAC_DMAC_COUNT_PW_MASK         (0x18000000)
84 #define DMAC_DMAC_COUNT_PW_LSBMASK              (0x00000003)
85 #define DMAC_DMAC_COUNT_PW_SHIFT                (27)
86 
87 // DMAC     DMAC_COUNT     DIR
88 #define DMAC_DMAC_COUNT_DIR_MASK                (0x04000000)
89 #define DMAC_DMAC_COUNT_DIR_LSBMASK             (0x00000001)
90 #define DMAC_DMAC_COUNT_DIR_SHIFT               (26)
91 
92 // DMAC     DMAC_COUNT     PI
93 #define DMAC_DMAC_COUNT_PI_MASK         (0x03000000)
94 #define DMAC_DMAC_COUNT_PI_LSBMASK              (0x00000003)
95 #define DMAC_DMAC_COUNT_PI_SHIFT                (24)
96 
97 // DMAC     DMAC_COUNT     LIST_FIN_CTL
98 #define DMAC_DMAC_COUNT_LIST_FIN_CTL_MASK               (0x00400000)
99 #define DMAC_DMAC_COUNT_LIST_FIN_CTL_LSBMASK            (0x00000001)
100 #define DMAC_DMAC_COUNT_LIST_FIN_CTL_SHIFT              (22)
101 
102 // DMAC     DMAC_COUNT     DREQ
103 #define DMAC_DMAC_COUNT_DREQ_MASK               (0x00100000)
104 #define DMAC_DMAC_COUNT_DREQ_LSBMASK            (0x00000001)
105 #define DMAC_DMAC_COUNT_DREQ_SHIFT              (20)
106 
107 // DMAC     DMAC_COUNT     SRST
108 #define DMAC_DMAC_COUNT_SRST_MASK               (0x00080000)
109 #define DMAC_DMAC_COUNT_SRST_LSBMASK            (0x00000001)
110 #define DMAC_DMAC_COUNT_SRST_SHIFT              (19)
111 
112 // DMAC     DMAC_COUNT     LIST_EN
113 #define DMAC_DMAC_COUNT_LIST_EN_MASK            (0x00040000)
114 #define DMAC_DMAC_COUNT_LIST_EN_LSBMASK         (0x00000001)
115 #define DMAC_DMAC_COUNT_LIST_EN_SHIFT           (18)
116 
117 // DMAC     DMAC_COUNT     ENABLE_2D_MODE
118 #define DMAC_DMAC_COUNT_ENABLE_2D_MODE_MASK             (0x00020000)
119 #define DMAC_DMAC_COUNT_ENABLE_2D_MODE_LSBMASK          (0x00000001)
120 #define DMAC_DMAC_COUNT_ENABLE_2D_MODE_SHIFT            (17)
121 
122 // DMAC     DMAC_COUNT     EN
123 #define DMAC_DMAC_COUNT_EN_MASK         (0x00010000)
124 #define DMAC_DMAC_COUNT_EN_LSBMASK              (0x00000001)
125 #define DMAC_DMAC_COUNT_EN_SHIFT                (16)
126 
127 // DMAC     DMAC_COUNT     CNT
128 #define DMAC_DMAC_COUNT_CNT_MASK                (0x0000FFFF)
129 #define DMAC_DMAC_COUNT_CNT_LSBMASK             (0x0000FFFF)
130 #define DMAC_DMAC_COUNT_CNT_SHIFT               (0)
131 
132 #define DMAC_DMAC_PERIPH_OFFSET         (0x0008)
133 #define DMAC_DMAC_PERIPH_STRIDE         (32)
134 #define DMAC_DMAC_PERIPH_NO_ENTRIES             (4)
135 
136 // DMAC     DMAC_PERIPH     ACC_DEL
137 #define DMAC_DMAC_PERIPH_ACC_DEL_MASK           (0xE0000000)
138 #define DMAC_DMAC_PERIPH_ACC_DEL_LSBMASK                (0x00000007)
139 #define DMAC_DMAC_PERIPH_ACC_DEL_SHIFT          (29)
140 
141 // DMAC     DMAC_PERIPH     INCR
142 #define DMAC_DMAC_PERIPH_INCR_MASK              (0x08000000)
143 #define DMAC_DMAC_PERIPH_INCR_LSBMASK           (0x00000001)
144 #define DMAC_DMAC_PERIPH_INCR_SHIFT             (27)
145 
146 // DMAC     DMAC_PERIPH     BURST
147 #define DMAC_DMAC_PERIPH_BURST_MASK             (0x07000000)
148 #define DMAC_DMAC_PERIPH_BURST_LSBMASK          (0x00000007)
149 #define DMAC_DMAC_PERIPH_BURST_SHIFT            (24)
150 
151 // DMAC     DMAC_PERIPH     EXT_SA
152 #define DMAC_DMAC_PERIPH_EXT_SA_MASK            (0x0000000F)
153 #define DMAC_DMAC_PERIPH_EXT_SA_LSBMASK         (0x0000000F)
154 #define DMAC_DMAC_PERIPH_EXT_SA_SHIFT           (0)
155 
156 #define DMAC_DMAC_IRQ_STAT_OFFSET               (0x000C)
157 #define DMAC_DMAC_IRQ_STAT_STRIDE               (32)
158 #define DMAC_DMAC_IRQ_STAT_NO_ENTRIES           (4)
159 
160 // DMAC     DMAC_IRQ_STAT     LIST_FIN
161 #define DMAC_DMAC_IRQ_STAT_LIST_FIN_MASK                (0x00200000)
162 #define DMAC_DMAC_IRQ_STAT_LIST_FIN_LSBMASK             (0x00000001)
163 #define DMAC_DMAC_IRQ_STAT_LIST_FIN_SHIFT               (21)
164 
165 // DMAC     DMAC_IRQ_STAT     LIST_INT
166 #define DMAC_DMAC_IRQ_STAT_LIST_INT_MASK                (0x00100000)
167 #define DMAC_DMAC_IRQ_STAT_LIST_INT_LSBMASK             (0x00000001)
168 #define DMAC_DMAC_IRQ_STAT_LIST_INT_SHIFT               (20)
169 
170 // DMAC     DMAC_IRQ_STAT     TRANSFER_FIN
171 #define DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_MASK            (0x00020000)
172 #define DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_LSBMASK         (0x00000001)
173 #define DMAC_DMAC_IRQ_STAT_TRANSFER_FIN_SHIFT           (17)
174 
175 #define DMAC_DMAC_2D_MODE_OFFSET                (0x0010)
176 #define DMAC_DMAC_2D_MODE_STRIDE                (32)
177 #define DMAC_DMAC_2D_MODE_NO_ENTRIES            (4)
178 
179 // DMAC     DMAC_2D_MODE     REP_COUNT
180 #define DMAC_DMAC_2D_MODE_REP_COUNT_MASK                (0x7FF00000)
181 #define DMAC_DMAC_2D_MODE_REP_COUNT_LSBMASK             (0x000007FF)
182 #define DMAC_DMAC_2D_MODE_REP_COUNT_SHIFT               (20)
183 
184 // DMAC     DMAC_2D_MODE     LINE_ADDR_OFFSET
185 #define DMAC_DMAC_2D_MODE_LINE_ADDR_OFFSET_MASK         (0x000FFC00)
186 #define DMAC_DMAC_2D_MODE_LINE_ADDR_OFFSET_LSBMASK              (0x000003FF)
187 #define DMAC_DMAC_2D_MODE_LINE_ADDR_OFFSET_SHIFT                (10)
188 
189 // DMAC     DMAC_2D_MODE     ROW_LENGTH
190 #define DMAC_DMAC_2D_MODE_ROW_LENGTH_MASK               (0x000003FF)
191 #define DMAC_DMAC_2D_MODE_ROW_LENGTH_LSBMASK            (0x000003FF)
192 #define DMAC_DMAC_2D_MODE_ROW_LENGTH_SHIFT              (0)
193 
194 #define DMAC_DMAC_PERIPHERAL_ADDR_OFFSET                (0x0014)
195 #define DMAC_DMAC_PERIPHERAL_ADDR_STRIDE                (32)
196 #define DMAC_DMAC_PERIPHERAL_ADDR_NO_ENTRIES            (4)
197 
198 // DMAC     DMAC_PERIPHERAL_ADDR     ADDR
199 #define DMAC_DMAC_PERIPHERAL_ADDR_ADDR_MASK             (0x007FFFFF)
200 #define DMAC_DMAC_PERIPHERAL_ADDR_ADDR_LSBMASK          (0x007FFFFF)
201 #define DMAC_DMAC_PERIPHERAL_ADDR_ADDR_SHIFT            (0)
202 
203 #define DMAC_DMAC_PER_HOLD_OFFSET               (0x0018)
204 #define DMAC_DMAC_PER_HOLD_STRIDE               (32)
205 #define DMAC_DMAC_PER_HOLD_NO_ENTRIES           (4)
206 
207 // DMAC     DMAC_PER_HOLD     PER_HOLD
208 #define DMAC_DMAC_PER_HOLD_PER_HOLD_MASK                (0x0000007F)
209 #define DMAC_DMAC_PER_HOLD_PER_HOLD_LSBMASK             (0x0000007F)
210 #define DMAC_DMAC_PER_HOLD_PER_HOLD_SHIFT               (0)
211 
212 #define DMAC_DMAC_SOFT_RESET_OFFSET             (0x0080)
213 
214 
215 
216 #ifdef __cplusplus
217 }
218 #endif
219 
220 #endif /* __MSVDX_DMAC_REGS_IO2_H__ */
221