1 /*++
2 
3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
4 
5 
6   This program and the accompanying materials are licensed and made available under
7 
8   the terms and conditions of the BSD License that accompanies this distribution.
9 
10   The full text of the license may be found at
11 
12   http://opensource.org/licenses/bsd-license.php.
13 
14 
15 
16   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 
18   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 
20 
21 
22 
23 
24 
25 Module Name:
26 
27   PlatformInfo.h
28 
29 Abstract:
30 
31   GUID used for Platform Info Data entries in the HOB list.
32 
33 --*/
34 
35 #ifndef _PLATFORM_INFO_GUID_H_
36 #define _PLATFORM_INFO_GUID_H_
37 
38 #ifndef ECP_FLAG
39 #include <PiPei.h>
40 
41 #include <Library/HobLib.h>
42 #include <Library/IoLib.h>
43 #include <Library/DebugLib.h>
44 #include <Library/SmbusLib.h>
45 #include <IndustryStandard/SmBus.h>
46 #endif
47 
48 #define PLATFORM_INFO_REVISION = 1      // Revision id for current platform information struct.
49 
50 //
51 // Start::BayLake Board Defines
52 //
53 #define BOARD_REVISION_DEFAULT = 0xff
54 #define UNKNOWN_FABID		0x0F
55 #define FAB_ID_MASK			0x0F
56 #define BOARD_ID_2   0x01
57 #define BOARD_ID_1   0x40
58 #define BOARD_ID_0   0x04
59 
60 #define BOARD_ID_DT_CRB     0x0
61 #define BOARD_ID_DT_VLVR    0x1
62 #define BOARD_ID_SVP_VLV    0xC
63 #define BOARD_ID_SVP_EV_VLV 0xD
64 //
65 // End::BayLake Board Defines
66 //
67 
68 //
69 // Start::Alpine Valley Board Defines
70 //
71 #define DC_ID_DDR3L      0x00
72 #define DC_ID_DDR3       0x04
73 #define DC_ID_LPDDR3     0x02
74 #define DC_ID_LPDDR2     0x06
75 #define DC_ID_DDR4       0x01
76 #define DC_ID_DDR3L_ECC  0x05
77 #define DC_ID_NO_MEM     0x07
78 //
79 // End::Alpine Valley Board Defines
80 //
81 
82 #define MAX_FAB_ID_RETRY_COUNT  100
83 #define MAX_FAB_ID_CHECK_COUNT  3
84 
85 #define PLATFORM_INFO_HOB_REVISION	0x1
86 
87 #define EFI_PLATFORM_INFO_GUID \
88   { \
89     0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
90   }
91 
92 extern EFI_GUID gEfiPlatformInfoGuid;
93 
94 typedef enum {
95   FlavorUnknown = 0,
96 
97   //
98   // Mobile
99   //
100   FlavorMobile = 1,
101 
102   //
103   // Desktop
104   //
105   FlavorDesktop = 2,
106 
107   //
108   // Tablet
109   //
110   FlavorTablet = 3
111 } PLATFORM_FLAVOR;
112 
113 #pragma pack(1)
114 
115 typedef struct {
116   UINT16  PciResourceIoBase;
117   UINT16  PciResourceIoLimit;
118   UINT32  PciResourceMem32Base;
119   UINT32  PciResourceMem32Limit;
120   UINT64  PciResourceMem64Base;
121   UINT64  PciResourceMem64Limit;
122   UINT64  PciExpressBase;
123   UINT32  PciExpressSize;
124   UINT8   PciHostAddressWidth;
125   UINT8   PciResourceMinSecBus;
126 } EFI_PLATFORM_PCI_DATA;
127 
128 typedef struct {
129   UINT8 CpuAddressWidth;
130   UINT32 CpuFamilyStepping;
131 } EFI_PLATFORM_CPU_DATA;
132 
133 typedef struct {
134   UINT8 SysIoApicEnable;
135   UINT8 SysSioExist;
136 } EFI_PLATFORM_SYS_DATA;
137 
138 typedef struct {
139   UINT32  MemTolm;
140   UINT32  MemMaxTolm;
141   UINT32  MemTsegSize;
142   UINT32  MemTsegBase;
143   UINT32  MemIedSize;
144   UINT32  MemIgdSize;
145   UINT32  MemIgdBase;
146   UINT32  MemIgdGttSize;
147   UINT32  MemIgdGttBase;
148   UINT64  MemMir0;
149   UINT64  MemMir1;
150   UINT32  MemConfigSize;
151   UINT16  MmioSize;
152   UINT8   DdrFreq;
153   UINT8   DdrType;
154   UINT32  MemSize;
155   BOOLEAN EccSupport;
156   UINT8   Reserved[3];
157   UINT16  DimmSize[2];
158 } EFI_PLATFORM_MEM_DATA;
159 
160 
161 typedef struct {
162   UINT32 IgdOpRegionAddress;    // IGD OpRegion Starting Address
163   UINT8  IgdBootType;           // IGD Boot Display Device
164   UINT8  IgdPanelType;          // IGD Panel Type CMOs option
165   UINT8  IgdTvFormat;           // IGD TV Format CMOS option
166   UINT8  IgdTvMinor;            // IGD TV Minor Format CMOS option
167   UINT8  IgdPanelScaling;       // IGD Panel Scaling
168   UINT8  IgdBlcConfig;          // IGD BLC Configuration
169   UINT8  IgdBiaConfig;          // IGD BIA Configuration
170   UINT8  IgdSscConfig;          // IGD SSC Configuration
171   UINT8  IgdDvmtMemSize;        // IGD DVMT Memory Size
172   UINT8  IgdFunc1Enable;        // IGD Function 1 Enable
173   UINT8  IgdHpllVco;            // HPLL VCO
174   UINT8  IgdSciSmiMode;         // GMCH SMI/SCI mode (0=SCI)
175   UINT8  IgdPAVP;               // IGD PAVP data
176 } EFI_PLATFORM_IGD_DATA;
177 
178 typedef enum {
179   BOARD_ID_AV_SVP   = 0x0,    // Alpine Valley Board
180   BOARD_ID_BL_RVP   = 0x2,    // BayLake Board (RVP)
181   BOARD_ID_BL_FFRD8 = 0x3,    // FFRD8 b'0011
182   BOARD_ID_BL_FFRD  = 0x4,    // BayLake Board (FFRD)
183   BOARD_ID_BL_RVP_DDR3L  = 0x5,    // BayLake Board (RVP DDR3L)
184   BOARD_ID_BL_STHI  = 0x7,    // PPV- STHI Board
185   BOARD_ID_BB_RVP   = 0x20,   // Bayley Bay Board
186   BOARD_ID_BS_RVP   = 0x30,   // Bakersport Board
187   BOARD_ID_CVH      = 0x90,   // Crestview Hills
188   BOARD_ID_MINNOW2  = 0xA0,    // MinnowBorad Max
189   BOARD_ID_MINNOW2_TURBOT  = 0xB0    // MinnowBoard Turbot
190 
191 } BOARD_ID_LIST;
192 
193 typedef enum {
194   FAB1 = 0,
195   FAB2 = 1,
196   FAB3 = 2
197 } FAB_ID_LIST;
198 
199 typedef enum {
200     PR0  = 0,   // FFRD PR0
201     PR05 = 1,   // FFRD PR0.3 and PR 0.5
202     PR1  = 2,   // FFRD PR1
203     PR11 = 3    // FFRD PR1.1
204 } FFRD_ID_LIST;
205 
206 
207 //
208 // VLV2 GPIO GROUP OFFSET
209 //
210 #define GPIO_SCORE_OFFSET	0x0000
211 #define GPIO_NCORE_OFFSET	0x1000
212 #define GPIO_SSUS_OFFSET	0x2000
213 
214 //
215 // GPIO Initialization Data Structure for BayLake.
216 // SC = SCORE, SS= SSUS
217 // Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
218 //
219 
220 //
221 // IO space
222 //
223 typedef struct{
224   UINT32  Use_Sel_SC0;
225   UINT32  Use_Sel_SC1;
226   UINT32  Use_Sel_SC2;
227   UINT32  Use_Sel_SS;
228 
229   UINT32  Io_Sel_SC0;
230   UINT32  Io_Sel_SC1;
231   UINT32  Io_Sel_SC2;
232   UINT32  Io_Sel_SS;
233 
234   UINT32  GP_Lvl_SC0;
235   UINT32  GP_Lvl_SC1;
236   UINT32  GP_Lvl_SC2;
237   UINT32  GP_Lvl_SS;
238 
239   UINT32  TPE_SC0;
240   UINT32  TPE_SS;
241 
242   UINT32  TNE_SC0;
243   UINT32  TNE_SS;
244 
245   UINT32  TS_SC0;
246   UINT32  TS_SS;
247 
248   UINT32  WE_SS;
249 } CFIO_INIT_STRUCT;
250 
251 
252 
253 //
254 // CFIO PAD configuration Registers
255 //
256 //
257 // Memory space
258 //
259 typedef union {
260   UINT32 dw;
261   struct {
262     UINT32 Func_Pin_Mux:3;  // 0:2 Function of CFIO selection
263     UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
264     UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
265     UINT32 Pull_assign:2; // 7:8 Pull assignment
266     UINT32 Pull_strength:2; // 9:10 Pull strength
267     UINT32 Bypass_flop:1; // 11 Bypass flop
268     UINT32 Filter_en:1; // 12 Filter Enable
269     UINT32 Hist_ctrl:2; // 13:14 hysteresis control
270     UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
271     UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
272     UINT32 Reserved:3; // 22:24 Reserved
273     UINT32 TPE:1; // 25 Trigger Positive Edge Enable
274     UINT32 TNE:1; // 26 Trigger Negative Edge Enable
275     UINT32 Reserved2:3; // 27:29 Reserved
276     UINT32 i1p5sel:1; // 30
277     UINT32 IODEN:1; // 31 : Open Drain enable. Active high
278 	} r;
279 } PAD_CONF0;
280 
281 typedef union{
282   UINT32 dw;
283   struct {
284     UINT32 instr:16; // 0:15 Pad (N) strength.
285     UINT32 ipstr:16; // 16:31 Pad (P) strength.
286   }r;
287 } PAD_CONF1;
288 
289 typedef union{
290   UINT32 dw;
291   struct {
292     UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
293     UINT32 ioutenb:1; // 1 output enable
294     UINT32 iinenb:1; // 2 input enable
295     UINT32 Reserved:29; // 3:31 Reserved
296   }r;
297 } PAD_VAL;
298 
299 typedef union{
300   UINT32 GPI;
301   struct {
302     UINT32 ihbpen:1; // 0 Pad high by pass enable
303     UINT32 ihbpinen:1; // 1 Pad high by pass input
304     UINT32 instaticen:1; // 2 TBD
305     UINT32 ipstaticen:1; // 3 TBD
306     UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
307     UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
308     UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
309   }r;
310 } PAD_DFT;
311 
312 //
313 // GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
314 //
315 typedef enum {
316   Native = 0xFF,  // Native, no need to set PAD_VALUE
317   GPI = 2,    // GPI, input only in PAD_VALUE
318   GPO = 4,    // GPO, output only in PAD_VALUE
319   GPIO = 0,      // GPIO, input & output
320   TRISTS = 6,      // Tri-State
321   GPIO_NONE
322 } GPIO_USAGE;
323 
324 typedef enum {
325   LO = 0,
326   HI = 1,
327   NA = 0xFF
328 } GPO_D4;
329 
330 typedef enum {
331   F0 = 0,
332   F1 = 1,
333   F2 = 2,
334   F3 = 3,
335   F4 = 4,
336   F5 = 5,
337   F6 = 6,
338   F7 = 7
339 } GPIO_FUNC_NUM;
340 
341 //
342 // Mapping to CONF0 bit 27:24
343 // Note: Assume "Direct Irq En" is not set, unless specially notified.
344 //
345 typedef enum {
346   TRIG_ = 0,
347   TRIG_Edge_High = /*BIT3 |*/ BIT1,	// Positive Edge (Rasing)
348   TRIG_Edge_Low  = /*BIT3 |*/ BIT2,	// Negative Edge (Falling)
349   TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1,	// Both Edge
350   TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0,	// Level High
351   TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0,	// Level Low
352 } INT_TYPE;
353 
354 typedef enum {
355   P_20K_H,	// Pull Up 20K
356   P_20K_L,	// Pull Down 20K
357   P_10K_H,	// Pull Up 10K
358   P_10K_L,	// Pull Down 10K
359   P_2K_H,	// Pull Up 2K
360   P_2K_L,	// Pull Down 2K
361   P_NONE      // Pull None
362 } PULL_TYPE;
363 
364 #ifdef EFI_DEBUG
365   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
366 #else
367   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {          usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
368 #endif
369 
370 //
371 // GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
372 // NC = NCORE, SC = SCORE, SS= SSUS
373 //
374 typedef struct {
375 
376 #ifdef EFI_DEBUG
377   char         pad_name[32];// GPIO Pin Name for debug purpose
378 #endif
379 
380   GPIO_USAGE     usage;     // GPIO pin used as Native mode or GPI/GPO/GPIO mode
381   GPO_D4         gpod4;     // GPO default value
382   GPIO_FUNC_NUM  func;      // Function Number (F0~F7)
383   INT_TYPE       int_type;  // Edge or Level trigger, low or high active
384   PULL_TYPE      pull;      // Pull Up or Down
385   UINT8          offset;    // Equal with (PCONF0 register offset >> 4 bits)
386 } GPIO_CONF_PAD_INIT;
387 
388 //
389 //typedef UINT64 BOARD_FEATURES
390 //
391 typedef struct _EFI_PLATFORM_INFO_HOB {
392   UINT16                      PlatformType; // Platform Type
393   UINT8                       BoardId;             // Board ID
394   UINT8                       BoardRev;            // Board Revision
395   PLATFORM_FLAVOR             PlatformFlavor;      // Platform Flavor
396   UINT8                       DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
397   UINT8                       DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
398   UINT8                       ECOId;               // ECO applied on platform
399   UINT16                      IohSku;
400   UINT8                       IohRevision;
401   UINT16                      IchSku;
402   UINT8                       IchRevision;
403   EFI_PLATFORM_PCI_DATA       PciData;
404   EFI_PLATFORM_CPU_DATA       CpuData;
405   EFI_PLATFORM_MEM_DATA       MemData;
406   EFI_PLATFORM_SYS_DATA       SysData;
407   EFI_PLATFORM_IGD_DATA       IgdData;
408   UINT8                       RevisonId;           // Structure Revision ID
409   EFI_PHYSICAL_ADDRESS        PlatformCfioData;
410   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC;
411   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC;
412   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS;
413   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC_TRI;
414   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_TRI;
415   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_TRI;
416   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1;
417   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_PR1_1;
418   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1_1;
419 
420   UINT8                       CfioEnabled;
421   UINT32                      SsidSvid;
422   UINT16                      AudioSubsystemDeviceId;
423   UINT64                      AcpiOemId;
424   UINT64                      AcpiOemTableId;
425   UINT16                      MemCfgID;
426 } EFI_PLATFORM_INFO_HOB;
427 
428 #pragma pack()
429 
430 EFI_STATUS
431 GetPlatformInfoHob (
432   IN CONST EFI_PEI_SERVICES           **PeiServices,
433   OUT EFI_PLATFORM_INFO_HOB           **PlatformInfoHob
434   );
435 
436 
437 EFI_STATUS
438 InstallPlatformClocksNotify (
439   IN CONST EFI_PEI_SERVICES           **PeiServices
440   );
441 
442 EFI_STATUS
443 InstallPlatformSysCtrlGPIONotify (
444   IN CONST EFI_PEI_SERVICES           **PeiServices
445   );
446 
447 #endif
448