1 /*
2  * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
3  * Copyright (c) Imagination Technologies Limited, UK
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial portions
15  * of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *    Edward Lin <edward.lin@intel.com>
27  *
28  */
29 #ifndef _TNG_HOSTDEFS_H_
30 #define _TNG_HOSTDEFS_H_
31 
32 #include "img_types.h"
33 #include "hwdefs/coreflags.h"
34 
35 #define FORCED_REFERENCE 1
36 #define LTREFHEADER 1
37 
38 #define MIN_30_REV 0x00030000
39 #define MAX_30_REV 0x00030099
40 #define MIN_32_REV 0x00030200
41 #define MAX_32_REV 0x00030299
42 #define MIN_34_REV 0x00030400
43 #define MAX_34_REV 0x00030499
44 #define MIN_36_REV 0x00030600
45 #define MAX_36_REV 0x00030699
46 
47 #define MVEA_MV_PARAM_REGION_SIZE 16
48 #define MVEA_ABOVE_PARAM_REGION_SIZE 96
49 
50 #define ALIGN_64(X)  (((X)+63) &~63)
51 #define ALIGN_4(X)  (((X)+3) &~3)
52 
53 #define MTX_CONTEXT_SIZE (10 * 1024)
54 
55 
56 #define SHIFT_GOP_FRAMETYPE		(0)
57 #define MASK_GOP_FRAMETYPE		(0x3 << SHIFT_GOP_FRAMETYPE)
58 #define SHIFT_GOP_REFERENCE		(2)
59 #define MASK_GOP_REFERENCE		(0x1 << SHIFT_GOP_REFERENCE)
60 #define SHIFT_GOP_POS			(3)
61 #define MASK_GOP_POS			(0x1f << SHIFT_GOP_POS)
62 #define SHIFT_GOP_LEVEL			(4)
63 #define MASK_GOP_LEVEL			(0xF << SHIFT_GOP_LEVEL)
64 #define SHIFT_GOP_REF0			(0 + 8)
65 #define MASK_GOP_REF0			(0xf << SHIFT_GOP_REF0)
66 #define SHIFT_GOP_REF1			(4 + 8)
67 #define MASK_GOP_REF1			(0xf << SHIFT_GOP_REF1)
68 /**********************************************************************************************************/
69 
70 #define MTX_CMDID_PRIORITY 0x80
71 #define MV_ROW_STRIDE ((sizeof(IMG_MV_SETTINGS) * MAX_BFRAMES + 63) & ~63)
72 #define MV_OFFSET_IN_TABLE(BDistance, Position) ((BDistance) * MV_ROW_STRIDE + (Position) * sizeof(IMG_MV_SETTINGS))
73 
74 //Edward FIXME
75 #define MAX_GOP_SIZE    (MAX_BFRAMES + 1)
76 #define MV_ROW_STRIDE ((sizeof(IMG_MV_SETTINGS) * MAX_BFRAMES + 63) & ~63)
77 #define MV_ROW2 ((MAX_BFRAMES) * (MAX_BFRAMES) + 1)
78 
79 /* Specific to Standard Latency */
80 
81 //details   Sizes for arrays that depend on reference usage pattern
82 //brief      Reference usage
83 #define MAX_REF_B_LEVELS       3
84 #define MAX_REF_SPACING        1
85 #define MAX_REF_I_OR_P_LEVELS  (MAX_REF_SPACING + 2)
86 #define MAX_REF_LEVELS         (MAX_REF_B_LEVELS + MAX_REF_I_OR_P_LEVELS)
87 #define MAX_PIC_NODES          (MAX_REF_LEVELS + 2)
88 #define MAX_MV                 (MAX_PIC_NODES * 2)
89 
90 #define MAX_BFRAMES            7
91 #define MAX_GOP_SIZE           (MAX_BFRAMES + 1)
92 #define MAX_SOURCE_SLOTS_SL    (MAX_GOP_SIZE + 1)
93 
94 
95 //brief      WB FIFO
96 #define LOG2_WB_FIFO_SIZE      ( 5 )
97 
98 #define WB_FIFO_SIZE           ( 1 << (LOG2_WB_FIFO_SIZE) )
99 
100 #define SHIFT_WB_PRODUCER      ( 0 )
101 #define MASK_WB_PRODUCER       ( ((1 << LOG2_WB_FIFO_SIZE) - 1) << SHIFT_WB_PRODUCER )
102 
103 #define SHIFT_WB_CONSUMER      ( 0 )
104 #define MASK_WB_CONSUMER       ( ((1 << LOG2_WB_FIFO_SIZE) - 1) << SHIFT_WB_CONSUMER )
105 
106 /*****************************************************************************/
107 #define SCALE_TBL_SZ            (8)
108 #define TOPAZHP_NUM_PIPES       (2)
109 #define TNG_HEADER_SIZE         (128)
110 #define NUM_SLICE_TYPES         (5)
111 /*****************************************************************************/
112 #define SHIFT_MTX_MSG_CMD_ID          (0)
113 #define MASK_MTX_MSG_CMD_ID           (0x7f << SHIFT_MTX_MSG_CMD_ID)
114 #define SHIFT_MTX_MSG_PRIORITY        (7)
115 #define MASK_MTX_MSG_PRIORITY         (0x1 << SHIFT_MTX_MSG_PRIORITY)
116 #define SHIFT_MTX_MSG_CORE            (8)
117 #define MASK_MTX_MSG_CORE             (0xff << SHIFT_MTX_MSG_CORE)
118 #define SHIFT_MTX_MSG_COUNT           (16)
119 #define MASK_MTX_MSG_COUNT            (0xffff << SHIFT_MTX_MSG_COUNT)
120 #define SHIFT_MTX_MSG_MESSAGE_ID      (16)
121 #define MASK_MTX_MSG_MESSAGE_ID       (0xff << SHIFT_MTX_MSG_MESSAGE_ID)
122 /*****************************************************************************/
123 #define SHIFT_MTX_MSG_PICMGMT_SUBTYPE           (0)
124 #define MASK_MTX_MSG_PICMGMT_SUBTYPE            (0xff << SHIFT_MTX_MSG_PICMGMT_SUBTYPE)
125 #define SHIFT_MTX_MSG_PICMGMT_DATA              (8)
126 #define MASK_MTX_MSG_PICMGMT_DATA               (0xffffff << SHIFT_MTX_MSG_PICMGMT_DATA)
127 
128 #define SHIFT_MTX_MSG_RC_UPDATE_QP              (0)
129 #define MASK_MTX_MSG_RC_UPDATE_QP               (0x3f << SHIFT_MTX_MSG_RC_UPDATE_QP)
130 #define SHIFT_MTX_MSG_RC_UPDATE_BITRATE         (6)
131 #define MASK_MTX_MSG_RC_UPDATE_BITRATE          (0x03ffffff << SHIFT_MTX_MSG_RC_UPDATE_BITRATE)
132 
133 #define SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_USE    (0)
134 #define MASK_MTX_MSG_PROVIDE_REF_BUFFER_USE     (0xff << SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_USE)
135 #define SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_SLOT   (8)
136 #define MASK_MTX_MSG_PROVIDE_REF_BUFFER_SLOT    (0xff << SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_SLOT)
137 #define SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_LT     (16)
138 #define MASK_MTX_MSG_PROVIDE_REF_BUFFER_LT      (0xff << SHIFT_MTX_MSG_PROVIDE_REF_BUFFER_LT)
139 
140 #define SHIFT_MTX_MSG_PROVIDE_CODED_BUFFER_SLOT (0)
141 #define MASK_MTX_MSG_PROVIDE_CODED_BUFFER_SLOT  (0x0f << SHIFT_MTX_MSG_PROVIDE_CODED_BUFFER_SLOT)
142 #define SHIFT_MTX_MSG_PROVIDE_CODED_BUFFER_SIZE (4)
143 #define MASK_MTX_MSG_PROVIDE_CODED_BUFFER_SIZE  (0x0fffffff << SHIFT_MTX_MSG_PROVIDE_CODED_BUFFER_SLOT)
144 
145 #define SHIFT_MTX_MSG_RC_UPDATE_MIN_QP                  (0)
146 #define MASK_MTX_MSG_RC_UPDATE_MIN_QP                   (0x3f << SHIFT_MTX_MSG_RC_UPDATE_MIN_QP)
147 #define SHIFT_MTX_MSG_RC_UPDATE_MAX_QP                  (6)
148 #define MASK_MTX_MSG_RC_UPDATE_MAX_QP                   (0x3f << SHIFT_MTX_MSG_RC_UPDATE_MAX_QP)
149 #define SHIFT_MTX_MSG_RC_UPDATE_INTRA                   (12)
150 #define MASK_MTX_MSG_RC_UPDATE_INTRA                    (0xffff << SHIFT_MTX_MSG_RC_UPDATE_INTRA)
151 
152 #define RC_MASK_frame_width        (1<<0)
153 #define RC_MASK_frame_height       (1<<1)
154 #define RC_MASK_bits_per_second    (1<<2)
155 #define RC_MASK_target_percentage  (1<<3)
156 #define RC_MASK_window_size        (1<<4)
157 #define RC_MASK_initial_qp         (1<<5)
158 #define RC_MASK_min_qp             (1<<6)
159 #define RC_MASK_force_kf           (1<<7)
160 #define RC_MASK_no_ref_last        (1<<8)
161 #define RC_MASK_no_ref_gf          (1<<9)
162 #define RC_MASK_no_ref_arf         (1<<10)
163 #define RC_MASK_frame_rate         (1<<11)
164 #define RC_MASK_intra_period       (1<<12)
165 #define RC_MASK_intra_idr_period   (1<<13)
166 #define RC_MASK_ip_period          (1<<14)
167 #define RC_MASK_quality            (1<<15)
168 #define RC_MASK_refresh_entropy_probs    (1<<16)
169 #define RC_MASK_copy_buffer_to_golden    (1<<17)
170 #define RC_MASK_copy_buffer_to_alternate (1<<18)
171 #define RC_MASK_refresh_last             (1<<19)
172 #define RC_MASK_refresh_golden_frame     (1<<20)
173 #define RC_MASK_refresh_alternate_frame  (1<<21)
174 #define RC_MASK_max_qp             (1<<22)
175 
176 /*!
177  *****************************************************************************
178  *
179  * @details
180  *
181  * Enum describing Command IDs.  Some commands require data to be DMA'd in
182  * from the Host, with the base address of the data specified in the Command
183  * Data Address word of the command.  The data required is specified with each
184  * command type.
185  *
186  * @brief          Command IDs
187  *
188  ****************************************************************************/
189 typedef enum {
190 	// Common Commands
191     MTX_CMDID_NULL,                   //!< (no data)\n Null command does nothing\n
192     MTX_CMDID_SHUTDOWN,               //!< (no data)\n shutdown the MTX\n
193 
194     // Video Commands
195     MTX_CMDID_DO_HEADER,              //!< (extra data: #MTX_HEADER_PARAMS)\n Command for Sequence, Picture and Slice headers\n
196     MTX_CMDID_ENCODE_FRAME,           //!< (no data)\n Encode frame data\n
197     MTX_CMDID_START_FRAME,            //!< (no data)\n Prepare to encode frame\n
198     MTX_CMDID_ENCODE_SLICE,           //!< (no data)\n Encode slice data\n
199     MTX_CMDID_END_FRAME,              //!< (no data)\n Complete frame encoding\n
200     MTX_CMDID_SETVIDEO,               //!< (data: pipe number, extra data: #IMG_MTX_VIDEO_CONTEXT)\n Set MTX Video Context\n
201     MTX_CMDID_GETVIDEO,               //!< (data: pipe number, extra data: #IMG_MTX_VIDEO_CONTEXT)\n Get MTX Video Context\n
202     MTX_CMDID_DO_CHANGE_PIPEWORK,     //!< (data: new pipe allocations for the context)\n Change pipe allocation for a Video Context\n
203     MTX_CMDID_PICMGMT,                //!< (data: subtype and parameters, extra data: #IMG_PICMGMT_CUSTOM_QUANT_DATA (optional))\n Change encoding parameters\n
204     MTX_CMDID_RC_UPDATE,              //!< (data: QP and bitrate)\n Change encoding parameters\n
205     MTX_CMDID_PROVIDE_SOURCE_BUFFER,  //!< (extra data: #IMG_SOURCE_BUFFER_PARAMS)\n Transfer source buffer from host\n
206     MTX_CMDID_PROVIDE_REF_BUFFER,     //!< (data: buffer parameters, extra data: reference buffer)\n Transfer reference buffer from host\n
207     MTX_CMDID_PROVIDE_CODED_BUFFER,   //!< (data: slot and size, extra data: coded buffer)\n Transfer output buffer from host\n
208     MTX_CMDID_ABORT,                  //!< (no data)\n Stop encoding and release all buffers\n
209 
210     // JPEG commands
211     MTX_CMDID_SETQUANT,	             //!< (extra data: #JPEG_MTX_QUANT_TABLE)\n
212     MTX_CMDID_SETUP_INTERFACE,       //!< (extra data: #JPEG WRITEBACK POINTERS)\n
213     MTX_CMDID_ISSUEBUFF,             //!< (extra data: #MTX_ISSUE_BUFFERS)\n
214     MTX_CMDID_SETUP,                 //!< (extra data: #JPEG_MTX_DMA_SETUP)\n\n
215 
216     MTX_CMDID_ENDMARKER,             //!< end marker for enum
217 
218     /* SW Commands */
219     MTX_CMDID_PAD = 0x7a,           //!< Will be ignored by kernel
220     MTX_CMDID_SW_WRITEREG = 0x7b,
221     MTX_CMDID_SW_LEAVE_LOWPOWER = 0x7c,
222     MTX_CMDID_SW_ENTER_LOWPOWER = 0x7e,
223     MTX_CMDID_SW_NEW_CODEC = 0x7f,
224     MTX_CMDID_SW_FILL_INPUT_CTRL = 0x81,
225     MTX_CMDID_SW_UPDATE_AIR_SEND = 0x82,
226     MTX_CMDID_SW_AIR_BUF_CLEAR = 0x83,
227     MTX_CMDID_SW_UPDATE_AIR_CALC = 0x84
228 } tng_MTX_CMD_ID;
229 
230 
231 /*!
232  *****************************************************************************
233  * @details    Enum describing MTX firmware version (codec and rate control)
234  * @brief          Firmware version
235  ****************************************************************************/
236 typedef enum
237 {
238     IMG_CODEC_JPEG = 0,    /* !< JPEG */
239     IMG_CODEC_H264_NO_RC,  /* !< H264 with no rate control */
240     IMG_CODEC_H264_VBR,    /* !< H264 variable bitrate */
241     IMG_CODEC_H264_CBR,    /* !< H264 constant bitrate */
242     IMG_CODEC_H264_VCM,    /* !< H264 video conferance mode */
243     IMG_CODEC_H264_LLRC,   /* !< H264 low-latency rate control */
244     IMG_CODEC_H264_ALL_RC, /* !< H264 with multiple rate control modes */
245     IMG_CODEC_H263_NO_RC,  /* !< H263 with no rate control */
246     IMG_CODEC_H263_VBR,    /* !< H263 variable bitrate */
247     IMG_CODEC_H263_CBR,    /* !< H263 constant bitrate */
248     IMG_CODEC_MPEG4_NO_RC, /* !< MPEG4 with no rate control */
249     IMG_CODEC_MPEG4_VBR,   /* !< MPEG4 variable bitrate */
250     IMG_CODEC_MPEG4_CBR,   /* !< MPEG4 constant bitrate */
251     IMG_CODEC_MPEG2_NO_RC, /* !< MPEG2 with no rate control */
252     IMG_CODEC_MPEG2_VBR,   /* !< MPEG2 variable bitrate */
253     IMG_CODEC_MPEG2_CBR,   /* !< MPEG2 constant bitrate */
254     IMG_CODEC_H264MVC_NO_RC, /* !< MVC H264 with no rate control */
255     IMG_CODEC_H264MVC_CBR, /* !< MVC H264 constant bitrate */
256     IMG_CODEC_H264MVC_VBR, /* !< MVC H264 variable bitrate */
257     IMG_CODEC_NUM
258 } IMG_CODEC;
259 
260 /*!
261  *****************************************************************************
262  * @details    Enum describing encoding standard (codec)
263  * @brief          Encoding standard
264  ****************************************************************************/
265 typedef enum
266 {
267     IMG_STANDARD_NONE = 0,   //!< There is no FW in MTX memory
268     IMG_STANDARD_JPEG,       //!< JPEG
269     IMG_STANDARD_H264,       //!< H264 with no rate control
270     IMG_STANDARD_H263,       //!< H263 with no rate control
271     IMG_STANDARD_MPEG4,      //!< MPEG4 with no rate control
272     IMG_STANDARD_MPEG2       //!< MPEG2 with no rate control
273 } IMG_STANDARD;
274 
275 /*!
276  *****************************************************************************
277  * @details    Enum describing image surface format types
278  * @brief          Image surface format
279  ****************************************************************************/
280 typedef enum
281 {
282     IMG_CODEC_YUV,                  //!< Planar Y U V
283     IMG_CODEC_YV12,                 //!< YV12 format Data
284     IMG_CODEC_IMC2,                 //!< IMC2 format Data
285     IMG_CODEC_PL8,                   //!< PL8 format YUV data
286     IMG_CODEC_PL12,                 //!< PL12 format YUV data
287     IMG_CODEC_422_YUV,           //!< YUV format 422 data
288     IMG_CODEC_422_YV12,          //!< YV12 format 422 data
289     IMG_CODEC_422_PL8,            //!< PL8 format 422 data
290     IMG_CODEC_422_IMC2,          //!< PL8 format 422 data
291     IMG_CODEC_422_PL12,          //!< PL12 format 422 data
292     IMG_CODEC_Y0UY1V_8888,   //!< 422 YUYV data
293     IMG_CODEC_Y0VY1U_8888,   //!< 422 YVYU data
294     IMG_CODEC_UY0VY1_8888,   //!< 422 UYVY data
295     IMG_CODEC_VY0UY1_8888,   //!< 422 VYUY data
296     PVR_SURF_UNSPECIFIED      //!< End of the enum
297 } IMG_FORMAT;
298 
299 /*****************************************************************************
300  * @details    Structure describing coded header data returned by the firmware.
301  *             The size of the structure should not be more than 48-bytes
302  *              (i.e. CODED_BUFFER_HEADER_SIZE)
303  * @brief      Coded header structure
304  ****************************************************************************/
305 typedef struct
306 {
307     IMG_UINT32  ui32BytesWritten;   //!< Bytes in this coded buffer excluding this header
308     IMG_UINT32  ui32Feedback;       //!< Feedback word for this coded buffers
309     IMG_UINT32  ui32ExtraFeedback;  //!< Extra feedback word for this coded buffers
310     IMG_UINT32  ui32HostCtx;            //!< Host context value
311 
312     IMG_UINT16  ui16_I_MbCnt;       //!< Number of MBs coded as I-macroblocks in this slice
313     IMG_UINT16  ui16_P_MbCnt;       //!< Number of MBs coded as P-macroblocks in this slice
314 
315     IMG_UINT16  ui16_B_MbCnt;       //!< Number of MBs coded as B-macroblocks in this slice
316     IMG_UINT16  ui16_Skip_MbCnt;    //!< Number of MBs coded as skipped in this slice
317 
318     IMG_UINT16  ui16_IPCM_MbCnt;    //!< Number of macroblocks coded as IPCM in this slice
319     IMG_UINT8  ui8_InterSumSatdHi;    //!< High 8 bits for the inter sum satd
320     IMG_UINT8  ui8_IntraSumSatdHi;    //!< High 8 bits for the intra sum satd
321 
322     IMG_UINT32  ui32_DC_Bits;       //!< Number of bits use for coding DC coefficients in this slice
323     IMG_UINT32  ui32_MV_Bits;       //!< Number of bits used for coding all Motion vector data in this slice
324     IMG_UINT32  ui32_Symbols_Bits;  //!< Number of bits used for coding all MB level symbols in this slice
325     IMG_UINT32  ui32_Residual_Bits; //!< Number of bits used for coding residual data in all MBs in this slice
326 
327     IMG_UINT32  ui32_QpyInter;      //!< Sum of QPy/Qscale for all Inter-MBs in the slice
328     IMG_UINT32  ui32_QpyIntra;      //!< Sum of QPy/Qscale for all Intra-MBs in the slice
329     IMG_UINT32  ui32_InterSumSatd;  //!< Sum of SATD for all Inter-MBs in the slice
330     IMG_UINT32  ui32_IntraSumSatd;  //!< Sum of SATD for all Intra-MBs in the slice
331     IMG_UINT32  ui32_MVOutputIndex; //!< Index into the motion vector buffers for this frame
332 } CODED_DATA_HDR, *P_CODED_DATA_HDR;
333 
334 /*!
335  ************************************************************
336  *
337  * @details     Mask defines for the -ui8EnableSelStatsFlags variable
338  *
339  * @brief       Selectable first pass and multipass statistics flag values
340  *
341  *************************************************************/
342 #define ESF_FIRST_STAGE_STATS 1
343 #define ESF_MP_BEST_MB_DECISION_STATS 2
344 #define ESF_MP_BEST_MOTION_VECTOR_STATS 4
345 
346 /*!
347 ******************************************************************************
348  @details    Struct describing Bias parameters
349  @brief          Bias parameters
350 ******************************************************************************/
351 typedef struct tag_IMG_BIAS_PARAMS {
352     IMG_UINT32      uLambdaSAD;
353     IMG_UINT32      uLambdaSATD;
354     IMG_UINT32      uLambdaSATDTable;
355 
356 
357     IMG_UINT32      uIPESkipVecBias;
358     IMG_UINT32      uDirectVecBias;
359     IMG_UINT32      uSPESkipVecBias;
360 
361     IMG_UINT32  uisz1;
362     IMG_UINT32  uisz2;
363 
364     IMG_INT32 uzb4;
365     IMG_INT32 uzb8;
366 
367     IMG_UINT32  uTHInter;
368     IMG_UINT32  uTHInterQP;
369     IMG_UINT32  uTHInterMaxLevel;
370     IMG_UINT32  uTHSkipIPE;
371     IMG_UINT32  uTHSkipSPE;
372 
373     IMG_UINT32       iIntra16Bias;
374     IMG_UINT32       iInterMBBias;
375     IMG_UINT32       iInterMBBiasB;
376 
377     IMG_BOOL16      bRCEnable;
378     IMG_BOOL16      bRCBiases;
379     IMG_BOOL16      bZeroDetectionDisable;
380 
381 } IMG_BIAS_PARAMS;
382 
383 #define TOPAZ_PIC_PARAMS_VERBOSE 0
384 
385 #define MAX_SLICES_PER_PICTURE 72
386 #define MAX_TOPAZ_CORES        4
387 #define MAX_TOPAZ_CMD_COUNT    (0x1000)
388 
389 #define MAX_NUM_CORES 2
390 
391 /* defines used for the second 32 bit word of the coded data header */
392 /* The peak bitrate was exceeded for this frame */
393 #define RC_STATUS_FLAG_BITRATE_OVERFLOW 0x00000080
394 /* At least one slice in this frame was larger than the slice limit */
395 #define RC_STATUS_FLAG_SLICE_OVERFLOW   0x00000040
396 /* At least one slice in this frame was large enough for the firmware to try to reduce it by increasing Qp or skipping MBs */
397 #define RC_STATUS_FLAG_LARGE_SLICE           0x00000020
398 #define SKIP_NEXT_FRAME                 0x800   /* The next frame should be skipped */
399 
400 typedef enum _WEIGHTED_BIPRED_IDC_ {
401     WBI_NONE = 0x0,
402     WBI_EXPLICIT,
403     WBI_IMPLICIT
404 } WEIGHTED_BIPRED_IDC;
405 
406 typedef enum _IMG_RCMODE_ {
407     IMG_RCMODE_NONE = 0,
408     IMG_RCMODE_CBR,
409     IMG_RCMODE_VBR,
410     IMG_RCMODE_ERC, //Example Rate Control
411     IMG_RCMODE_VCM
412 } IMG_RCMODE;
413 
414 /*!
415 *****************************************************************************
416 @details    Struct describing rate control params
417 @brief          Rate control parameters
418 ****************************************************************************/
419 typedef struct _RC_PARAMS_ {
420     IMG_UINT32  ui32BitsPerSecond;  //!< Bit rate
421     IMG_UINT32  ui32TransferBitsPerSecond; //!< Transfer rate of encoded data from encoder to the output
422     IMG_UINT32  ui32InitialQp;      //!< Initial QP (only field used by JPEG)
423     IMG_UINT32  ui32BUSize;         //!< Basic unit size
424     IMG_UINT32  ui32FrameRate;
425     IMG_UINT32  ui32BufferSize;
426     IMG_UINT32  ui32IntraFreq;
427     IMG_UINT32  ui32SliceByteLimit;
428     IMG_UINT32  ui32SliceMBLimit;
429     IMG_INT32   i32InitialLevel;
430     IMG_INT32   i32InitialDelay;
431     IMG_UINT16   iMinQP;
432     IMG_UINT16  ui16BFrames;
433     IMG_BOOL16  b16Hierarchical;
434     IMG_BOOL16  bIsH264Codec;
435     IMG_BOOL    bRCEnable;
436     IMG_BOOL    bScDetectDisable;
437     IMG_BOOL    bDisableFrameSkipping;
438     IMG_BOOL    bDisableBitStuffing;
439     IMG_RCMODE  eRCMode;
440     IMG_UINT8   u8Slices;
441     IMG_INT8    i8QCPOffset;
442 
443     IMG_BOOL    bBitrateChanged;
444 } IMG_RC_PARAMS;
445 
446 /*!
447  *****************************************************************************
448  * @details    Struct describing rate control input parameters
449  * @brief          Rate control input parameters
450  ****************************************************************************/
451 typedef struct
452 {
453     IMG_UINT16 ui16MBPerFrm;        //!< Number of MBs Per Frame
454     IMG_UINT16 ui16MBPerBU;         //!< Number of MBs Per BU
455     IMG_UINT16 ui16BUPerFrm;        //!< Number of BUs Per Frame
456 
457     IMG_UINT16 ui16IntraPeriod;       //!< Intra frame frequency
458     IMG_UINT16 ui16BFrames;         //!< B frame frequency
459 
460     IMG_INT32  i32BitsPerFrm;        //!< Bits Per Frame
461     IMG_INT32  i32BitsPerBU;	  //!< Bits Per BU
462 
463     IMG_INT32  i32BitRate;             //!< Bit Rate (bps)
464     IMG_INT32  i32BufferSize;        //!< Size of Buffer (VCM mode: in frames; all other modes: in bits)
465     IMG_INT32  i32InitialLevel;        //!< Initial Level of Buffer
466     IMG_INT32  i32InitialDelay;       //!< Initial Delay of Buffer
467 
468     IMG_BOOL16 bFrmSkipDisable; //!< Disable Frame skipping
469 
470     IMG_UINT8  ui8SeInitQP;          //!< Initial QP for Sequence
471     IMG_UINT8  ui8MinQPVal;        //!< Minimum QP value to use
472     IMG_UINT8  ui8MaxQPVal;       //!< Maximum QP value to use
473 
474     IMG_UINT8  ui8ScaleFactor;     //!< Scale Factor used to limit the range of arithmetic with high resolutions and bitrates
475     IMG_UINT8  ui8MBPerRow;      //!< Number of MBs Per Row
476 
477     union {
478         struct {
479             IMG_INT32   i32TransferRate;    //!< Rate at which bits are sent from encoder to the output after each frame finished encoding
480             IMG_BOOL16  bScDetectDisable;   //!< Disable Scene Change detection
481             IMG_UINT32  ui32RCScaleFactor;  //!< Constant used in rate control = (GopSize/(BufferSize-InitialLevel))*256
482             IMG_BOOL16  bHierarchicalMode;  //!< Flag indicating Hierarchical B Pic or Flat mode rate control
483         } h264;
484         struct {
485             IMG_UINT8   ui8HalfFrameRate;   //!< Half Frame Rate (MP4 only)
486             IMG_UINT8   ui8FCode;           //!< F Code (MP4 only)
487             IMG_INT32   i32BitsPerGOP;	    //!< Bits Per GOP (MP4 only)
488             IMG_BOOL16  bBUSkipDisable;     //!< Disable BU skipping
489             IMG_INT32   i32BitsPerMB;       //!< Bits Per MB
490             IMG_UINT16  ui16AvQPVal;        //!< Average QP in Current Picture
491             IMG_UINT16  ui16MyInitQP;       //!< Initial Quantizer
492         } other;
493     } mode;
494 } IN_RC_PARAMS;
495 
496 typedef enum _frame_type_ {
497     IMG_INTRA_IDR = 0,
498     IMG_INTRA_FRAME,
499     IMG_INTER_P,
500     IMG_INTER_B,
501 } IMG_FRAME_TYPE;
502 
503 typedef struct {
504     IMG_UINT32 ui32Flags;//!< Picture parameter flags
505     IN_RC_PARAMS sInParams;//!< Rate control parameters
506 } PIC_PARAMS;
507 
508 typedef struct tag_IMG_MV_SETTINGS {
509     IMG_UINT32      ui32MVCalc_Below;
510     IMG_UINT32      ui32MVCalc_Colocated;
511     IMG_UINT32      ui32MVCalc_Config;
512 } IMG_MV_SETTINGS;
513 
514 typedef enum {
515     BLK_SZ_16x16 = 0,           //!< Use 16x16 block size for motion search. This is the smallest for h.263
516     BLK_SZ_8x8 = 1,                     //!< Use 'upto' 8x8 block size for motion search. This is the smallest for MPEG-4
517     BLK_SZ_4x4 = 2,                     //!< Use 'upto' 4x4 block size for motion search. This is the smallest for H.264
518     BLK_SZ_DEFAULT = 3  //!< Driver picks the best possible block size for this encode session
519 } IMG_IPE_MINBLOCKSIZE;
520 
521 typedef struct {
522     IMG_BOOL16      bDisableIntra4x4;           //!< Disable Intra 4x4.
523     IMG_BOOL16      bDisableIntra8x8;           //!< Disable Intra 8x8.
524     IMG_BOOL16      bDisableIntra16x16; //!< Disable Intra 16x16.
525     IMG_BOOL16      bDisableInter8x8;           //!< Disable Inter 8x8.
526     IMG_BOOL16      bRestrictInter4x4;          //!< Only one 8x8 block may be divided into 4x4 block per MB
527     IMG_BOOL16      bDisableBPicRef_1;  //!< Don't allow b-picture to refer reference-picture-1
528     IMG_BOOL16      bDisableBPicRef_0;  //!< Don't allow b-picture to refer reference-picture-0
529     IMG_BOOL16      bEnable8x16MVDetect;//!< Enable 8x16 motion vector block size detection
530     IMG_BOOL16      bEnable16x8MVDetect;//!< Enable 16x8 motion vector block size detection
531     IMG_BOOL16      bDisableBFrames;    //!< Disable B-frames in encoded output
532     IMG_IPE_MINBLOCKSIZE    eMinBlkSz;  //!< Smallest block size used for motion search
533 } IMG_ENCODE_FEATURES;
534 
535 typedef enum {
536     ENC_PROFILE_DEFAULT = 0,    //!< Sets features for default video encode
537     ENC_PROFILE_LOWCOMPLEXITY,  //!< Sets features for low complexity video encode
538     ENC_PROFILE_HIGHCOMPLEXITY  //!< Sets features for low delay video encode
539 } IMG_VIDEO_ENC_PROFILE;
540 
541 typedef enum {
542     H264ES_PROFILE_BASELINE = 5,
543     H264ES_PROFILE_MAIN,
544     H264ES_PROFILE_HIGH
545 } IMG_VIDEO_H264ES_PROFILE;
546 
547 #define MAX_SLICESPERPIC                (68)
548 
549 /*!
550  ***********************************************************************************
551  *
552  * Description        : Video encode context
553  *
554  ************************************************************************************/
555 typedef struct tag_IMG_MTX_VIDEO_CONTEXT
556 {
557     IMG_UINT64      ui64ClockDivBitrate; // keep this at the top as it has alignment issues
558 
559     IMG_UINT32      ui32WidthInMbs;                         //!< target output width
560     IMG_UINT32      ui32PictureHeightInMbs;                 //!< target output height
561 
562 #ifdef FORCED_REFERENCE
563     IMG_UINT32      apTmpReconstructured[MAX_PIC_NODES];
564 #endif
565     IMG_UINT32      apReconstructured[MAX_PIC_NODES];
566     IMG_UINT32      apColocated[MAX_PIC_NODES];
567     IMG_UINT32      apMV[MAX_MV];
568     IMG_UINT32      apInterViewMV[2];
569 
570     IMG_UINT32      ui32DebugCRCs;                          //!< Send debug information from Register CRCs to Host with the coded buffer
571 
572     IMG_UINT32      apWritebackRegions[WB_FIFO_SIZE];       //!< Data section
573 
574     IMG_UINT32      ui32InitialCPBremovaldelayoffset;
575     IMG_UINT32      ui32MaxBufferMultClockDivBitrate;
576     IMG_UINT32      pSEIBufferingPeriodTemplate;
577     IMG_UINT32      pSEIPictureTimingTemplate;
578 
579     IMG_BOOL16      b16EnableMvc;
580     IMG_UINT16      ui16MvcViewIdx;
581     IMG_UINT32      apSliceParamsTemplates[5];
582     IMG_UINT32      apPicHdrTemplates[4];
583 
584     IMG_UINT32      apSeqHeader;
585     IMG_UINT32      apSubSetSeqHeader;
586     IMG_BOOL16      b16NoSequenceHeaders;
587 
588     IMG_UINT32      aui32SliceMap[MAX_SOURCE_SLOTS_SL];     //!< Slice map of the source picture
589 
590     IMG_UINT32      ui32FlatGopStruct;                      //!< Address of Flat MiniGop structure
591 
592     IMG_BOOL8       b8WeightedPredictionEnabled;
593     IMG_UINT8       ui8MTXWeightedImplicitBiPred;
594     IMG_UINT32      aui32WeightedPredictionVirtAddr[MAX_SOURCE_SLOTS_SL];
595 
596     IMG_UINT32      ui32HierarGopStruct;                    //!< Address of hierarchical MiniGop structure
597 
598     IMG_UINT32      pFirstPassOutParamAddr[MAX_SOURCE_SLOTS_SL];                //!< Output Parameters of the First Pass
599 #ifndef EXCLUDE_BEST_MP_DECISION_DATA
600     IMG_UINT32      pFirstPassOutBestMultipassParamAddr[MAX_SOURCE_SLOTS_SL];   //!< Selectable Output Best MV Parameters data of the First Pass
601 #endif
602     IMG_UINT32      pMBCtrlInParamsAddr[MAX_SOURCE_SLOTS_SL];                   //!< Input Parameters to the second pass
603 
604     IMG_UINT32      ui32InterIntraScale[SCALE_TBL_SZ];
605     IMG_UINT32      ui32SkippedCodedScale[SCALE_TBL_SZ];
606 
607     IMG_UINT32      ui32PicRowStride;                       //!< Strides of source Y data and chroma data
608 
609     IMG_UINT32      apAboveParams[TOPAZHP_NUM_PIPES];       //!< Picture level parameters (supplied by driver)
610 
611     IMG_UINT32      ui32IdrPeriod;
612     IMG_UINT32      ui32IntraLoopCnt;
613     IMG_UINT32      ui32BFrameCount;
614     IMG_BOOL8       b8Hierarchical;
615     IMG_UINT8       ui8MPEG2IntraDCPrecision;               //!< Only used in MPEG2, 2 bit field (0 = 8 bit, 1 = 9 bit, 2 = 10 bit and 3=11 bit precision). Set to zero for other encode standards.
616     IMG_UINT8       aui8PicOnLevel[MAX_REF_LEVELS];
617 
618     IMG_UINT32      ui32VopTimeResolution;
619 
620     IMG_UINT32      ui32InitialQp;                          //!< Initial QP (only field used by JPEG)
621     IMG_UINT32      ui32BUSize;                             //!< Basic unit size
622 
623     IMG_MV_SETTINGS sMVSettingsIdr;
624 
625     IMG_MV_SETTINGS sMVSettingsNonB[MAX_BFRAMES + 1];
626 
627     IMG_UINT32      ui32MVSettingsBTable;
628     IMG_UINT32      ui32MVSettingsHierarchical;
629 #ifdef FIRMWARE_BIAS
630     IMG_UINT32      aui32DirectBias_P[27];
631     IMG_UINT32      aui32InterBias_P[27];
632 
633     IMG_UINT32      aui32DirectBias_B[27];
634     IMG_UINT32      aui32InterBias_B[27];
635 #endif
636 
637     IMG_FORMAT      eFormat;                                //!< Pixel format of the source surface
638     IMG_STANDARD    eStandard;                              //!< Encoder standard (H264 / H263 / MPEG4 / JPEG)
639     IMG_RCMODE      eRCMode;                                //!< RC flavour
640 
641     IMG_BOOL8       b8FirstPic;
642     IMG_BOOL8       b8IsInterlaced;
643     IMG_BOOL8       b8TopFieldFirst;
644     IMG_BOOL8       b8ArbitrarySO;
645     IMG_BOOL8       bOutputReconstructed;
646 
647     IMG_BOOL8       b8DisableBitStuffing;
648 
649     IMG_BOOL8       b8InsertHRDparams;
650 
651     IMG_UINT8       ui8MaxSlicesPerPicture;
652 
653     /* Contents Adaptive Rate Control parameters*/
654     IMG_BOOL16      bCARC;
655     IMG_INT32       iCARCBaseline;
656     IMG_UINT32      uCARCThreshold;
657     IMG_UINT32      uCARCCutoff;
658     IMG_UINT32      uCARCNegRange;
659     IMG_UINT32      uCARCNegScale;
660     IMG_UINT32      uCARCPosRange;
661     IMG_UINT32      uCARCPosScale;
662     IMG_UINT32      uCARCShift;
663 
664     IMG_UINT32      ui32MVClip_Config;                      //!< Value to use for MVClip_Config  register
665     IMG_UINT32      ui32PredCombControl;                    //!< Value to use for Predictor combiner register
666     IMG_UINT32      ui32LRITC_Tile_Use_Config;              //!< Value to use for LRITC_Tile_Use_Config register
667     IMG_UINT32      ui32LRITC_Cache_Chunk_Config;           //!< Value to use for LRITC_Tile_Free_Config register
668     IMG_UINT32      ui32IPEVectorClipping;                  //!< Value to use for IPEVectorClipping register
669     IMG_UINT32      ui32H264CompControl;                    //!< Value to use for H264CompControl register
670     IMG_UINT32      ui32H264CompIntraPredModes;             //!< Value to use for H264CompIntraPredMode register
671     IMG_UINT32      ui32IPCM_0_Config;                      //!< Value to use for IPCM_0 Config register
672     IMG_UINT32      ui32IPCM_1_Config;                      //!< Value to use for IPCM_1 Config register
673     IMG_UINT32      ui32SPEMvdClipRange;                    //!< Value to use for SPEMvdClipRange register
674     IMG_UINT32      ui32JMCompControl;                      //!< Value to use for JMCompControl register
675     IMG_UINT32      ui32MBHostCtrl;                         //!< Value to use for MB_HOST_CONTROL register
676     IMG_UINT32      ui32DeblockCtrl;                        //!< Value for the CR_DB_DISABLE_DEBLOCK_IDC register
677     IMG_UINT32      ui32SkipCodedInterIntra;                //!< Value for the CR_DB_DISABLE_DEBLOCK_IDC register
678 
679     IMG_UINT32      ui32VLCControl;
680     IMG_UINT32      ui32VLCSliceControl;                    //!< Slice control register value. Configures the size of a slice
681     IMG_UINT32      ui32VLCSliceMBControl;                  //!< Slice control register value. Configures the size of a slice
682     IMG_UINT16      ui16CQPOffset;                          //!< Chroma QP offset to use (when PPS id = 0)
683 
684     IMG_BOOL8       b8CodedHeaderPerSlice;
685 
686     IMG_UINT32      ui32FirstPicFlags;
687     IMG_UINT32      ui32NonFirstPicFlags;
688 
689 #ifndef EXCLUDE_ADAPTIVE_ROUNDING
690     IMG_BOOL16      bMCAdaptiveRoundingDisable;
691     IMG_UINT16      ui16MCAdaptiveRoundingOffsets[18][4];
692     IMG_INT16       i16MCAdaptiveRoundingOffsetsDelta[7][4];
693 #endif
694 
695 #ifdef FORCED_REFERENCE
696     IMG_UINT32      ui32PatchedReconAddress;                //!< Reconstructed address to allow host picture management
697     IMG_UINT32      ui32PatchedRef0Address;                 //!< Reference 0 address to allow host picture management
698     IMG_UINT32      ui32PatchedRef1Address;                 //!< Reference 1 address to allow host picture management
699 #endif
700 #ifdef LTREFHEADER
701     IMG_UINT32      aui32LTRefHeader[MAX_SOURCE_SLOTS_SL];
702     IMG_INT8        i8SliceHeaderSlotNum;
703 #endif
704     IMG_BOOL8       b8ReconIsLongTerm;
705     IMG_BOOL8       b8Ref0IsLongTerm;
706     IMG_BOOL8       b8Ref1IsLongTerm;
707     IMG_UINT8       ui8RefSpacing;
708 
709 #if INPUT_SCALER_SUPPORTED
710     IMG_UINT32      ui32ScalerInputSizeReg;
711     IMG_UINT32      ui32ScalerCropReg;
712     IMG_UINT32      ui32ScalerPitchReg;
713     IMG_UINT32      asHorScalerCoeffRegs[4];
714     IMG_UINT32      asVerScalerCoeffRegs[4];
715 #endif
716 
717     IMG_UINT8       ui8NumPipes;
718     IMG_UINT8       ui8FirstPipe;
719     IMG_UINT8       ui8LastPipe;
720     IMG_UINT8       ui8PipesToUseFlags;
721 
722     /*
723     The following IN_RC_PARAMS should never be used by RC.
724     This is because MVC RC module is unable to alter them, thus
725     they may (and will, in case of MVC) contain incorrect values.
726     */
727     IN_RC_PARAMS    sInParams;
728 }IMG_MTX_VIDEO_CONTEXT;
729 
730 typedef struct _OMX_CARC_PARAMS {
731     IMG_BOOL        bCARC;
732     IMG_INT32       i32CARCBaseline;
733     IMG_UINT32      ui32CARCThreshold;
734     IMG_UINT32      ui32CARCCutoff;
735     IMG_UINT32      ui32CARCNegRange;
736     IMG_UINT32      ui32CARCNegScale;
737     IMG_UINT32      ui32CARCPosRange;
738     IMG_UINT32      ui32CARCPosScale;
739     IMG_UINT32      ui32CARCShift;
740 } OMX_CARC_PARAMS;
741 
742 typedef struct tag_IMG_BIAS_TABLES {
743     IMG_UINT32 aui32LambdaBias[53];
744     IMG_UINT32 aui32IntraBias[53];
745     IMG_UINT32 aui32IntraScale[53];
746     IMG_UINT32 aui32QpBias[53];
747 
748     IMG_UINT32 aui32DirectBias_P[53];
749     IMG_UINT32 aui32InterBias_P[53];
750 
751     IMG_UINT32 aui32DirectBias_B[53];
752     IMG_UINT32 aui32InterBias_B[53];
753 
754     IMG_UINT32  ui32sz1;
755     IMG_UINT32      ui32RejectThresholdH264;
756 
757     IMG_UINT32      ui32FCode;                          //!< value only used in MPEG4
758 
759     IMG_UINT32      ui32LritcCacheChunkConfig;
760     IMG_UINT32      ui32SeqConfigInit;
761 
762 } IMG_BIAS_TABLES;
763 
764 /*!
765 *****************************************************************************
766 @details                Struct describing surface component info
767 @brief                  Surface component info
768 ****************************************************************************/
769 typedef struct {
770     IMG_UINT32 ui32Step;
771     IMG_UINT32 ui32Width;
772     IMG_UINT32 ui32Height;
773     IMG_UINT32 ui32PhysWidth;
774     IMG_UINT32 ui32PhysHeight;
775 } IMG_SURF_COMPONENT_INFO;
776 
777 
778 /*!
779 *****************************************************************************
780 @details                Struct describing a frame
781 @brief                  Frame information
782 ****************************************************************************/
783 typedef struct {
784     //IMG_BUFFER *psYPlaneBuffer;                    //!< pointer to the image buffer
785     //IMG_BUFFER *psUPlaneBuffer;                    //!< pointer to the image buffer
786     //IMG_BUFFER *psVPlaneBuffer;                    //!< pointer to the image buffer
787     IMG_UINT32 ui32Width;                          //!< stride of pBuffer
788     IMG_UINT32 ui32Height;                         //!< height of picture in pBuffer
789 
790     IMG_UINT32 ui32ComponentCount;                 //!< number of colour components used
791     IMG_FORMAT eFormat;
792 
793     IMG_UINT32      aui32ComponentOffset[3];
794     IMG_UINT32      aui32BottomComponentOffset[3];
795     IMG_SURF_COMPONENT_INFO aui32ComponentInfo[3];
796 
797     IMG_INT32 i32YComponentOffset;
798     IMG_INT32 i32UComponentOffset;
799     IMG_INT32 i32VComponentOffset;
800 
801     IMG_INT32 i32Field0YOffset, i32Field1YOffset;
802     IMG_INT32 i32Field0UOffset, i32Field1UOffset;
803     IMG_INT32 i32Field0VOffset, i32Field1VOffset;
804 
805     IMG_UINT16 ui16SrcYStride, ui16SrcUVStride;
806 
807 } IMG_FRAME, JPEG_SOURCE_SURFACE;
808 
809 
810 /*!
811 *****************************************************************************
812  @details    Struct describing the capabilities of the encoder
813  @brief          Encoder Caps
814 ****************************************************************************/
815 typedef struct _IMG_ENC_CAPS {
816     IMG_UINT16      ui16MinSlices;                  //!< Minimum slices to use
817     IMG_UINT16      ui16MaxSlices;                  //!< Maximum slices to use
818     IMG_UINT16      ui16RecommendedSlices;  //!< Recommended number of slices
819     IMG_UINT32      ui32NumCores;                   //!< Number of cores that will be used
820     IMG_UINT32      ui32CoreFeatures;               //!< Core features flags
821 } IMG_ENC_CAPS;
822 
823 typedef struct _IMG_FIRST_STAGE_MB_PARAMS {
824     IMG_UINT16      ui16Ipe0Sad;        //!< Final SAD value for best candidate calculated by IPE 0
825     IMG_UINT16      ui16Ipe1Sad;        //!< Final SAD value for best candidate calculated by IPE 1
826     IMG_UINT8       ui8Ipe0Blks;        //!< Block dimentions for IPE 0 for this Macro-Block
827     IMG_UINT8       ui8Ipe1Blks;        //!< Block dimentions for IPE 1 for this Macro-Block
828     IMG_UINT8       ui8CARCCmplxVal;    //!< CARC complexity value for this macroblock
829     IMG_UINT8       ui8dummy;           //!< Reserved (added for alignment).
830 
831 } IMG_FIRST_STAGE_MB_PARAMS, *P_IMG_FIRST_STAGE_MB_PARAMS;
832 
833 /*!
834  *****************************************************************************
835  *
836  * @Name           Picture Parameter Flags
837  *
838  * @details    Picture parameter flags used in the PIC_PARAM structure
839  *
840  ****************************************************************************/
841 /* @{ */
842 #define ISINTERP_FLAGS                          (0x00000001)
843 #define ISMPEG2_FLAGS                          (0x00000002)
844 #define ISMPEG4_FLAGS                          (0x00000004)
845 #define ISH263_FLAGS                              (0x00000008)
846 #define ISRC_FLAGS                                 (0x00000010)
847 #define ISRC_I16BIAS                                (0x00000020)
848 #define LOW_LATENCY_INTRA_ON_FLY   (0x00000040)
849 #define ISINTERB_FLAGS                          (0x00000080)
850 #define ISSCENE_DISABLED                     (0x00000100)
851 #define ISMULTIREF_FLAGS                     (0x00000200)
852 #define SPATIALDIRECT_FLAGS               (0x00000400)
853 /* @} */
854 
855 /*!
856  *****************************************************************************
857  *
858  * @details    SEI (Buffering Period and Picture Timing) Constants shared between host and firmware
859  *
860  * @brief      SEI Constants
861  *
862  ****************************************************************************/
863 #define BPH_SEI_NAL_INITIAL_CPB_REMOVAL_DELAY_SIZE 23
864 #define BPH_SEI_NAL_INITIAL_CPB_REMOVAL_DELAY_OFFSET_SIZE BPH_SEI_NAL_INITIAL_CPB_REMOVAL_DELAY_SIZE
865 #define PTH_SEI_NAL_CPB_REMOVAL_DELAY_SIZE 23
866 #define PTH_SEI_NAL_DPB_OUTPUT_DELAY_SIZE 7
867 
868 /*!
869  *****************************************************************************
870  * @details    Enum describing threshold values for skipped MB biasing
871  * @brief          Skip thresholds
872  ****************************************************************************/
873 typedef enum
874 {
875     TH_SKIP_0    = 0,    //!< Bias threshold for QP 0 to 12
876     TH_SKIP_12  = 1,    //!< Bias threshold for QP 12 to 24
877     TH_SKIP_24  = 2     //!< Bias threshold for QP 24 and above
878 } TH_SKIP_SCALE;
879 
880 
881 typedef enum
882 {
883     MTX_SCRATCHREG_FULLNESS = 0,   //!< Coded buffer fullness
884     MTX_SCRATCHREG_TOHOST,         //!< Reg for MTX->Host data
885     MTX_SCRATCHREG_TOMTX,          //!< Reg for Host->MTX data
886 
887     MTX_SCRATCHREG_SIZE            //!< End marker for enum
888 } MTX_eScratchRegData;
889 
890 
891 #define MASK_INTEL_CH_PY 0x000000FF
892 #define SHIFT_INTEL_CH_PY 0
893 #define MASK_INTEL_CH_MX 0x0000FF00
894 #define SHIFT_INTEL_CH_MX 8
895 #define MASK_INTEL_CH_PM 0x00FF0000
896 #define SHIFT_INTEL_CH_PM 16
897 
898 #define MASK_INTEL_H264_ConfigReg1 0x0000001F
899 #define SHIFT_INTEL_H264_ConfigReg1 0
900 #define MASK_INTEL_H264_ConfigReg2 0x00003F00
901 #define SHIFT_INTEL_H264_ConfigReg2 8
902 #define MASK_INTEL_H264_LL 0x00010000
903 #define SHIFT_INTEL_H264_LL 16
904 #define MASK_INTEL_H264_LL8X8P 0x00020000
905 #define SHIFT_INTEL_H264_LL8X8P 17
906 #define INTEL_SZ  0x0344
907 #define INTEL_CHCF 0x0050
908 #define INTEL_H264_RT 0x0184
909 
910 
911 
912 
913 #endif //_TNG_HOSTDEFS_H_
914