1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arch.h> 35 #include "../fvp_def.h" 36 37 38 /******************************************************************************* 39 * Platform binary types for linking 40 ******************************************************************************/ 41 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 42 #define PLATFORM_LINKER_ARCH aarch64 43 44 /******************************************************************************* 45 * Generic platform constants 46 ******************************************************************************/ 47 48 /* Size of cacheable stacks */ 49 #if DEBUG_XLAT_TABLE 50 #define PLATFORM_STACK_SIZE 0x800 51 #elif IMAGE_BL1 52 #if TRUSTED_BOARD_BOOT 53 #define PLATFORM_STACK_SIZE 0x1000 54 #else 55 #define PLATFORM_STACK_SIZE 0x440 56 #endif 57 #elif IMAGE_BL2 58 #if TRUSTED_BOARD_BOOT 59 #define PLATFORM_STACK_SIZE 0x1000 60 #else 61 #define PLATFORM_STACK_SIZE 0x400 62 #endif 63 #elif IMAGE_BL31 64 #define PLATFORM_STACK_SIZE 0x400 65 #elif IMAGE_BL32 66 #define PLATFORM_STACK_SIZE 0x440 67 #endif 68 69 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 70 71 /* Trusted Boot Firmware BL2 */ 72 #define BL2_IMAGE_NAME "bl2.bin" 73 74 /* EL3 Runtime Firmware BL31 */ 75 #define BL31_IMAGE_NAME "bl31.bin" 76 77 /* Secure Payload BL32 (Trusted OS) */ 78 #define BL32_IMAGE_NAME "bl32.bin" 79 80 /* Non-Trusted Firmware BL33 */ 81 #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ 82 83 #if TRUSTED_BOARD_BOOT 84 /* Certificates */ 85 # define BL2_CERT_NAME "bl2.crt" 86 # define TRUSTED_KEY_CERT_NAME "trusted_key.crt" 87 88 # define BL30_KEY_CERT_NAME "bl30_key.crt" 89 # define BL31_KEY_CERT_NAME "bl31_key.crt" 90 # define BL32_KEY_CERT_NAME "bl32_key.crt" 91 # define BL33_KEY_CERT_NAME "bl33_key.crt" 92 93 # define BL30_CERT_NAME "bl30.crt" 94 # define BL31_CERT_NAME "bl31.crt" 95 # define BL32_CERT_NAME "bl32.crt" 96 # define BL33_CERT_NAME "bl33.crt" 97 #endif /* TRUSTED_BOARD_BOOT */ 98 99 #define PLATFORM_CACHE_LINE_SIZE 64 100 #define PLATFORM_CLUSTER_COUNT 2ull 101 #define PLATFORM_CLUSTER0_CORE_COUNT 4 102 #define PLATFORM_CLUSTER1_CORE_COUNT 4 103 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 104 PLATFORM_CLUSTER0_CORE_COUNT) 105 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 106 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ 107 PLATFORM_CORE_COUNT) 108 #define MAX_IO_DEVICES 3 109 #define MAX_IO_HANDLES 4 110 111 /******************************************************************************* 112 * BL1 specific defines. 113 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 114 * addresses. 115 ******************************************************************************/ 116 #define BL1_RO_BASE FVP_TRUSTED_ROM_BASE 117 #define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \ 118 + FVP_TRUSTED_ROM_SIZE) 119 /* 120 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 121 * the current BL1 RW debug size plus a little space for growth. 122 */ 123 #if TRUSTED_BOARD_BOOT 124 #define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \ 125 + FVP_TRUSTED_SRAM_SIZE - 0x8000) 126 #else 127 #define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE \ 128 + FVP_TRUSTED_SRAM_SIZE - 0x6000) 129 #endif 130 #define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE \ 131 + FVP_TRUSTED_SRAM_SIZE) 132 133 /******************************************************************************* 134 * BL2 specific defines. 135 ******************************************************************************/ 136 /* 137 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 138 * size plus a little space for growth. 139 */ 140 #if TRUSTED_BOARD_BOOT 141 #define BL2_BASE (BL31_BASE - 0x1C000) 142 #else 143 #define BL2_BASE (BL31_BASE - 0xC000) 144 #endif 145 #define BL2_LIMIT BL31_BASE 146 147 /******************************************************************************* 148 * BL31 specific defines. 149 ******************************************************************************/ 150 /* 151 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 152 * current BL3-1 debug size plus a little space for growth. 153 */ 154 #define BL31_BASE (FVP_TRUSTED_SRAM_BASE \ 155 + FVP_TRUSTED_SRAM_SIZE - 0x1D000) 156 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 157 #define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE \ 158 + FVP_TRUSTED_SRAM_SIZE) 159 160 /******************************************************************************* 161 * BL32 specific defines. 162 ******************************************************************************/ 163 /* 164 * The TSP can execute either from Trusted SRAM or Trusted DRAM. 165 */ 166 #define BL32_SRAM_BASE FVP_TRUSTED_SRAM_BASE 167 #define BL32_SRAM_LIMIT BL31_BASE 168 #define BL32_DRAM_BASE FVP_TRUSTED_DRAM_BASE 169 #define BL32_DRAM_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21)) 170 171 #if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM 172 # define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE 173 # define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE 174 # define TSP_PROGBITS_LIMIT BL2_BASE 175 # define BL32_BASE BL32_SRAM_BASE 176 # define BL32_LIMIT BL32_SRAM_LIMIT 177 #elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM 178 # define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE 179 # define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE 180 # define BL32_BASE BL32_DRAM_BASE 181 # define BL32_LIMIT BL32_DRAM_LIMIT 182 #else 183 # error "Unsupported FVP_TSP_RAM_LOCATION_ID value" 184 #endif 185 186 /* 187 * ID of the secure physical generic timer interrupt used by the TSP. 188 */ 189 #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER 190 191 /******************************************************************************* 192 * Platform specific page table and MMU setup constants 193 ******************************************************************************/ 194 #define ADDR_SPACE_SIZE (1ull << 32) 195 196 #if IMAGE_BL1 197 # define MAX_XLAT_TABLES 2 198 #elif IMAGE_BL2 199 # define MAX_XLAT_TABLES 3 200 #elif IMAGE_BL31 201 # define MAX_XLAT_TABLES 2 202 #elif IMAGE_BL32 203 # if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID 204 # define MAX_XLAT_TABLES 3 205 # else 206 # define MAX_XLAT_TABLES 2 207 # endif 208 #endif 209 210 #define MAX_MMAP_REGIONS 16 211 212 /******************************************************************************* 213 * Declarations and constants to access the mailboxes safely. Each mailbox is 214 * aligned on the biggest cache line size in the platform. This is known only 215 * to the platform as it might have a combination of integrated and external 216 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 217 * line at any cache level. They could belong to different cpus/clusters & 218 * get written while being protected by different locks causing corruption of 219 * a valid mailbox address. 220 ******************************************************************************/ 221 #define CACHE_WRITEBACK_SHIFT 6 222 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 223 224 #if !USE_COHERENT_MEM 225 /******************************************************************************* 226 * Size of the per-cpu data in bytes that should be reserved in the generic 227 * per-cpu data structure for the FVP port. 228 ******************************************************************************/ 229 #define PLAT_PCPU_DATA_SIZE 2 230 #endif 231 232 #endif /* __PLATFORM_DEF_H__ */ 233