1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 6 This program and the accompanying materials are licensed and made available under 7 8 the terms and conditions of the BSD License that accompanies this distribution. 9 10 The full text of the license may be found at 11 12 http://opensource.org/licenses/bsd-license.php. 13 14 15 16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 20 21 22 23 24 Module Name: 25 26 Platform.h 27 28 Abstract: 29 30 Pinetrail platform specific information. 31 32 **/ 33 34 #ifndef _PLATFORM_H 35 #define _PLATFORM_H 36 37 #include "ChipsetAccess.h" 38 #include "PlatformBaseAddresses.h" 39 40 41 // 42 // Number of P & T states supported. 43 // 44 #define NPTM_P_STATES_SUPPORTED 16 45 #define NPTM_T_STATES_SUPPORTED 8 46 47 // 48 // I/O APIC IDs, the code uses math to generate the numbers 49 // instead of using these defines. 50 // 51 #define ICH_IOAPIC (1 << 0) 52 #define ICH_IOAPIC_ID 0x08 53 54 // 55 // Possible SMBus addresses that will be present. 56 // 57 #define SMBUS_ADDR_CH_A_1 0xA0 58 #define SMBUS_ADDR_CH_A_2 0xA2 59 #define SMBUS_ADDR_CH_B_1 0xA4 60 #define SMBUS_ADDR_CH_B_2 0xA6 61 #define SMBUS_ADDR_CH_C_1 0xA8 62 #define SMBUS_ADDR_CH_C_2 0xAA 63 #define SMBUS_ADDR_CH_D_1 0xAC 64 #define SMBUS_ADDR_CH_D_2 0xAE 65 #define SMBUS_ADDR_HOST_CLK_BUFFER 0xDC 66 #define SMBUS_ADDR_ICH_SLAVE 0x44 67 #define SMBUS_ADDR_HECETA 0x5C 68 #define SMBUS_ADDR_SMBARP 0xC2 69 #define SMBUS_ADDR_82573E 0xC6 70 #define SMBUS_ADDR_CLKCHIP 0xD2 71 #define SMBUS_ADDR_BRD_REV 0x4E 72 #define SMBUS_ADDR_DB803 0x82 73 74 // 75 // SMBus addresses that used on this platform. 76 // 77 #define PLATFORM_SMBUS_RSVD_ADDRESSES { \ 78 SMBUS_ADDR_CH_A_1, \ 79 SMBUS_ADDR_CH_A_2, \ 80 SMBUS_ADDR_HOST_CLK_BUFFER, \ 81 SMBUS_ADDR_ICH_SLAVE, \ 82 SMBUS_ADDR_SMBARP, \ 83 SMBUS_ADDR_CLKCHIP, \ 84 SMBUS_ADDR_BRD_REV, \ 85 SMBUS_ADDR_DB803 \ 86 } 87 88 // 89 // Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES. 90 // 91 #define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8 92 93 // 94 // CMOS usage 95 // 96 #define CMOS_CPU_BSP_SELECT 0x10 97 #define CMOS_CPU_UP_MODE 0x11 98 #define CMOS_CPU_RATIO_OFFSET 0x12 99 #define CMOS_CPU_CORE_HT_OFFSET 0x13 100 #define CMOS_EFI_DEBUG 0x14 101 #define CMOS_CPU_BIST_OFFSET 0x15 102 #define CMOS_CPU_VMX_OFFSET 0x16 103 #define CMOS_ICH_PORT80_OFFSET 0x17 104 #define CMOS_PLATFORM_DESIGNATOR 0x18 // Second bank CMOS location of Platform ID. 105 #define CMOS_VALIDATION_TEST_BYTE 0x19 // BIT0 - Validation mailbox for UPonDP. 106 #define CMOS_SERIAL_BAUD_RATE 0x1A // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600 107 #define CMOS_DCU_MODE_OFFSET 0x1B 108 #define CMOS_VR11_SET_OFFSET 0x1C 109 #define CMOS_SBSP_TO_AP_COMM 0x20 // SEC code use ONLY!!! 110 #define CMOS_RESET_TYPE_BY_OS 0x52 111 #define TCG_CMOS_MOR_AREA_OFFSET 0x65 // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c & 112 #define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E 113 #define ACPI_TPM_REQUEST 0x75 114 #define ACPI_TPM_LAST_REQUEST 0x76 115 #define CMOS_BOOT_FLAG_ADDRESS 0x7E 116 117 // 118 // GPIO Index Data Structure. 119 // 120 typedef struct { 121 UINT8 Register; 122 UINT32 Value; 123 } ICH_GPIO_DEV; 124 125 // 126 // CPU Equates 127 // 128 #define MAX_THREAD 2 129 #define MAX_CORE 1 130 #define MAX_DIE 2 131 #define MAX_CPU_SOCKET 1 132 #define MAX_CPU_NUM (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET) 133 134 #define MEM64_LEN 0x00100000000 135 #define RES_MEM64_36_BASE 0x01000000000 - MEM64_LEN // 2^36 136 #define RES_MEM64_36_LIMIT 0x01000000000 - 1 // 2^36 137 #define RES_MEM64_39_BASE 0x08000000000 - MEM64_LEN // 2^39 138 #define RES_MEM64_39_LIMIT 0x08000000000 - 1 // 2^39 139 #define RES_MEM64_40_BASE 0x10000000000 - MEM64_LEN // 2^40 140 #define RES_MEM64_40_LIMIT 0x10000000000 - 1 // 2^40 141 142 #define PLATFORM_MAX_BUS_NUM 0x3f 143 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID 0x574d 144 #define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b 145 #define V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086 146 147 #endif 148