1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_H_
6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_H_
7
8 #include <vector>
9
10 #include "src/arm64/assembler-arm64.h"
11 #include "src/bailout-reason.h"
12 #include "src/base/bits.h"
13 #include "src/globals.h"
14
15 // Simulator specific helpers.
16 #if USE_SIMULATOR
17 // TODO(all): If possible automatically prepend an indicator like
18 // UNIMPLEMENTED or LOCATION.
19 #define ASM_UNIMPLEMENTED(message) \
20 __ Debug(message, __LINE__, NO_PARAM)
21 #define ASM_UNIMPLEMENTED_BREAK(message) \
22 __ Debug(message, __LINE__, \
23 FLAG_ignore_asm_unimplemented_break ? NO_PARAM : BREAK)
24 #if DEBUG
25 #define ASM_LOCATION(message) __ Debug("LOCATION: " message, __LINE__, NO_PARAM)
26 #else
27 #define ASM_LOCATION(message)
28 #endif
29 #else
30 #define ASM_UNIMPLEMENTED(message)
31 #define ASM_UNIMPLEMENTED_BREAK(message)
32 #define ASM_LOCATION(message)
33 #endif
34
35
36 namespace v8 {
37 namespace internal {
38
39 // Give alias names to registers for calling conventions.
40 #define kReturnRegister0 x0
41 #define kReturnRegister1 x1
42 #define kReturnRegister2 x2
43 #define kJSFunctionRegister x1
44 #define kContextRegister cp
45 #define kAllocateSizeRegister x1
46 #define kInterpreterAccumulatorRegister x0
47 #define kInterpreterBytecodeOffsetRegister x19
48 #define kInterpreterBytecodeArrayRegister x20
49 #define kInterpreterDispatchTableRegister x21
50 #define kJavaScriptCallArgCountRegister x0
51 #define kJavaScriptCallNewTargetRegister x3
52 #define kRuntimeCallFunctionRegister x1
53 #define kRuntimeCallArgCountRegister x0
54
55 #define LS_MACRO_LIST(V) \
56 V(Ldrb, Register&, rt, LDRB_w) \
57 V(Strb, Register&, rt, STRB_w) \
58 V(Ldrsb, Register&, rt, rt.Is64Bits() ? LDRSB_x : LDRSB_w) \
59 V(Ldrh, Register&, rt, LDRH_w) \
60 V(Strh, Register&, rt, STRH_w) \
61 V(Ldrsh, Register&, rt, rt.Is64Bits() ? LDRSH_x : LDRSH_w) \
62 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \
63 V(Str, CPURegister&, rt, StoreOpFor(rt)) \
64 V(Ldrsw, Register&, rt, LDRSW_x)
65
66 #define LSPAIR_MACRO_LIST(V) \
67 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
68 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
69 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
70
71 #define LDA_STL_MACRO_LIST(V) \
72 V(Ldarb, ldarb) \
73 V(Ldarh, ldarh) \
74 V(Ldar, ldar) \
75 V(Ldaxrb, ldaxrb) \
76 V(Ldaxrh, ldaxrh) \
77 V(Ldaxr, ldaxr) \
78 V(Stlrb, stlrb) \
79 V(Stlrh, stlrh) \
80 V(Stlr, stlr)
81
82 #define STLX_MACRO_LIST(V) \
83 V(Stlxrb, stlxrb) \
84 V(Stlxrh, stlxrh) \
85 V(Stlxr, stlxr)
86
87 // ----------------------------------------------------------------------------
88 // Static helper functions
89
90 // Generate a MemOperand for loading a field from an object.
91 inline MemOperand FieldMemOperand(Register object, int offset);
92 inline MemOperand UntagSmiFieldMemOperand(Register object, int offset);
93
94 // Generate a MemOperand for loading a SMI from memory.
95 inline MemOperand UntagSmiMemOperand(Register object, int offset);
96
97
98 // ----------------------------------------------------------------------------
99 // MacroAssembler
100
101 enum BranchType {
102 // Copies of architectural conditions.
103 // The associated conditions can be used in place of those, the code will
104 // take care of reinterpreting them with the correct type.
105 integer_eq = eq,
106 integer_ne = ne,
107 integer_hs = hs,
108 integer_lo = lo,
109 integer_mi = mi,
110 integer_pl = pl,
111 integer_vs = vs,
112 integer_vc = vc,
113 integer_hi = hi,
114 integer_ls = ls,
115 integer_ge = ge,
116 integer_lt = lt,
117 integer_gt = gt,
118 integer_le = le,
119 integer_al = al,
120 integer_nv = nv,
121
122 // These two are *different* from the architectural codes al and nv.
123 // 'always' is used to generate unconditional branches.
124 // 'never' is used to not generate a branch (generally as the inverse
125 // branch type of 'always).
126 always, never,
127 // cbz and cbnz
128 reg_zero, reg_not_zero,
129 // tbz and tbnz
130 reg_bit_clear, reg_bit_set,
131
132 // Aliases.
133 kBranchTypeFirstCondition = eq,
134 kBranchTypeLastCondition = nv,
135 kBranchTypeFirstUsingReg = reg_zero,
136 kBranchTypeFirstUsingBit = reg_bit_clear
137 };
138
InvertBranchType(BranchType type)139 inline BranchType InvertBranchType(BranchType type) {
140 if (kBranchTypeFirstCondition <= type && type <= kBranchTypeLastCondition) {
141 return static_cast<BranchType>(
142 NegateCondition(static_cast<Condition>(type)));
143 } else {
144 return static_cast<BranchType>(type ^ 1);
145 }
146 }
147
148 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
149 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
150 enum PointersToHereCheck {
151 kPointersToHereMaybeInteresting,
152 kPointersToHereAreAlwaysInteresting
153 };
154 enum LinkRegisterStatus { kLRHasNotBeenSaved, kLRHasBeenSaved };
155 enum TargetAddressStorageMode {
156 CAN_INLINE_TARGET_ADDRESS,
157 NEVER_INLINE_TARGET_ADDRESS
158 };
159 enum UntagMode { kNotSpeculativeUntag, kSpeculativeUntag };
160 enum ArrayHasHoles { kArrayCantHaveHoles, kArrayCanHaveHoles };
161 enum CopyHint { kCopyUnknown, kCopyShort, kCopyLong };
162 enum DiscardMoveMode { kDontDiscardForSameWReg, kDiscardForSameWReg };
163 enum SeqStringSetCharCheckIndexType { kIndexIsSmi, kIndexIsInteger32 };
164
165 class MacroAssembler : public Assembler {
166 public:
167 MacroAssembler(Isolate* isolate, byte* buffer, unsigned buffer_size,
168 CodeObjectRequired create_code_object);
169
170 inline Handle<Object> CodeObject();
171
172 // Instruction set functions ------------------------------------------------
173 // Logical macros.
174 inline void And(const Register& rd,
175 const Register& rn,
176 const Operand& operand);
177 inline void Ands(const Register& rd,
178 const Register& rn,
179 const Operand& operand);
180 inline void Bic(const Register& rd,
181 const Register& rn,
182 const Operand& operand);
183 inline void Bics(const Register& rd,
184 const Register& rn,
185 const Operand& operand);
186 inline void Orr(const Register& rd,
187 const Register& rn,
188 const Operand& operand);
189 inline void Orn(const Register& rd,
190 const Register& rn,
191 const Operand& operand);
192 inline void Eor(const Register& rd,
193 const Register& rn,
194 const Operand& operand);
195 inline void Eon(const Register& rd,
196 const Register& rn,
197 const Operand& operand);
198 inline void Tst(const Register& rn, const Operand& operand);
199 void LogicalMacro(const Register& rd,
200 const Register& rn,
201 const Operand& operand,
202 LogicalOp op);
203
204 // Add and sub macros.
205 inline void Add(const Register& rd,
206 const Register& rn,
207 const Operand& operand);
208 inline void Adds(const Register& rd,
209 const Register& rn,
210 const Operand& operand);
211 inline void Sub(const Register& rd,
212 const Register& rn,
213 const Operand& operand);
214 inline void Subs(const Register& rd,
215 const Register& rn,
216 const Operand& operand);
217 inline void Cmn(const Register& rn, const Operand& operand);
218 inline void Cmp(const Register& rn, const Operand& operand);
219 inline void Neg(const Register& rd,
220 const Operand& operand);
221 inline void Negs(const Register& rd,
222 const Operand& operand);
223
224 void AddSubMacro(const Register& rd,
225 const Register& rn,
226 const Operand& operand,
227 FlagsUpdate S,
228 AddSubOp op);
229
230 // Add/sub with carry macros.
231 inline void Adc(const Register& rd,
232 const Register& rn,
233 const Operand& operand);
234 inline void Adcs(const Register& rd,
235 const Register& rn,
236 const Operand& operand);
237 inline void Sbc(const Register& rd,
238 const Register& rn,
239 const Operand& operand);
240 inline void Sbcs(const Register& rd,
241 const Register& rn,
242 const Operand& operand);
243 inline void Ngc(const Register& rd,
244 const Operand& operand);
245 inline void Ngcs(const Register& rd,
246 const Operand& operand);
247 void AddSubWithCarryMacro(const Register& rd,
248 const Register& rn,
249 const Operand& operand,
250 FlagsUpdate S,
251 AddSubWithCarryOp op);
252
253 // Move macros.
254 void Mov(const Register& rd,
255 const Operand& operand,
256 DiscardMoveMode discard_mode = kDontDiscardForSameWReg);
257 void Mov(const Register& rd, uint64_t imm);
258 inline void Mvn(const Register& rd, uint64_t imm);
259 void Mvn(const Register& rd, const Operand& operand);
260 static bool IsImmMovn(uint64_t imm, unsigned reg_size);
261 static bool IsImmMovz(uint64_t imm, unsigned reg_size);
262 static unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size);
263
264 // Try to move an immediate into the destination register in a single
265 // instruction. Returns true for success, and updates the contents of dst.
266 // Returns false, otherwise.
267 bool TryOneInstrMoveImmediate(const Register& dst, int64_t imm);
268
269 // Move an immediate into register dst, and return an Operand object for use
270 // with a subsequent instruction that accepts a shift. The value moved into
271 // dst is not necessarily equal to imm; it may have had a shifting operation
272 // applied to it that will be subsequently undone by the shift applied in the
273 // Operand.
274 Operand MoveImmediateForShiftedOp(const Register& dst, int64_t imm);
275
276 // Conditional macros.
277 inline void Ccmp(const Register& rn,
278 const Operand& operand,
279 StatusFlags nzcv,
280 Condition cond);
281 inline void Ccmn(const Register& rn,
282 const Operand& operand,
283 StatusFlags nzcv,
284 Condition cond);
285 void ConditionalCompareMacro(const Register& rn,
286 const Operand& operand,
287 StatusFlags nzcv,
288 Condition cond,
289 ConditionalCompareOp op);
290 void Csel(const Register& rd,
291 const Register& rn,
292 const Operand& operand,
293 Condition cond);
294
295 // Load/store macros.
296 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \
297 inline void FN(const REGTYPE REG, const MemOperand& addr);
298 LS_MACRO_LIST(DECLARE_FUNCTION)
299 #undef DECLARE_FUNCTION
300
301 void LoadStoreMacro(const CPURegister& rt,
302 const MemOperand& addr,
303 LoadStoreOp op);
304
305 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
306 inline void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr);
307 LSPAIR_MACRO_LIST(DECLARE_FUNCTION)
308 #undef DECLARE_FUNCTION
309
310 void LoadStorePairMacro(const CPURegister& rt, const CPURegister& rt2,
311 const MemOperand& addr, LoadStorePairOp op);
312
313 // Load-acquire/store-release macros.
314 #define DECLARE_FUNCTION(FN, OP) \
315 inline void FN(const Register& rt, const Register& rn);
316 LDA_STL_MACRO_LIST(DECLARE_FUNCTION)
317 #undef DECLARE_FUNCTION
318
319 #define DECLARE_FUNCTION(FN, OP) \
320 inline void FN(const Register& rs, const Register& rt, const Register& rn);
321 STLX_MACRO_LIST(DECLARE_FUNCTION)
322 #undef DECLARE_FUNCTION
323
324 // V8-specific load/store helpers.
325 void Load(const Register& rt, const MemOperand& addr, Representation r);
326 void Store(const Register& rt, const MemOperand& addr, Representation r);
327
328 enum AdrHint {
329 // The target must be within the immediate range of adr.
330 kAdrNear,
331 // The target may be outside of the immediate range of adr. Additional
332 // instructions may be emitted.
333 kAdrFar
334 };
335 void Adr(const Register& rd, Label* label, AdrHint = kAdrNear);
336
337 // Remaining instructions are simple pass-through calls to the assembler.
338 inline void Asr(const Register& rd, const Register& rn, unsigned shift);
339 inline void Asr(const Register& rd, const Register& rn, const Register& rm);
340
341 // Branch type inversion relies on these relations.
342 STATIC_ASSERT((reg_zero == (reg_not_zero ^ 1)) &&
343 (reg_bit_clear == (reg_bit_set ^ 1)) &&
344 (always == (never ^ 1)));
345
346 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1);
347
348 inline void B(Label* label);
349 inline void B(Condition cond, Label* label);
350 void B(Label* label, Condition cond);
351 inline void Bfi(const Register& rd,
352 const Register& rn,
353 unsigned lsb,
354 unsigned width);
355 inline void Bfxil(const Register& rd,
356 const Register& rn,
357 unsigned lsb,
358 unsigned width);
359 inline void Bind(Label* label);
360 inline void Bl(Label* label);
361 inline void Blr(const Register& xn);
362 inline void Br(const Register& xn);
363 inline void Brk(int code);
364 void Cbnz(const Register& rt, Label* label);
365 void Cbz(const Register& rt, Label* label);
366 inline void Cinc(const Register& rd, const Register& rn, Condition cond);
367 inline void Cinv(const Register& rd, const Register& rn, Condition cond);
368 inline void Cls(const Register& rd, const Register& rn);
369 inline void Clz(const Register& rd, const Register& rn);
370 inline void Cneg(const Register& rd, const Register& rn, Condition cond);
371 inline void CzeroX(const Register& rd, Condition cond);
372 inline void CmovX(const Register& rd, const Register& rn, Condition cond);
373 inline void Cset(const Register& rd, Condition cond);
374 inline void Csetm(const Register& rd, Condition cond);
375 inline void Csinc(const Register& rd,
376 const Register& rn,
377 const Register& rm,
378 Condition cond);
379 inline void Csinv(const Register& rd,
380 const Register& rn,
381 const Register& rm,
382 Condition cond);
383 inline void Csneg(const Register& rd,
384 const Register& rn,
385 const Register& rm,
386 Condition cond);
387 inline void Dmb(BarrierDomain domain, BarrierType type);
388 inline void Dsb(BarrierDomain domain, BarrierType type);
389 inline void Debug(const char* message, uint32_t code, Instr params = BREAK);
390 inline void Extr(const Register& rd,
391 const Register& rn,
392 const Register& rm,
393 unsigned lsb);
394 inline void Fabs(const FPRegister& fd, const FPRegister& fn);
395 inline void Fadd(const FPRegister& fd,
396 const FPRegister& fn,
397 const FPRegister& fm);
398 inline void Fccmp(const FPRegister& fn,
399 const FPRegister& fm,
400 StatusFlags nzcv,
401 Condition cond);
402 inline void Fcmp(const FPRegister& fn, const FPRegister& fm);
403 inline void Fcmp(const FPRegister& fn, double value);
404 inline void Fcsel(const FPRegister& fd,
405 const FPRegister& fn,
406 const FPRegister& fm,
407 Condition cond);
408 inline void Fcvt(const FPRegister& fd, const FPRegister& fn);
409 inline void Fcvtas(const Register& rd, const FPRegister& fn);
410 inline void Fcvtau(const Register& rd, const FPRegister& fn);
411 inline void Fcvtms(const Register& rd, const FPRegister& fn);
412 inline void Fcvtmu(const Register& rd, const FPRegister& fn);
413 inline void Fcvtns(const Register& rd, const FPRegister& fn);
414 inline void Fcvtnu(const Register& rd, const FPRegister& fn);
415 inline void Fcvtzs(const Register& rd, const FPRegister& fn);
416 inline void Fcvtzu(const Register& rd, const FPRegister& fn);
417 inline void Fdiv(const FPRegister& fd,
418 const FPRegister& fn,
419 const FPRegister& fm);
420 inline void Fmadd(const FPRegister& fd,
421 const FPRegister& fn,
422 const FPRegister& fm,
423 const FPRegister& fa);
424 inline void Fmax(const FPRegister& fd,
425 const FPRegister& fn,
426 const FPRegister& fm);
427 inline void Fmaxnm(const FPRegister& fd,
428 const FPRegister& fn,
429 const FPRegister& fm);
430 inline void Fmin(const FPRegister& fd,
431 const FPRegister& fn,
432 const FPRegister& fm);
433 inline void Fminnm(const FPRegister& fd,
434 const FPRegister& fn,
435 const FPRegister& fm);
436 inline void Fmov(FPRegister fd, FPRegister fn);
437 inline void Fmov(FPRegister fd, Register rn);
438 // Provide explicit double and float interfaces for FP immediate moves, rather
439 // than relying on implicit C++ casts. This allows signalling NaNs to be
440 // preserved when the immediate matches the format of fd. Most systems convert
441 // signalling NaNs to quiet NaNs when converting between float and double.
442 inline void Fmov(FPRegister fd, double imm);
443 inline void Fmov(FPRegister fd, float imm);
444 // Provide a template to allow other types to be converted automatically.
445 template<typename T>
Fmov(FPRegister fd,T imm)446 void Fmov(FPRegister fd, T imm) {
447 DCHECK(allow_macro_instructions_);
448 Fmov(fd, static_cast<double>(imm));
449 }
450 inline void Fmov(Register rd, FPRegister fn);
451 inline void Fmsub(const FPRegister& fd,
452 const FPRegister& fn,
453 const FPRegister& fm,
454 const FPRegister& fa);
455 inline void Fmul(const FPRegister& fd,
456 const FPRegister& fn,
457 const FPRegister& fm);
458 inline void Fneg(const FPRegister& fd, const FPRegister& fn);
459 inline void Fnmadd(const FPRegister& fd,
460 const FPRegister& fn,
461 const FPRegister& fm,
462 const FPRegister& fa);
463 inline void Fnmsub(const FPRegister& fd,
464 const FPRegister& fn,
465 const FPRegister& fm,
466 const FPRegister& fa);
467 inline void Frinta(const FPRegister& fd, const FPRegister& fn);
468 inline void Frintm(const FPRegister& fd, const FPRegister& fn);
469 inline void Frintn(const FPRegister& fd, const FPRegister& fn);
470 inline void Frintp(const FPRegister& fd, const FPRegister& fn);
471 inline void Frintz(const FPRegister& fd, const FPRegister& fn);
472 inline void Fsqrt(const FPRegister& fd, const FPRegister& fn);
473 inline void Fsub(const FPRegister& fd,
474 const FPRegister& fn,
475 const FPRegister& fm);
476 inline void Hint(SystemHint code);
477 inline void Hlt(int code);
478 inline void Isb();
479 inline void Ldnp(const CPURegister& rt,
480 const CPURegister& rt2,
481 const MemOperand& src);
482 // Load a literal from the inline constant pool.
483 inline void Ldr(const CPURegister& rt, const Immediate& imm);
484 // Helper function for double immediate.
485 inline void Ldr(const CPURegister& rt, double imm);
486 inline void Lsl(const Register& rd, const Register& rn, unsigned shift);
487 inline void Lsl(const Register& rd, const Register& rn, const Register& rm);
488 inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
489 inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
490 inline void Madd(const Register& rd,
491 const Register& rn,
492 const Register& rm,
493 const Register& ra);
494 inline void Mneg(const Register& rd, const Register& rn, const Register& rm);
495 inline void Mov(const Register& rd, const Register& rm);
496 inline void Movk(const Register& rd, uint64_t imm, int shift = -1);
497 inline void Mrs(const Register& rt, SystemRegister sysreg);
498 inline void Msr(SystemRegister sysreg, const Register& rt);
499 inline void Msub(const Register& rd,
500 const Register& rn,
501 const Register& rm,
502 const Register& ra);
503 inline void Mul(const Register& rd, const Register& rn, const Register& rm);
Nop()504 inline void Nop() { nop(); }
505 inline void Rbit(const Register& rd, const Register& rn);
506 inline void Ret(const Register& xn = lr);
507 inline void Rev(const Register& rd, const Register& rn);
508 inline void Rev16(const Register& rd, const Register& rn);
509 inline void Rev32(const Register& rd, const Register& rn);
510 inline void Ror(const Register& rd, const Register& rs, unsigned shift);
511 inline void Ror(const Register& rd, const Register& rn, const Register& rm);
512 inline void Sbfiz(const Register& rd,
513 const Register& rn,
514 unsigned lsb,
515 unsigned width);
516 inline void Sbfx(const Register& rd,
517 const Register& rn,
518 unsigned lsb,
519 unsigned width);
520 inline void Scvtf(const FPRegister& fd,
521 const Register& rn,
522 unsigned fbits = 0);
523 inline void Sdiv(const Register& rd, const Register& rn, const Register& rm);
524 inline void Smaddl(const Register& rd,
525 const Register& rn,
526 const Register& rm,
527 const Register& ra);
528 inline void Smsubl(const Register& rd,
529 const Register& rn,
530 const Register& rm,
531 const Register& ra);
532 inline void Smull(const Register& rd,
533 const Register& rn,
534 const Register& rm);
535 inline void Smulh(const Register& rd,
536 const Register& rn,
537 const Register& rm);
538 inline void Umull(const Register& rd, const Register& rn, const Register& rm);
539 inline void Stnp(const CPURegister& rt,
540 const CPURegister& rt2,
541 const MemOperand& dst);
542 inline void Sxtb(const Register& rd, const Register& rn);
543 inline void Sxth(const Register& rd, const Register& rn);
544 inline void Sxtw(const Register& rd, const Register& rn);
545 void Tbnz(const Register& rt, unsigned bit_pos, Label* label);
546 void Tbz(const Register& rt, unsigned bit_pos, Label* label);
547 inline void Ubfiz(const Register& rd,
548 const Register& rn,
549 unsigned lsb,
550 unsigned width);
551 inline void Ubfx(const Register& rd,
552 const Register& rn,
553 unsigned lsb,
554 unsigned width);
555 inline void Ucvtf(const FPRegister& fd,
556 const Register& rn,
557 unsigned fbits = 0);
558 inline void Udiv(const Register& rd, const Register& rn, const Register& rm);
559 inline void Umaddl(const Register& rd,
560 const Register& rn,
561 const Register& rm,
562 const Register& ra);
563 inline void Umsubl(const Register& rd,
564 const Register& rn,
565 const Register& rm,
566 const Register& ra);
567 inline void Uxtb(const Register& rd, const Register& rn);
568 inline void Uxth(const Register& rd, const Register& rn);
569 inline void Uxtw(const Register& rd, const Register& rn);
570
571 // Pseudo-instructions ------------------------------------------------------
572
573 // Compute rd = abs(rm).
574 // This function clobbers the condition flags. On output the overflow flag is
575 // set iff the negation overflowed.
576 //
577 // If rm is the minimum representable value, the result is not representable.
578 // Handlers for each case can be specified using the relevant labels.
579 void Abs(const Register& rd, const Register& rm,
580 Label * is_not_representable = NULL,
581 Label * is_representable = NULL);
582
583 // Push or pop up to 4 registers of the same width to or from the stack,
584 // using the current stack pointer as set by SetStackPointer.
585 //
586 // If an argument register is 'NoReg', all further arguments are also assumed
587 // to be 'NoReg', and are thus not pushed or popped.
588 //
589 // Arguments are ordered such that "Push(a, b);" is functionally equivalent
590 // to "Push(a); Push(b);".
591 //
592 // It is valid to push the same register more than once, and there is no
593 // restriction on the order in which registers are specified.
594 //
595 // It is not valid to pop into the same register more than once in one
596 // operation, not even into the zero register.
597 //
598 // If the current stack pointer (as set by SetStackPointer) is csp, then it
599 // must be aligned to 16 bytes on entry and the total size of the specified
600 // registers must also be a multiple of 16 bytes.
601 //
602 // Even if the current stack pointer is not the system stack pointer (csp),
603 // Push (and derived methods) will still modify the system stack pointer in
604 // order to comply with ABI rules about accessing memory below the system
605 // stack pointer.
606 //
607 // Other than the registers passed into Pop, the stack pointer and (possibly)
608 // the system stack pointer, these methods do not modify any other registers.
609 void Push(const CPURegister& src0, const CPURegister& src1 = NoReg,
610 const CPURegister& src2 = NoReg, const CPURegister& src3 = NoReg);
611 void Push(const CPURegister& src0, const CPURegister& src1,
612 const CPURegister& src2, const CPURegister& src3,
613 const CPURegister& src4, const CPURegister& src5 = NoReg,
614 const CPURegister& src6 = NoReg, const CPURegister& src7 = NoReg);
615 void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg,
616 const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg);
617 void Pop(const CPURegister& dst0, const CPURegister& dst1,
618 const CPURegister& dst2, const CPURegister& dst3,
619 const CPURegister& dst4, const CPURegister& dst5 = NoReg,
620 const CPURegister& dst6 = NoReg, const CPURegister& dst7 = NoReg);
621 void Push(const Register& src0, const FPRegister& src1);
622
623 // Alternative forms of Push and Pop, taking a RegList or CPURegList that
624 // specifies the registers that are to be pushed or popped. Higher-numbered
625 // registers are associated with higher memory addresses (as in the A32 push
626 // and pop instructions).
627 //
628 // (Push|Pop)SizeRegList allow you to specify the register size as a
629 // parameter. Only kXRegSizeInBits, kWRegSizeInBits, kDRegSizeInBits and
630 // kSRegSizeInBits are supported.
631 //
632 // Otherwise, (Push|Pop)(CPU|X|W|D|S)RegList is preferred.
633 void PushCPURegList(CPURegList registers);
634 void PopCPURegList(CPURegList registers);
635
636 inline void PushSizeRegList(RegList registers, unsigned reg_size,
637 CPURegister::RegisterType type = CPURegister::kRegister) {
638 PushCPURegList(CPURegList(type, reg_size, registers));
639 }
640 inline void PopSizeRegList(RegList registers, unsigned reg_size,
641 CPURegister::RegisterType type = CPURegister::kRegister) {
642 PopCPURegList(CPURegList(type, reg_size, registers));
643 }
PushXRegList(RegList regs)644 inline void PushXRegList(RegList regs) {
645 PushSizeRegList(regs, kXRegSizeInBits);
646 }
PopXRegList(RegList regs)647 inline void PopXRegList(RegList regs) {
648 PopSizeRegList(regs, kXRegSizeInBits);
649 }
PushWRegList(RegList regs)650 inline void PushWRegList(RegList regs) {
651 PushSizeRegList(regs, kWRegSizeInBits);
652 }
PopWRegList(RegList regs)653 inline void PopWRegList(RegList regs) {
654 PopSizeRegList(regs, kWRegSizeInBits);
655 }
PushDRegList(RegList regs)656 inline void PushDRegList(RegList regs) {
657 PushSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister);
658 }
PopDRegList(RegList regs)659 inline void PopDRegList(RegList regs) {
660 PopSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister);
661 }
PushSRegList(RegList regs)662 inline void PushSRegList(RegList regs) {
663 PushSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister);
664 }
PopSRegList(RegList regs)665 inline void PopSRegList(RegList regs) {
666 PopSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister);
667 }
668
669 // Push the specified register 'count' times.
670 void PushMultipleTimes(CPURegister src, Register count);
671 void PushMultipleTimes(CPURegister src, int count);
672
673 // This is a convenience method for pushing a single Handle<Object>.
674 inline void Push(Handle<Object> handle);
Push(Smi * smi)675 void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); }
676
677 // Aliases of Push and Pop, required for V8 compatibility.
push(Register src)678 inline void push(Register src) {
679 Push(src);
680 }
pop(Register dst)681 inline void pop(Register dst) {
682 Pop(dst);
683 }
684
685 // Sometimes callers need to push or pop multiple registers in a way that is
686 // difficult to structure efficiently for fixed Push or Pop calls. This scope
687 // allows push requests to be queued up, then flushed at once. The
688 // MacroAssembler will try to generate the most efficient sequence required.
689 //
690 // Unlike the other Push and Pop macros, PushPopQueue can handle mixed sets of
691 // register sizes and types.
692 class PushPopQueue {
693 public:
PushPopQueue(MacroAssembler * masm)694 explicit PushPopQueue(MacroAssembler* masm) : masm_(masm), size_(0) { }
695
~PushPopQueue()696 ~PushPopQueue() {
697 DCHECK(queued_.empty());
698 }
699
Queue(const CPURegister & rt)700 void Queue(const CPURegister& rt) {
701 size_ += rt.SizeInBytes();
702 queued_.push_back(rt);
703 }
704
705 enum PreambleDirective {
706 WITH_PREAMBLE,
707 SKIP_PREAMBLE
708 };
709 void PushQueued(PreambleDirective preamble_directive = WITH_PREAMBLE);
710 void PopQueued();
711
712 private:
713 MacroAssembler* masm_;
714 int size_;
715 std::vector<CPURegister> queued_;
716 };
717
718 // Poke 'src' onto the stack. The offset is in bytes.
719 //
720 // If the current stack pointer (according to StackPointer()) is csp, then
721 // csp must be aligned to 16 bytes.
722 void Poke(const CPURegister& src, const Operand& offset);
723
724 // Peek at a value on the stack, and put it in 'dst'. The offset is in bytes.
725 //
726 // If the current stack pointer (according to StackPointer()) is csp, then
727 // csp must be aligned to 16 bytes.
728 void Peek(const CPURegister& dst, const Operand& offset);
729
730 // Poke 'src1' and 'src2' onto the stack. The values written will be adjacent
731 // with 'src2' at a higher address than 'src1'. The offset is in bytes.
732 //
733 // If the current stack pointer (according to StackPointer()) is csp, then
734 // csp must be aligned to 16 bytes.
735 void PokePair(const CPURegister& src1, const CPURegister& src2, int offset);
736
737 // Peek at two values on the stack, and put them in 'dst1' and 'dst2'. The
738 // values peeked will be adjacent, with the value in 'dst2' being from a
739 // higher address than 'dst1'. The offset is in bytes.
740 //
741 // If the current stack pointer (according to StackPointer()) is csp, then
742 // csp must be aligned to 16 bytes.
743 void PeekPair(const CPURegister& dst1, const CPURegister& dst2, int offset);
744
745 // Emit code that loads |parameter_index|'th parameter from the stack to
746 // the register according to the CallInterfaceDescriptor definition.
747 // |sp_to_caller_sp_offset_in_words| specifies the number of words pushed
748 // below the caller's sp.
749 template <class Descriptor>
750 void LoadParameterFromStack(
751 Register reg, typename Descriptor::ParameterIndices parameter_index,
752 int sp_to_ra_offset_in_words = 0) {
753 DCHECK(Descriptor::kPassLastArgsOnStack);
754 UNIMPLEMENTED();
755 }
756
757 // Claim or drop stack space without actually accessing memory.
758 //
759 // In debug mode, both of these will write invalid data into the claimed or
760 // dropped space.
761 //
762 // If the current stack pointer (according to StackPointer()) is csp, then it
763 // must be aligned to 16 bytes and the size claimed or dropped must be a
764 // multiple of 16 bytes.
765 //
766 // Note that unit_size must be specified in bytes. For variants which take a
767 // Register count, the unit size must be a power of two.
768 inline void Claim(int64_t count, uint64_t unit_size = kXRegSize);
769 inline void Claim(const Register& count,
770 uint64_t unit_size = kXRegSize);
771 inline void Drop(int64_t count, uint64_t unit_size = kXRegSize);
772 inline void Drop(const Register& count,
773 uint64_t unit_size = kXRegSize);
774
775 // Variants of Claim and Drop, where the 'count' parameter is a SMI held in a
776 // register.
777 inline void ClaimBySMI(const Register& count_smi,
778 uint64_t unit_size = kXRegSize);
779 inline void DropBySMI(const Register& count_smi,
780 uint64_t unit_size = kXRegSize);
781
782 // Compare a register with an operand, and branch to label depending on the
783 // condition. May corrupt the status flags.
784 inline void CompareAndBranch(const Register& lhs,
785 const Operand& rhs,
786 Condition cond,
787 Label* label);
788
789 // Test the bits of register defined by bit_pattern, and branch if ANY of
790 // those bits are set. May corrupt the status flags.
791 inline void TestAndBranchIfAnySet(const Register& reg,
792 const uint64_t bit_pattern,
793 Label* label);
794
795 // Test the bits of register defined by bit_pattern, and branch if ALL of
796 // those bits are clear (ie. not set.) May corrupt the status flags.
797 inline void TestAndBranchIfAllClear(const Register& reg,
798 const uint64_t bit_pattern,
799 Label* label);
800
801 // Insert one or more instructions into the instruction stream that encode
802 // some caller-defined data. The instructions used will be executable with no
803 // side effects.
804 inline void InlineData(uint64_t data);
805
806 // Insert an instrumentation enable marker into the instruction stream.
807 inline void EnableInstrumentation();
808
809 // Insert an instrumentation disable marker into the instruction stream.
810 inline void DisableInstrumentation();
811
812 // Insert an instrumentation event marker into the instruction stream. These
813 // will be picked up by the instrumentation system to annotate an instruction
814 // profile. The argument marker_name must be a printable two character string;
815 // it will be encoded in the event marker.
816 inline void AnnotateInstrumentation(const char* marker_name);
817
818 // If emit_debug_code() is true, emit a run-time check to ensure that
819 // StackPointer() does not point below the system stack pointer.
820 //
821 // Whilst it is architecturally legal for StackPointer() to point below csp,
822 // it can be evidence of a potential bug because the ABI forbids accesses
823 // below csp.
824 //
825 // If StackPointer() is the system stack pointer (csp), then csp will be
826 // dereferenced to cause the processor (or simulator) to abort if it is not
827 // properly aligned.
828 //
829 // If emit_debug_code() is false, this emits no code.
830 void AssertStackConsistency();
831
832 // Emits a runtime assert that the CSP is aligned.
833 void AssertCspAligned();
834
835 // Preserve the callee-saved registers (as defined by AAPCS64).
836 //
837 // Higher-numbered registers are pushed before lower-numbered registers, and
838 // thus get higher addresses.
839 // Floating-point registers are pushed before general-purpose registers, and
840 // thus get higher addresses.
841 //
842 // Note that registers are not checked for invalid values. Use this method
843 // only if you know that the GC won't try to examine the values on the stack.
844 //
845 // This method must not be called unless the current stack pointer (as set by
846 // SetStackPointer) is the system stack pointer (csp), and is aligned to
847 // ActivationFrameAlignment().
848 void PushCalleeSavedRegisters();
849
850 // Restore the callee-saved registers (as defined by AAPCS64).
851 //
852 // Higher-numbered registers are popped after lower-numbered registers, and
853 // thus come from higher addresses.
854 // Floating-point registers are popped after general-purpose registers, and
855 // thus come from higher addresses.
856 //
857 // This method must not be called unless the current stack pointer (as set by
858 // SetStackPointer) is the system stack pointer (csp), and is aligned to
859 // ActivationFrameAlignment().
860 void PopCalleeSavedRegisters();
861
862 // Set the current stack pointer, but don't generate any code.
SetStackPointer(const Register & stack_pointer)863 inline void SetStackPointer(const Register& stack_pointer) {
864 DCHECK(!TmpList()->IncludesAliasOf(stack_pointer));
865 sp_ = stack_pointer;
866 }
867
868 // Return the current stack pointer, as set by SetStackPointer.
StackPointer()869 inline const Register& StackPointer() const {
870 return sp_;
871 }
872
873 // Align csp for a frame, as per ActivationFrameAlignment, and make it the
874 // current stack pointer.
AlignAndSetCSPForFrame()875 inline void AlignAndSetCSPForFrame() {
876 int sp_alignment = ActivationFrameAlignment();
877 // AAPCS64 mandates at least 16-byte alignment.
878 DCHECK(sp_alignment >= 16);
879 DCHECK(base::bits::IsPowerOfTwo32(sp_alignment));
880 Bic(csp, StackPointer(), sp_alignment - 1);
881 SetStackPointer(csp);
882 }
883
884 // Push the system stack pointer (csp) down to allow the same to be done to
885 // the current stack pointer (according to StackPointer()). This must be
886 // called _before_ accessing the memory.
887 //
888 // This is necessary when pushing or otherwise adding things to the stack, to
889 // satisfy the AAPCS64 constraint that the memory below the system stack
890 // pointer is not accessed. The amount pushed will be increased as necessary
891 // to ensure csp remains aligned to 16 bytes.
892 //
893 // This method asserts that StackPointer() is not csp, since the call does
894 // not make sense in that context.
895 inline void BumpSystemStackPointer(const Operand& space);
896
897 // Re-synchronizes the system stack pointer (csp) with the current stack
898 // pointer (according to StackPointer()).
899 //
900 // This method asserts that StackPointer() is not csp, since the call does
901 // not make sense in that context.
902 inline void SyncSystemStackPointer();
903
904 // Helpers ------------------------------------------------------------------
905 // Root register.
906 inline void InitializeRootRegister();
907
908 void AssertFPCRState(Register fpcr = NoReg);
909 void CanonicalizeNaN(const FPRegister& dst, const FPRegister& src);
CanonicalizeNaN(const FPRegister & reg)910 void CanonicalizeNaN(const FPRegister& reg) {
911 CanonicalizeNaN(reg, reg);
912 }
913
914 // Load an object from the root table.
915 void LoadRoot(CPURegister destination,
916 Heap::RootListIndex index);
917 // Store an object to the root table.
918 void StoreRoot(Register source,
919 Heap::RootListIndex index);
920
921 // Load both TrueValue and FalseValue roots.
922 void LoadTrueFalseRoots(Register true_root, Register false_root);
923
924 void LoadHeapObject(Register dst, Handle<HeapObject> object);
925
LoadObject(Register result,Handle<Object> object)926 void LoadObject(Register result, Handle<Object> object) {
927 AllowDeferredHandleDereference heap_object_check;
928 if (object->IsHeapObject()) {
929 LoadHeapObject(result, Handle<HeapObject>::cast(object));
930 } else {
931 DCHECK(object->IsSmi());
932 Mov(result, Operand(object));
933 }
934 }
935
936 static int SafepointRegisterStackIndex(int reg_code);
937
938 // This is required for compatibility with architecture independant code.
939 // Remove if not needed.
Move(Register dst,Register src)940 inline void Move(Register dst, Register src) { Mov(dst, src); }
Move(Register dst,Handle<Object> x)941 inline void Move(Register dst, Handle<Object> x) { LoadObject(dst, x); }
Move(Register dst,Smi * src)942 inline void Move(Register dst, Smi* src) { Mov(dst, src); }
943
944 void LoadInstanceDescriptors(Register map,
945 Register descriptors);
946 void EnumLengthUntagged(Register dst, Register map);
947 void EnumLengthSmi(Register dst, Register map);
948 void NumberOfOwnDescriptors(Register dst, Register map);
949 void LoadAccessor(Register dst, Register holder, int accessor_index,
950 AccessorComponent accessor);
951
952 template<typename Field>
DecodeField(Register dst,Register src)953 void DecodeField(Register dst, Register src) {
954 static const int shift = Field::kShift;
955 static const int setbits = CountSetBits(Field::kMask, 32);
956 Ubfx(dst, src, shift, setbits);
957 }
958
959 template<typename Field>
DecodeField(Register reg)960 void DecodeField(Register reg) {
961 DecodeField<Field>(reg, reg);
962 }
963
964 // ---- SMI and Number Utilities ----
965
966 inline void SmiTag(Register dst, Register src);
967 inline void SmiTag(Register smi);
968 inline void SmiUntag(Register dst, Register src);
969 inline void SmiUntag(Register smi);
970 inline void SmiUntagToDouble(FPRegister dst,
971 Register src,
972 UntagMode mode = kNotSpeculativeUntag);
973 inline void SmiUntagToFloat(FPRegister dst,
974 Register src,
975 UntagMode mode = kNotSpeculativeUntag);
976
977 // Tag and push in one step.
978 inline void SmiTagAndPush(Register src);
979 inline void SmiTagAndPush(Register src1, Register src2);
980
981 inline void JumpIfSmi(Register value,
982 Label* smi_label,
983 Label* not_smi_label = NULL);
984 inline void JumpIfNotSmi(Register value, Label* not_smi_label);
985 inline void JumpIfBothSmi(Register value1,
986 Register value2,
987 Label* both_smi_label,
988 Label* not_smi_label = NULL);
989 inline void JumpIfEitherSmi(Register value1,
990 Register value2,
991 Label* either_smi_label,
992 Label* not_smi_label = NULL);
993 inline void JumpIfEitherNotSmi(Register value1,
994 Register value2,
995 Label* not_smi_label);
996 inline void JumpIfBothNotSmi(Register value1,
997 Register value2,
998 Label* not_smi_label);
999
1000 // Abort execution if argument is a smi, enabled via --debug-code.
1001 void AssertNotSmi(Register object, BailoutReason reason = kOperandIsASmi);
1002 void AssertSmi(Register object, BailoutReason reason = kOperandIsNotASmi);
1003
1004 inline void ObjectTag(Register tagged_obj, Register obj);
1005 inline void ObjectUntag(Register untagged_obj, Register obj);
1006
1007 // Abort execution if argument is not a name, enabled via --debug-code.
1008 void AssertName(Register object);
1009
1010 // Abort execution if argument is not a JSFunction, enabled via --debug-code.
1011 void AssertFunction(Register object);
1012
1013 // Abort execution if argument is not a JSGeneratorObject,
1014 // enabled via --debug-code.
1015 void AssertGeneratorObject(Register object);
1016
1017 // Abort execution if argument is not a JSBoundFunction,
1018 // enabled via --debug-code.
1019 void AssertBoundFunction(Register object);
1020
1021 // Abort execution if argument is not a JSReceiver, enabled via --debug-code.
1022 void AssertReceiver(Register object);
1023
1024 // Abort execution if argument is not undefined or an AllocationSite, enabled
1025 // via --debug-code.
1026 void AssertUndefinedOrAllocationSite(Register object, Register scratch);
1027
1028 // Abort execution if argument is not a string, enabled via --debug-code.
1029 void AssertString(Register object);
1030
1031 // Abort execution if argument is not a positive or zero integer, enabled via
1032 // --debug-code.
1033 void AssertPositiveOrZero(Register value);
1034
1035 // Abort execution if argument is not a number (heap number or smi).
1036 void AssertNumber(Register value);
1037 void AssertNotNumber(Register value);
1038
1039 void JumpIfHeapNumber(Register object, Label* on_heap_number,
1040 SmiCheckType smi_check_type = DONT_DO_SMI_CHECK);
1041 void JumpIfNotHeapNumber(Register object, Label* on_not_heap_number,
1042 SmiCheckType smi_check_type = DONT_DO_SMI_CHECK);
1043
1044 // Sets the vs flag if the input is -0.0.
1045 void TestForMinusZero(DoubleRegister input);
1046
1047 // Jump to label if the input double register contains -0.0.
1048 void JumpIfMinusZero(DoubleRegister input, Label* on_negative_zero);
1049
1050 // Jump to label if the input integer register contains the double precision
1051 // floating point representation of -0.0.
1052 void JumpIfMinusZero(Register input, Label* on_negative_zero);
1053
1054 // Saturate a signed 32-bit integer in input to an unsigned 8-bit integer in
1055 // output.
1056 void ClampInt32ToUint8(Register in_out);
1057 void ClampInt32ToUint8(Register output, Register input);
1058
1059 // Saturate a double in input to an unsigned 8-bit integer in output.
1060 void ClampDoubleToUint8(Register output,
1061 DoubleRegister input,
1062 DoubleRegister dbl_scratch);
1063
1064 // Try to represent a double as a signed 32-bit int.
1065 // This succeeds if the result compares equal to the input, so inputs of -0.0
1066 // are represented as 0 and handled as a success.
1067 //
1068 // On output the Z flag is set if the operation was successful.
1069 void TryRepresentDoubleAsInt32(Register as_int,
1070 FPRegister value,
1071 FPRegister scratch_d,
1072 Label* on_successful_conversion = NULL,
1073 Label* on_failed_conversion = NULL) {
1074 DCHECK(as_int.Is32Bits());
1075 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion,
1076 on_failed_conversion);
1077 }
1078
1079 // Try to represent a double as a signed 64-bit int.
1080 // This succeeds if the result compares equal to the input, so inputs of -0.0
1081 // are represented as 0 and handled as a success.
1082 //
1083 // On output the Z flag is set if the operation was successful.
1084 void TryRepresentDoubleAsInt64(Register as_int,
1085 FPRegister value,
1086 FPRegister scratch_d,
1087 Label* on_successful_conversion = NULL,
1088 Label* on_failed_conversion = NULL) {
1089 DCHECK(as_int.Is64Bits());
1090 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion,
1091 on_failed_conversion);
1092 }
1093
1094 // ---- Object Utilities ----
1095
1096 // Initialize fields with filler values. Fields starting at |current_address|
1097 // not including |end_address| are overwritten with the value in |filler|. At
1098 // the end the loop, |current_address| takes the value of |end_address|.
1099 void InitializeFieldsWithFiller(Register current_address,
1100 Register end_address, Register filler);
1101
1102 // ---- String Utilities ----
1103
1104
1105 // Jump to label if either object is not a sequential one-byte string.
1106 // Optionally perform a smi check on the objects first.
1107 void JumpIfEitherIsNotSequentialOneByteStrings(
1108 Register first, Register second, Register scratch1, Register scratch2,
1109 Label* failure, SmiCheckType smi_check = DO_SMI_CHECK);
1110
1111 // Check if instance type is sequential one-byte string and jump to label if
1112 // it is not.
1113 void JumpIfInstanceTypeIsNotSequentialOneByte(Register type, Register scratch,
1114 Label* failure);
1115
1116 // Checks if both instance types are sequential one-byte strings and jumps to
1117 // label if either is not.
1118 void JumpIfEitherInstanceTypeIsNotSequentialOneByte(
1119 Register first_object_instance_type, Register second_object_instance_type,
1120 Register scratch1, Register scratch2, Label* failure);
1121
1122 // Checks if both instance types are sequential one-byte strings and jumps to
1123 // label if either is not.
1124 void JumpIfBothInstanceTypesAreNotSequentialOneByte(
1125 Register first_object_instance_type, Register second_object_instance_type,
1126 Register scratch1, Register scratch2, Label* failure);
1127
1128 void JumpIfNotUniqueNameInstanceType(Register type, Label* not_unique_name);
1129
1130 // ---- Calling / Jumping helpers ----
1131
1132 // This is required for compatibility in architecture indepenedant code.
jmp(Label * L)1133 inline void jmp(Label* L) { B(L); }
1134
1135 void CallStub(CodeStub* stub, TypeFeedbackId ast_id = TypeFeedbackId::None());
1136 void TailCallStub(CodeStub* stub);
1137
1138 void CallRuntime(const Runtime::Function* f,
1139 int num_arguments,
1140 SaveFPRegsMode save_doubles = kDontSaveFPRegs);
1141
1142 // Convenience function: Same as above, but takes the fid instead.
1143 void CallRuntime(Runtime::FunctionId fid, int num_arguments,
1144 SaveFPRegsMode save_doubles = kDontSaveFPRegs) {
1145 CallRuntime(Runtime::FunctionForId(fid), num_arguments, save_doubles);
1146 }
1147
1148 // Convenience function: Same as above, but takes the fid instead.
1149 void CallRuntime(Runtime::FunctionId fid,
1150 SaveFPRegsMode save_doubles = kDontSaveFPRegs) {
1151 const Runtime::Function* function = Runtime::FunctionForId(fid);
1152 CallRuntime(function, function->nargs, save_doubles);
1153 }
1154
CallRuntimeSaveDoubles(Runtime::FunctionId fid)1155 void CallRuntimeSaveDoubles(Runtime::FunctionId fid) {
1156 const Runtime::Function* function = Runtime::FunctionForId(fid);
1157 CallRuntime(function, function->nargs, kSaveFPRegs);
1158 }
1159
1160 void TailCallRuntime(Runtime::FunctionId fid);
1161
1162 int ActivationFrameAlignment();
1163
1164 // Calls a C function.
1165 // The called function is not allowed to trigger a
1166 // garbage collection, since that might move the code and invalidate the
1167 // return address (unless this is somehow accounted for by the called
1168 // function).
1169 void CallCFunction(ExternalReference function,
1170 int num_reg_arguments);
1171 void CallCFunction(ExternalReference function,
1172 int num_reg_arguments,
1173 int num_double_arguments);
1174 void CallCFunction(Register function,
1175 int num_reg_arguments,
1176 int num_double_arguments);
1177
1178 // Jump to a runtime routine.
1179 void JumpToExternalReference(const ExternalReference& builtin,
1180 bool builtin_exit_frame = false);
1181
1182 // Convenience function: call an external reference.
1183 void CallExternalReference(const ExternalReference& ext,
1184 int num_arguments);
1185
1186
1187 void Jump(Register target);
1188 void Jump(Address target, RelocInfo::Mode rmode, Condition cond = al);
1189 void Jump(Handle<Code> code, RelocInfo::Mode rmode, Condition cond = al);
1190 void Jump(intptr_t target, RelocInfo::Mode rmode, Condition cond = al);
1191
1192 void Call(Register target);
1193 void Call(Label* target);
1194 void Call(Address target, RelocInfo::Mode rmode);
1195 void Call(Handle<Code> code,
1196 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
1197 TypeFeedbackId ast_id = TypeFeedbackId::None());
1198
1199 // For every Call variant, there is a matching CallSize function that returns
1200 // the size (in bytes) of the call sequence.
1201 static int CallSize(Register target);
1202 static int CallSize(Label* target);
1203 static int CallSize(Address target, RelocInfo::Mode rmode);
1204 static int CallSize(Handle<Code> code,
1205 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
1206 TypeFeedbackId ast_id = TypeFeedbackId::None());
1207
1208 // Removes current frame and its arguments from the stack preserving
1209 // the arguments and a return address pushed to the stack for the next call.
1210 // Both |callee_args_count| and |caller_args_count_reg| do not include
1211 // receiver. |callee_args_count| is not modified, |caller_args_count_reg|
1212 // is trashed.
1213 void PrepareForTailCall(const ParameterCount& callee_args_count,
1214 Register caller_args_count_reg, Register scratch0,
1215 Register scratch1);
1216
1217 // Registers used through the invocation chain are hard-coded.
1218 // We force passing the parameters to ensure the contracts are correctly
1219 // honoured by the caller.
1220 // 'function' must be x1.
1221 // 'actual' must use an immediate or x0.
1222 // 'expected' must use an immediate or x2.
1223 // 'call_kind' must be x5.
1224 void InvokePrologue(const ParameterCount& expected,
1225 const ParameterCount& actual,
1226 Label* done,
1227 InvokeFlag flag,
1228 bool* definitely_mismatches,
1229 const CallWrapper& call_wrapper);
1230 void FloodFunctionIfStepping(Register fun, Register new_target,
1231 const ParameterCount& expected,
1232 const ParameterCount& actual);
1233 void InvokeFunctionCode(Register function, Register new_target,
1234 const ParameterCount& expected,
1235 const ParameterCount& actual, InvokeFlag flag,
1236 const CallWrapper& call_wrapper);
1237 // Invoke the JavaScript function in the given register.
1238 // Changes the current context to the context in the function before invoking.
1239 void InvokeFunction(Register function,
1240 Register new_target,
1241 const ParameterCount& actual,
1242 InvokeFlag flag,
1243 const CallWrapper& call_wrapper);
1244 void InvokeFunction(Register function,
1245 const ParameterCount& expected,
1246 const ParameterCount& actual,
1247 InvokeFlag flag,
1248 const CallWrapper& call_wrapper);
1249 void InvokeFunction(Handle<JSFunction> function,
1250 const ParameterCount& expected,
1251 const ParameterCount& actual,
1252 InvokeFlag flag,
1253 const CallWrapper& call_wrapper);
1254
1255
1256 // ---- Floating point helpers ----
1257
1258 // Perform a conversion from a double to a signed int64. If the input fits in
1259 // range of the 64-bit result, execution branches to done. Otherwise,
1260 // execution falls through, and the sign of the result can be used to
1261 // determine if overflow was towards positive or negative infinity.
1262 //
1263 // On successful conversion, the least significant 32 bits of the result are
1264 // equivalent to the ECMA-262 operation "ToInt32".
1265 //
1266 // Only public for the test code in test-code-stubs-arm64.cc.
1267 void TryConvertDoubleToInt64(Register result,
1268 DoubleRegister input,
1269 Label* done);
1270
1271 // Performs a truncating conversion of a floating point number as used by
1272 // the JS bitwise operations. See ECMA-262 9.5: ToInt32.
1273 // Exits with 'result' holding the answer.
1274 void TruncateDoubleToI(Register result, DoubleRegister double_input);
1275
1276 // Performs a truncating conversion of a heap number as used by
1277 // the JS bitwise operations. See ECMA-262 9.5: ToInt32. 'result' and 'input'
1278 // must be different registers. Exits with 'result' holding the answer.
1279 void TruncateHeapNumberToI(Register result, Register object);
1280
1281 // Converts the smi or heap number in object to an int32 using the rules
1282 // for ToInt32 as described in ECMAScript 9.5.: the value is truncated
1283 // and brought into the range -2^31 .. +2^31 - 1. 'result' and 'input' must be
1284 // different registers.
1285 void TruncateNumberToI(Register object,
1286 Register result,
1287 Register heap_number_map,
1288 Label* not_int32);
1289
1290 // ---- Code generation helpers ----
1291
set_generating_stub(bool value)1292 void set_generating_stub(bool value) { generating_stub_ = value; }
generating_stub()1293 bool generating_stub() const { return generating_stub_; }
1294 #if DEBUG
set_allow_macro_instructions(bool value)1295 void set_allow_macro_instructions(bool value) {
1296 allow_macro_instructions_ = value;
1297 }
allow_macro_instructions()1298 bool allow_macro_instructions() const { return allow_macro_instructions_; }
1299 #endif
use_real_aborts()1300 bool use_real_aborts() const { return use_real_aborts_; }
set_has_frame(bool value)1301 void set_has_frame(bool value) { has_frame_ = value; }
has_frame()1302 bool has_frame() const { return has_frame_; }
1303 bool AllowThisStubCall(CodeStub* stub);
1304
1305 class NoUseRealAbortsScope {
1306 public:
NoUseRealAbortsScope(MacroAssembler * masm)1307 explicit NoUseRealAbortsScope(MacroAssembler* masm) :
1308 saved_(masm->use_real_aborts_), masm_(masm) {
1309 masm_->use_real_aborts_ = false;
1310 }
~NoUseRealAbortsScope()1311 ~NoUseRealAbortsScope() {
1312 masm_->use_real_aborts_ = saved_;
1313 }
1314 private:
1315 bool saved_;
1316 MacroAssembler* masm_;
1317 };
1318
1319 // ---------------------------------------------------------------------------
1320 // Debugger Support
1321
1322 void DebugBreak();
1323
1324 // ---------------------------------------------------------------------------
1325 // Exception handling
1326
1327 // Push a new stack handler and link into stack handler chain.
1328 void PushStackHandler();
1329
1330 // Unlink the stack handler on top of the stack from the stack handler chain.
1331 // Must preserve the result register.
1332 void PopStackHandler();
1333
1334
1335 // ---------------------------------------------------------------------------
1336 // Allocation support
1337
1338 // Allocate an object in new space or old space. The object_size is
1339 // specified either in bytes or in words if the allocation flag SIZE_IN_WORDS
1340 // is passed. The allocated object is returned in result.
1341 //
1342 // If the new space is exhausted control continues at the gc_required label.
1343 // In this case, the result and scratch registers may still be clobbered.
1344 void Allocate(Register object_size, Register result, Register result_end,
1345 Register scratch, Label* gc_required, AllocationFlags flags);
1346
1347 void Allocate(int object_size,
1348 Register result,
1349 Register scratch1,
1350 Register scratch2,
1351 Label* gc_required,
1352 AllocationFlags flags);
1353
1354 // FastAllocate is right now only used for folded allocations. It just
1355 // increments the top pointer without checking against limit. This can only
1356 // be done if it was proved earlier that the allocation will succeed.
1357 void FastAllocate(Register object_size, Register result, Register result_end,
1358 Register scratch, AllocationFlags flags);
1359
1360 void FastAllocate(int object_size, Register result, Register scratch1,
1361 Register scratch2, AllocationFlags flags);
1362
1363 void AllocateTwoByteString(Register result,
1364 Register length,
1365 Register scratch1,
1366 Register scratch2,
1367 Register scratch3,
1368 Label* gc_required);
1369 void AllocateOneByteString(Register result, Register length,
1370 Register scratch1, Register scratch2,
1371 Register scratch3, Label* gc_required);
1372 void AllocateTwoByteConsString(Register result,
1373 Register length,
1374 Register scratch1,
1375 Register scratch2,
1376 Label* gc_required);
1377 void AllocateOneByteConsString(Register result, Register length,
1378 Register scratch1, Register scratch2,
1379 Label* gc_required);
1380 void AllocateTwoByteSlicedString(Register result,
1381 Register length,
1382 Register scratch1,
1383 Register scratch2,
1384 Label* gc_required);
1385 void AllocateOneByteSlicedString(Register result, Register length,
1386 Register scratch1, Register scratch2,
1387 Label* gc_required);
1388
1389 // Allocates a heap number or jumps to the gc_required label if the young
1390 // space is full and a scavenge is needed.
1391 // All registers are clobbered.
1392 // If no heap_number_map register is provided, the function will take care of
1393 // loading it.
1394 void AllocateHeapNumber(Register result,
1395 Label* gc_required,
1396 Register scratch1,
1397 Register scratch2,
1398 CPURegister value = NoFPReg,
1399 CPURegister heap_number_map = NoReg,
1400 MutableMode mode = IMMUTABLE);
1401
1402 // Allocate and initialize a JSValue wrapper with the specified {constructor}
1403 // and {value}.
1404 void AllocateJSValue(Register result, Register constructor, Register value,
1405 Register scratch1, Register scratch2,
1406 Label* gc_required);
1407
1408 // ---------------------------------------------------------------------------
1409 // Support functions.
1410
1411 // Machine code version of Map::GetConstructor().
1412 // |temp| holds |result|'s map when done, and |temp2| its instance type.
1413 void GetMapConstructor(Register result, Register map, Register temp,
1414 Register temp2);
1415
1416 void TryGetFunctionPrototype(Register function, Register result,
1417 Register scratch, Label* miss);
1418
1419 // Compare object type for heap object. heap_object contains a non-Smi
1420 // whose object type should be compared with the given type. This both
1421 // sets the flags and leaves the object type in the type_reg register.
1422 // It leaves the map in the map register (unless the type_reg and map register
1423 // are the same register). It leaves the heap object in the heap_object
1424 // register unless the heap_object register is the same register as one of the
1425 // other registers.
1426 void CompareObjectType(Register heap_object,
1427 Register map,
1428 Register type_reg,
1429 InstanceType type);
1430
1431
1432 // Compare object type for heap object, and branch if equal (or not.)
1433 // heap_object contains a non-Smi whose object type should be compared with
1434 // the given type. This both sets the flags and leaves the object type in
1435 // the type_reg register. It leaves the map in the map register (unless the
1436 // type_reg and map register are the same register). It leaves the heap
1437 // object in the heap_object register unless the heap_object register is the
1438 // same register as one of the other registers.
1439 void JumpIfObjectType(Register object,
1440 Register map,
1441 Register type_reg,
1442 InstanceType type,
1443 Label* if_cond_pass,
1444 Condition cond = eq);
1445
1446 void JumpIfNotObjectType(Register object,
1447 Register map,
1448 Register type_reg,
1449 InstanceType type,
1450 Label* if_not_object);
1451
1452 // Compare instance type in a map. map contains a valid map object whose
1453 // object type should be compared with the given type. This both
1454 // sets the flags and leaves the object type in the type_reg register.
1455 void CompareInstanceType(Register map,
1456 Register type_reg,
1457 InstanceType type);
1458
1459 // Compare an object's map with the specified map. Condition flags are set
1460 // with result of map compare.
1461 void CompareObjectMap(Register obj, Heap::RootListIndex index);
1462
1463 // Compare an object's map with the specified map. Condition flags are set
1464 // with result of map compare.
1465 void CompareObjectMap(Register obj, Register scratch, Handle<Map> map);
1466
1467 // As above, but the map of the object is already loaded into the register
1468 // which is preserved by the code generated.
1469 void CompareMap(Register obj_map,
1470 Handle<Map> map);
1471
1472 // Check if the map of an object is equal to a specified map and branch to
1473 // label if not. Skip the smi check if not required (object is known to be a
1474 // heap object). If mode is ALLOW_ELEMENT_TRANSITION_MAPS, then also match
1475 // against maps that are ElementsKind transition maps of the specified map.
1476 void CheckMap(Register obj,
1477 Register scratch,
1478 Handle<Map> map,
1479 Label* fail,
1480 SmiCheckType smi_check_type);
1481
1482
1483 void CheckMap(Register obj,
1484 Register scratch,
1485 Heap::RootListIndex index,
1486 Label* fail,
1487 SmiCheckType smi_check_type);
1488
1489 // As above, but the map of the object is already loaded into obj_map, and is
1490 // preserved.
1491 void CheckMap(Register obj_map,
1492 Handle<Map> map,
1493 Label* fail,
1494 SmiCheckType smi_check_type);
1495
1496 // Check if the map of an object is equal to a specified weak map and branch
1497 // to a specified target if equal. Skip the smi check if not required
1498 // (object is known to be a heap object)
1499 void DispatchWeakMap(Register obj, Register scratch1, Register scratch2,
1500 Handle<WeakCell> cell, Handle<Code> success,
1501 SmiCheckType smi_check_type);
1502
1503 // Compare the given value and the value of weak cell.
1504 void CmpWeakValue(Register value, Handle<WeakCell> cell, Register scratch);
1505
1506 void GetWeakValue(Register value, Handle<WeakCell> cell);
1507
1508 // Load the value of the weak cell in the value register. Branch to the given
1509 // miss label if the weak cell was cleared.
1510 void LoadWeakValue(Register value, Handle<WeakCell> cell, Label* miss);
1511
1512 // Test the bitfield of the heap object map with mask and set the condition
1513 // flags. The object register is preserved.
1514 void TestMapBitfield(Register object, uint64_t mask);
1515
1516 // Load the elements kind field from a map, and return it in the result
1517 // register.
1518 void LoadElementsKindFromMap(Register result, Register map);
1519
1520 // Load the value from the root list and push it onto the stack.
1521 void PushRoot(Heap::RootListIndex index);
1522
1523 // Compare the object in a register to a value from the root list.
1524 void CompareRoot(const Register& obj, Heap::RootListIndex index);
1525
1526 // Compare the object in a register to a value and jump if they are equal.
1527 void JumpIfRoot(const Register& obj,
1528 Heap::RootListIndex index,
1529 Label* if_equal);
1530
1531 // Compare the object in a register to a value and jump if they are not equal.
1532 void JumpIfNotRoot(const Register& obj,
1533 Heap::RootListIndex index,
1534 Label* if_not_equal);
1535
1536 // Load and check the instance type of an object for being a unique name.
1537 // Loads the type into the second argument register.
1538 // The object and type arguments can be the same register; in that case it
1539 // will be overwritten with the type.
1540 // Fall-through if the object was a string and jump on fail otherwise.
1541 inline void IsObjectNameType(Register object, Register type, Label* fail);
1542
1543 // Load and check the instance type of an object for being a string.
1544 // Loads the type into the second argument register.
1545 // The object and type arguments can be the same register; in that case it
1546 // will be overwritten with the type.
1547 // Jumps to not_string or string appropriate. If the appropriate label is
1548 // NULL, fall through.
1549 inline void IsObjectJSStringType(Register object, Register type,
1550 Label* not_string, Label* string = NULL);
1551
1552 // Compare the contents of a register with an operand, and branch to true,
1553 // false or fall through, depending on condition.
1554 void CompareAndSplit(const Register& lhs,
1555 const Operand& rhs,
1556 Condition cond,
1557 Label* if_true,
1558 Label* if_false,
1559 Label* fall_through);
1560
1561 // Test the bits of register defined by bit_pattern, and branch to
1562 // if_any_set, if_all_clear or fall_through accordingly.
1563 void TestAndSplit(const Register& reg,
1564 uint64_t bit_pattern,
1565 Label* if_all_clear,
1566 Label* if_any_set,
1567 Label* fall_through);
1568
1569 // Check if a map for a JSObject indicates that the object can have both smi
1570 // and HeapObject elements. Jump to the specified label if it does not.
1571 void CheckFastObjectElements(Register map, Register scratch, Label* fail);
1572
1573 // Check to see if number can be stored as a double in FastDoubleElements.
1574 // If it can, store it at the index specified by key_reg in the array,
1575 // otherwise jump to fail.
1576 void StoreNumberToDoubleElements(Register value_reg,
1577 Register key_reg,
1578 Register elements_reg,
1579 Register scratch1,
1580 FPRegister fpscratch1,
1581 Label* fail,
1582 int elements_offset = 0);
1583
1584 // ---------------------------------------------------------------------------
1585 // Inline caching support.
1586
1587 void EmitSeqStringSetCharCheck(Register string,
1588 Register index,
1589 SeqStringSetCharCheckIndexType index_type,
1590 Register scratch,
1591 uint32_t encoding_mask);
1592
1593 // Hash the interger value in 'key' register.
1594 // It uses the same algorithm as ComputeIntegerHash in utils.h.
1595 void GetNumberHash(Register key, Register scratch);
1596
1597 // ---------------------------------------------------------------------------
1598 // Frames.
1599
1600 // Load the type feedback vector from a JavaScript frame.
1601 void EmitLoadTypeFeedbackVector(Register vector);
1602
1603 // Activation support.
1604 void EnterFrame(StackFrame::Type type);
1605 void EnterFrame(StackFrame::Type type, bool load_constant_pool_pointer_reg);
1606 void LeaveFrame(StackFrame::Type type);
1607
1608 void EnterBuiltinFrame(Register context, Register target, Register argc);
1609 void LeaveBuiltinFrame(Register context, Register target, Register argc);
1610
1611 // Returns map with validated enum cache in object register.
1612 void CheckEnumCache(Register object, Register scratch0, Register scratch1,
1613 Register scratch2, Register scratch3, Register scratch4,
1614 Label* call_runtime);
1615
1616 // AllocationMemento support. Arrays may have an associated
1617 // AllocationMemento object that can be checked for in order to pretransition
1618 // to another type.
1619 // On entry, receiver should point to the array object.
1620 // If allocation info is present, the Z flag is set (so that the eq
1621 // condition will pass).
1622 void TestJSArrayForAllocationMemento(Register receiver,
1623 Register scratch1,
1624 Register scratch2,
1625 Label* no_memento_found);
1626
JumpIfJSArrayHasAllocationMemento(Register receiver,Register scratch1,Register scratch2,Label * memento_found)1627 void JumpIfJSArrayHasAllocationMemento(Register receiver,
1628 Register scratch1,
1629 Register scratch2,
1630 Label* memento_found) {
1631 Label no_memento_found;
1632 TestJSArrayForAllocationMemento(receiver, scratch1, scratch2,
1633 &no_memento_found);
1634 B(eq, memento_found);
1635 Bind(&no_memento_found);
1636 }
1637
1638 // The stack pointer has to switch between csp and jssp when setting up and
1639 // destroying the exit frame. Hence preserving/restoring the registers is
1640 // slightly more complicated than simple push/pop operations.
1641 void ExitFramePreserveFPRegs();
1642 void ExitFrameRestoreFPRegs();
1643
1644 // Generates function and stub prologue code.
1645 void StubPrologue(StackFrame::Type type, int frame_slots);
1646 void Prologue(bool code_pre_aging);
1647
1648 // Enter exit frame. Exit frames are used when calling C code from generated
1649 // (JavaScript) code.
1650 //
1651 // The stack pointer must be jssp on entry, and will be set to csp by this
1652 // function. The frame pointer is also configured, but the only other
1653 // registers modified by this function are the provided scratch register, and
1654 // jssp.
1655 //
1656 // The 'extra_space' argument can be used to allocate some space in the exit
1657 // frame that will be ignored by the GC. This space will be reserved in the
1658 // bottom of the frame immediately above the return address slot.
1659 //
1660 // Set up a stack frame and registers as follows:
1661 // fp[8]: CallerPC (lr)
1662 // fp -> fp[0]: CallerFP (old fp)
1663 // fp[-8]: SPOffset (new csp)
1664 // fp[-16]: CodeObject()
1665 // fp[-16 - fp-size]: Saved doubles, if saved_doubles is true.
1666 // csp[8]: Memory reserved for the caller if extra_space != 0.
1667 // Alignment padding, if necessary.
1668 // csp -> csp[0]: Space reserved for the return address.
1669 //
1670 // This function also stores the new frame information in the top frame, so
1671 // that the new frame becomes the current frame.
1672 void EnterExitFrame(bool save_doubles, const Register& scratch,
1673 int extra_space = 0,
1674 StackFrame::Type frame_type = StackFrame::EXIT);
1675
1676 // Leave the current exit frame, after a C function has returned to generated
1677 // (JavaScript) code.
1678 //
1679 // This effectively unwinds the operation of EnterExitFrame:
1680 // * Preserved doubles are restored (if restore_doubles is true).
1681 // * The frame information is removed from the top frame.
1682 // * The exit frame is dropped.
1683 // * The stack pointer is reset to jssp.
1684 //
1685 // The stack pointer must be csp on entry.
1686 void LeaveExitFrame(bool save_doubles,
1687 const Register& scratch,
1688 bool restore_context);
1689
1690 void LoadContext(Register dst, int context_chain_length);
1691
1692 // Load the global object from the current context.
LoadGlobalObject(Register dst)1693 void LoadGlobalObject(Register dst) {
1694 LoadNativeContextSlot(Context::EXTENSION_INDEX, dst);
1695 }
1696
1697 // Load the global proxy from the current context.
LoadGlobalProxy(Register dst)1698 void LoadGlobalProxy(Register dst) {
1699 LoadNativeContextSlot(Context::GLOBAL_PROXY_INDEX, dst);
1700 }
1701
1702 // Emit code for a truncating division by a constant. The dividend register is
1703 // unchanged. Dividend and result must be different.
1704 void TruncatingDiv(Register result, Register dividend, int32_t divisor);
1705
1706 // ---------------------------------------------------------------------------
1707 // StatsCounter support
1708
1709 void SetCounter(StatsCounter* counter, int value, Register scratch1,
1710 Register scratch2);
1711 void IncrementCounter(StatsCounter* counter, int value, Register scratch1,
1712 Register scratch2);
1713 void DecrementCounter(StatsCounter* counter, int value, Register scratch1,
1714 Register scratch2);
1715
1716 // ---------------------------------------------------------------------------
1717 // Garbage collector support (GC).
1718
1719 enum RememberedSetFinalAction {
1720 kReturnAtEnd,
1721 kFallThroughAtEnd
1722 };
1723
1724 // Record in the remembered set the fact that we have a pointer to new space
1725 // at the address pointed to by the addr register. Only works if addr is not
1726 // in new space.
1727 void RememberedSetHelper(Register object, // Used for debug code.
1728 Register addr,
1729 Register scratch1,
1730 SaveFPRegsMode save_fp,
1731 RememberedSetFinalAction and_then);
1732
1733 // Push and pop the registers that can hold pointers, as defined by the
1734 // RegList constant kSafepointSavedRegisters.
1735 void PushSafepointRegisters();
1736 void PopSafepointRegisters();
1737
1738 void PushSafepointRegistersAndDoubles();
1739 void PopSafepointRegistersAndDoubles();
1740
1741 // Store value in register src in the safepoint stack slot for register dst.
StoreToSafepointRegisterSlot(Register src,Register dst)1742 void StoreToSafepointRegisterSlot(Register src, Register dst) {
1743 Poke(src, SafepointRegisterStackIndex(dst.code()) * kPointerSize);
1744 }
1745
1746 // Load the value of the src register from its safepoint stack slot
1747 // into register dst.
LoadFromSafepointRegisterSlot(Register dst,Register src)1748 void LoadFromSafepointRegisterSlot(Register dst, Register src) {
1749 Peek(src, SafepointRegisterStackIndex(dst.code()) * kPointerSize);
1750 }
1751
1752 void CheckPageFlag(const Register& object, const Register& scratch, int mask,
1753 Condition cc, Label* condition_met);
1754
1755 void CheckPageFlagSet(const Register& object,
1756 const Register& scratch,
1757 int mask,
1758 Label* if_any_set);
1759
1760 void CheckPageFlagClear(const Register& object,
1761 const Register& scratch,
1762 int mask,
1763 Label* if_all_clear);
1764
1765 // Check if object is in new space and jump accordingly.
1766 // Register 'object' is preserved.
JumpIfNotInNewSpace(Register object,Label * branch)1767 void JumpIfNotInNewSpace(Register object,
1768 Label* branch) {
1769 InNewSpace(object, ne, branch);
1770 }
1771
JumpIfInNewSpace(Register object,Label * branch)1772 void JumpIfInNewSpace(Register object,
1773 Label* branch) {
1774 InNewSpace(object, eq, branch);
1775 }
1776
1777 // Notify the garbage collector that we wrote a pointer into an object.
1778 // |object| is the object being stored into, |value| is the object being
1779 // stored. value and scratch registers are clobbered by the operation.
1780 // The offset is the offset from the start of the object, not the offset from
1781 // the tagged HeapObject pointer. For use with FieldMemOperand(reg, off).
1782 void RecordWriteField(
1783 Register object,
1784 int offset,
1785 Register value,
1786 Register scratch,
1787 LinkRegisterStatus lr_status,
1788 SaveFPRegsMode save_fp,
1789 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
1790 SmiCheck smi_check = INLINE_SMI_CHECK,
1791 PointersToHereCheck pointers_to_here_check_for_value =
1792 kPointersToHereMaybeInteresting);
1793
1794 // As above, but the offset has the tag presubtracted. For use with
1795 // MemOperand(reg, off).
1796 inline void RecordWriteContextSlot(
1797 Register context,
1798 int offset,
1799 Register value,
1800 Register scratch,
1801 LinkRegisterStatus lr_status,
1802 SaveFPRegsMode save_fp,
1803 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
1804 SmiCheck smi_check = INLINE_SMI_CHECK,
1805 PointersToHereCheck pointers_to_here_check_for_value =
1806 kPointersToHereMaybeInteresting) {
1807 RecordWriteField(context,
1808 offset + kHeapObjectTag,
1809 value,
1810 scratch,
1811 lr_status,
1812 save_fp,
1813 remembered_set_action,
1814 smi_check,
1815 pointers_to_here_check_for_value);
1816 }
1817
1818 // Notify the garbage collector that we wrote a code entry into a
1819 // JSFunction. Only scratch is clobbered by the operation.
1820 void RecordWriteCodeEntryField(Register js_function, Register code_entry,
1821 Register scratch);
1822
1823 void RecordWriteForMap(
1824 Register object,
1825 Register map,
1826 Register dst,
1827 LinkRegisterStatus lr_status,
1828 SaveFPRegsMode save_fp);
1829
1830 // For a given |object| notify the garbage collector that the slot |address|
1831 // has been written. |value| is the object being stored. The value and
1832 // address registers are clobbered by the operation.
1833 void RecordWrite(
1834 Register object,
1835 Register address,
1836 Register value,
1837 LinkRegisterStatus lr_status,
1838 SaveFPRegsMode save_fp,
1839 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
1840 SmiCheck smi_check = INLINE_SMI_CHECK,
1841 PointersToHereCheck pointers_to_here_check_for_value =
1842 kPointersToHereMaybeInteresting);
1843
1844 // Checks the color of an object. If the object is white we jump to the
1845 // incremental marker.
1846 void JumpIfWhite(Register value, Register scratch1, Register scratch2,
1847 Register scratch3, Register scratch4, Label* value_is_white);
1848
1849 // Helper for finding the mark bits for an address.
1850 // Note that the behaviour slightly differs from other architectures.
1851 // On exit:
1852 // - addr_reg is unchanged.
1853 // - The bitmap register points at the word with the mark bits.
1854 // - The shift register contains the index of the first color bit for this
1855 // object in the bitmap.
1856 inline void GetMarkBits(Register addr_reg,
1857 Register bitmap_reg,
1858 Register shift_reg);
1859
1860 // Check if an object has a given incremental marking color.
1861 void HasColor(Register object,
1862 Register scratch0,
1863 Register scratch1,
1864 Label* has_color,
1865 int first_bit,
1866 int second_bit);
1867
1868 void JumpIfBlack(Register object,
1869 Register scratch0,
1870 Register scratch1,
1871 Label* on_black);
1872
1873
1874 // ---------------------------------------------------------------------------
1875 // Debugging.
1876
1877 // Calls Abort(msg) if the condition cond is not satisfied.
1878 // Use --debug_code to enable.
1879 void Assert(Condition cond, BailoutReason reason);
1880 void AssertRegisterIsClear(Register reg, BailoutReason reason);
1881 void AssertRegisterIsRoot(
1882 Register reg,
1883 Heap::RootListIndex index,
1884 BailoutReason reason = kRegisterDidNotMatchExpectedRoot);
1885 void AssertFastElements(Register elements);
1886
1887 // Abort if the specified register contains the invalid color bit pattern.
1888 // The pattern must be in bits [1:0] of 'reg' register.
1889 //
1890 // If emit_debug_code() is false, this emits no code.
1891 void AssertHasValidColor(const Register& reg);
1892
1893 // Abort if 'object' register doesn't point to a string object.
1894 //
1895 // If emit_debug_code() is false, this emits no code.
1896 void AssertIsString(const Register& object);
1897
1898 // Like Assert(), but always enabled.
1899 void Check(Condition cond, BailoutReason reason);
1900 void CheckRegisterIsClear(Register reg, BailoutReason reason);
1901
1902 // Print a message to stderr and abort execution.
1903 void Abort(BailoutReason reason);
1904
1905 // Conditionally load the cached Array transitioned map of type
1906 // transitioned_kind from the native context if the map in register
1907 // map_in_out is the cached Array map in the native context of
1908 // expected_kind.
1909 void LoadTransitionedArrayMapConditional(
1910 ElementsKind expected_kind,
1911 ElementsKind transitioned_kind,
1912 Register map_in_out,
1913 Register scratch1,
1914 Register scratch2,
1915 Label* no_map_match);
1916
1917 void LoadNativeContextSlot(int index, Register dst);
1918
1919 // Load the initial map from the global function. The registers function and
1920 // map can be the same, function is then overwritten.
1921 void LoadGlobalFunctionInitialMap(Register function,
1922 Register map,
1923 Register scratch);
1924
TmpList()1925 CPURegList* TmpList() { return &tmp_list_; }
FPTmpList()1926 CPURegList* FPTmpList() { return &fptmp_list_; }
1927
1928 static CPURegList DefaultTmpList();
1929 static CPURegList DefaultFPTmpList();
1930
1931 // Like printf, but print at run-time from generated code.
1932 //
1933 // The caller must ensure that arguments for floating-point placeholders
1934 // (such as %e, %f or %g) are FPRegisters, and that arguments for integer
1935 // placeholders are Registers.
1936 //
1937 // At the moment it is only possible to print the value of csp if it is the
1938 // current stack pointer. Otherwise, the MacroAssembler will automatically
1939 // update csp on every push (using BumpSystemStackPointer), so determining its
1940 // value is difficult.
1941 //
1942 // Format placeholders that refer to more than one argument, or to a specific
1943 // argument, are not supported. This includes formats like "%1$d" or "%.*d".
1944 //
1945 // This function automatically preserves caller-saved registers so that
1946 // calling code can use Printf at any point without having to worry about
1947 // corruption. The preservation mechanism generates a lot of code. If this is
1948 // a problem, preserve the important registers manually and then call
1949 // PrintfNoPreserve. Callee-saved registers are not used by Printf, and are
1950 // implicitly preserved.
1951 void Printf(const char * format,
1952 CPURegister arg0 = NoCPUReg,
1953 CPURegister arg1 = NoCPUReg,
1954 CPURegister arg2 = NoCPUReg,
1955 CPURegister arg3 = NoCPUReg);
1956
1957 // Like Printf, but don't preserve any caller-saved registers, not even 'lr'.
1958 //
1959 // The return code from the system printf call will be returned in x0.
1960 void PrintfNoPreserve(const char * format,
1961 const CPURegister& arg0 = NoCPUReg,
1962 const CPURegister& arg1 = NoCPUReg,
1963 const CPURegister& arg2 = NoCPUReg,
1964 const CPURegister& arg3 = NoCPUReg);
1965
1966 // Code ageing support functions.
1967
1968 // Code ageing on ARM64 works similarly to on ARM. When V8 wants to mark a
1969 // function as old, it replaces some of the function prologue (generated by
1970 // FullCodeGenerator::Generate) with a call to a special stub (ultimately
1971 // generated by GenerateMakeCodeYoungAgainCommon). The stub restores the
1972 // function prologue to its initial young state (indicating that it has been
1973 // recently run) and continues. A young function is therefore one which has a
1974 // normal frame setup sequence, and an old function has a code age sequence
1975 // which calls a code ageing stub.
1976
1977 // Set up a basic stack frame for young code (or code exempt from ageing) with
1978 // type FUNCTION. It may be patched later for code ageing support. This is
1979 // done by to Code::PatchPlatformCodeAge and EmitCodeAgeSequence.
1980 //
1981 // This function takes an Assembler so it can be called from either a
1982 // MacroAssembler or a PatchingAssembler context.
1983 static void EmitFrameSetupForCodeAgePatching(Assembler* assm);
1984
1985 // Call EmitFrameSetupForCodeAgePatching from a MacroAssembler context.
1986 void EmitFrameSetupForCodeAgePatching();
1987
1988 // Emit a code age sequence that calls the relevant code age stub. The code
1989 // generated by this sequence is expected to replace the code generated by
1990 // EmitFrameSetupForCodeAgePatching, and represents an old function.
1991 //
1992 // If stub is NULL, this function generates the code age sequence but omits
1993 // the stub address that is normally embedded in the instruction stream. This
1994 // can be used by debug code to verify code age sequences.
1995 static void EmitCodeAgeSequence(Assembler* assm, Code* stub);
1996
1997 // Call EmitCodeAgeSequence from a MacroAssembler context.
1998 void EmitCodeAgeSequence(Code* stub);
1999
2000 // Return true if the sequence is a young sequence geneated by
2001 // EmitFrameSetupForCodeAgePatching. Otherwise, this method asserts that the
2002 // sequence is a code age sequence (emitted by EmitCodeAgeSequence).
2003 static bool IsYoungSequence(Isolate* isolate, byte* sequence);
2004
2005 // Jumps to found label if a prototype map has dictionary elements.
2006 void JumpIfDictionaryInPrototypeChain(Register object, Register scratch0,
2007 Register scratch1, Label* found);
2008
2009 // Perform necessary maintenance operations before a push or after a pop.
2010 //
2011 // Note that size is specified in bytes.
2012 void PushPreamble(Operand total_size);
2013 void PopPostamble(Operand total_size);
2014
PushPreamble(int count,int size)2015 void PushPreamble(int count, int size) { PushPreamble(count * size); }
PopPostamble(int count,int size)2016 void PopPostamble(int count, int size) { PopPostamble(count * size); }
2017
2018 private:
2019 // The actual Push and Pop implementations. These don't generate any code
2020 // other than that required for the push or pop. This allows
2021 // (Push|Pop)CPURegList to bundle together run-time assertions for a large
2022 // block of registers.
2023 //
2024 // Note that size is per register, and is specified in bytes.
2025 void PushHelper(int count, int size,
2026 const CPURegister& src0, const CPURegister& src1,
2027 const CPURegister& src2, const CPURegister& src3);
2028 void PopHelper(int count, int size,
2029 const CPURegister& dst0, const CPURegister& dst1,
2030 const CPURegister& dst2, const CPURegister& dst3);
2031
2032 // Call Printf. On a native build, a simple call will be generated, but if the
2033 // simulator is being used then a suitable pseudo-instruction is used. The
2034 // arguments and stack (csp) must be prepared by the caller as for a normal
2035 // AAPCS64 call to 'printf'.
2036 //
2037 // The 'args' argument should point to an array of variable arguments in their
2038 // proper PCS registers (and in calling order). The argument registers can
2039 // have mixed types. The format string (x0) should not be included.
2040 void CallPrintf(int arg_count = 0, const CPURegister * args = NULL);
2041
2042 // Helper for implementing JumpIfNotInNewSpace and JumpIfInNewSpace.
2043 void InNewSpace(Register object,
2044 Condition cond, // eq for new space, ne otherwise.
2045 Label* branch);
2046
2047 // Try to represent a double as an int so that integer fast-paths may be
2048 // used. Not every valid integer value is guaranteed to be caught.
2049 // It supports both 32-bit and 64-bit integers depending whether 'as_int'
2050 // is a W or X register.
2051 //
2052 // This does not distinguish between +0 and -0, so if this distinction is
2053 // important it must be checked separately.
2054 //
2055 // On output the Z flag is set if the operation was successful.
2056 void TryRepresentDoubleAsInt(Register as_int,
2057 FPRegister value,
2058 FPRegister scratch_d,
2059 Label* on_successful_conversion = NULL,
2060 Label* on_failed_conversion = NULL);
2061
2062 bool generating_stub_;
2063 #if DEBUG
2064 // Tell whether any of the macro instruction can be used. When false the
2065 // MacroAssembler will assert if a method which can emit a variable number
2066 // of instructions is called.
2067 bool allow_macro_instructions_;
2068 #endif
2069 bool has_frame_;
2070
2071 // The Abort method should call a V8 runtime function, but the CallRuntime
2072 // mechanism depends on CEntryStub. If use_real_aborts is false, Abort will
2073 // use a simpler abort mechanism that doesn't depend on CEntryStub.
2074 //
2075 // The purpose of this is to allow Aborts to be compiled whilst CEntryStub is
2076 // being generated.
2077 bool use_real_aborts_;
2078
2079 // This handle will be patched with the code object on installation.
2080 Handle<Object> code_object_;
2081
2082 // The register to use as a stack pointer for stack operations.
2083 Register sp_;
2084
2085 // Scratch registers available for use by the MacroAssembler.
2086 CPURegList tmp_list_;
2087 CPURegList fptmp_list_;
2088
2089 void InitializeNewString(Register string,
2090 Register length,
2091 Heap::RootListIndex map_index,
2092 Register scratch1,
2093 Register scratch2);
2094
2095 public:
2096 // Far branches resolving.
2097 //
2098 // The various classes of branch instructions with immediate offsets have
2099 // different ranges. While the Assembler will fail to assemble a branch
2100 // exceeding its range, the MacroAssembler offers a mechanism to resolve
2101 // branches to too distant targets, either by tweaking the generated code to
2102 // use branch instructions with wider ranges or generating veneers.
2103 //
2104 // Currently branches to distant targets are resolved using unconditional
2105 // branch isntructions with a range of +-128MB. If that becomes too little
2106 // (!), the mechanism can be extended to generate special veneers for really
2107 // far targets.
2108
2109 // Helps resolve branching to labels potentially out of range.
2110 // If the label is not bound, it registers the information necessary to later
2111 // be able to emit a veneer for this branch if necessary.
2112 // If the label is bound, it returns true if the label (or the previous link
2113 // in the label chain) is out of range. In that case the caller is responsible
2114 // for generating appropriate code.
2115 // Otherwise it returns false.
2116 // This function also checks wether veneers need to be emitted.
2117 bool NeedExtraInstructionsOrRegisterBranch(Label *label,
2118 ImmBranchType branch_type);
2119 };
2120
2121
2122 // Use this scope when you need a one-to-one mapping bewteen methods and
2123 // instructions. This scope prevents the MacroAssembler from being called and
2124 // literal pools from being emitted. It also asserts the number of instructions
2125 // emitted is what you specified when creating the scope.
2126 class InstructionAccurateScope BASE_EMBEDDED {
2127 public:
2128 explicit InstructionAccurateScope(MacroAssembler* masm, size_t count = 0)
masm_(masm)2129 : masm_(masm)
2130 #ifdef DEBUG
2131 ,
2132 size_(count * kInstructionSize)
2133 #endif
2134 {
2135 // Before blocking the const pool, see if it needs to be emitted.
2136 masm_->CheckConstPool(false, true);
2137 masm_->CheckVeneerPool(false, true);
2138
2139 masm_->StartBlockPools();
2140 #ifdef DEBUG
2141 if (count != 0) {
2142 masm_->bind(&start_);
2143 }
2144 previous_allow_macro_instructions_ = masm_->allow_macro_instructions();
2145 masm_->set_allow_macro_instructions(false);
2146 #endif
2147 }
2148
~InstructionAccurateScope()2149 ~InstructionAccurateScope() {
2150 masm_->EndBlockPools();
2151 #ifdef DEBUG
2152 if (start_.is_bound()) {
2153 DCHECK(masm_->SizeOfCodeGeneratedSince(&start_) == size_);
2154 }
2155 masm_->set_allow_macro_instructions(previous_allow_macro_instructions_);
2156 #endif
2157 }
2158
2159 private:
2160 MacroAssembler* masm_;
2161 #ifdef DEBUG
2162 size_t size_;
2163 Label start_;
2164 bool previous_allow_macro_instructions_;
2165 #endif
2166 };
2167
2168
2169 // This scope utility allows scratch registers to be managed safely. The
2170 // MacroAssembler's TmpList() (and FPTmpList()) is used as a pool of scratch
2171 // registers. These registers can be allocated on demand, and will be returned
2172 // at the end of the scope.
2173 //
2174 // When the scope ends, the MacroAssembler's lists will be restored to their
2175 // original state, even if the lists were modified by some other means.
2176 class UseScratchRegisterScope {
2177 public:
UseScratchRegisterScope(MacroAssembler * masm)2178 explicit UseScratchRegisterScope(MacroAssembler* masm)
2179 : available_(masm->TmpList()),
2180 availablefp_(masm->FPTmpList()),
2181 old_available_(available_->list()),
2182 old_availablefp_(availablefp_->list()) {
2183 DCHECK(available_->type() == CPURegister::kRegister);
2184 DCHECK(availablefp_->type() == CPURegister::kFPRegister);
2185 }
2186
2187 ~UseScratchRegisterScope();
2188
2189 // Take a register from the appropriate temps list. It will be returned
2190 // automatically when the scope ends.
AcquireW()2191 Register AcquireW() { return AcquireNextAvailable(available_).W(); }
AcquireX()2192 Register AcquireX() { return AcquireNextAvailable(available_).X(); }
AcquireS()2193 FPRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); }
AcquireD()2194 FPRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); }
2195
UnsafeAcquire(const Register & reg)2196 Register UnsafeAcquire(const Register& reg) {
2197 return Register(UnsafeAcquire(available_, reg));
2198 }
2199
2200 Register AcquireSameSizeAs(const Register& reg);
2201 FPRegister AcquireSameSizeAs(const FPRegister& reg);
2202
2203 private:
2204 static CPURegister AcquireNextAvailable(CPURegList* available);
2205 static CPURegister UnsafeAcquire(CPURegList* available,
2206 const CPURegister& reg);
2207
2208 // Available scratch registers.
2209 CPURegList* available_; // kRegister
2210 CPURegList* availablefp_; // kFPRegister
2211
2212 // The state of the available lists at the start of this scope.
2213 RegList old_available_; // kRegister
2214 RegList old_availablefp_; // kFPRegister
2215 };
2216
2217
2218 inline MemOperand ContextMemOperand(Register context, int index = 0) {
2219 return MemOperand(context, Context::SlotOffset(index));
2220 }
2221
NativeContextMemOperand()2222 inline MemOperand NativeContextMemOperand() {
2223 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX);
2224 }
2225
2226
2227 // Encode and decode information about patchable inline SMI checks.
2228 class InlineSmiCheckInfo {
2229 public:
2230 explicit InlineSmiCheckInfo(Address info);
2231
HasSmiCheck()2232 bool HasSmiCheck() const {
2233 return smi_check_ != NULL;
2234 }
2235
SmiRegister()2236 const Register& SmiRegister() const {
2237 return reg_;
2238 }
2239
SmiCheck()2240 Instruction* SmiCheck() const {
2241 return smi_check_;
2242 }
2243
2244 // Use MacroAssembler::InlineData to emit information about patchable inline
2245 // SMI checks. The caller may specify 'reg' as NoReg and an unbound 'site' to
2246 // indicate that there is no inline SMI check. Note that 'reg' cannot be csp.
2247 //
2248 // The generated patch information can be read using the InlineSMICheckInfo
2249 // class.
2250 static void Emit(MacroAssembler* masm, const Register& reg,
2251 const Label* smi_check);
2252
2253 // Emit information to indicate that there is no inline SMI check.
EmitNotInlined(MacroAssembler * masm)2254 static void EmitNotInlined(MacroAssembler* masm) {
2255 Label unbound;
2256 Emit(masm, NoReg, &unbound);
2257 }
2258
2259 private:
2260 Register reg_;
2261 Instruction* smi_check_;
2262
2263 // Fields in the data encoded by InlineData.
2264
2265 // A width of 5 (Rd_width) for the SMI register preclues the use of csp,
2266 // since kSPRegInternalCode is 63. However, csp should never hold a SMI or be
2267 // used in a patchable check. The Emit() method checks this.
2268 //
2269 // Note that the total size of the fields is restricted by the underlying
2270 // storage size handled by the BitField class, which is a uint32_t.
2271 class RegisterBits : public BitField<unsigned, 0, 5> {};
2272 class DeltaBits : public BitField<uint32_t, 5, 32-5> {};
2273 };
2274
2275 } // namespace internal
2276 } // namespace v8
2277
2278 #define ACCESS_MASM(masm) masm->
2279
2280 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_H_
2281