| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 40 __m128i Reg1; local
94 __m128i Reg1; local
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) { in addRegReg()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
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| D | MipsSEFrameLowering.cpp | 440 unsigned Reg1 = in emitPrologue() local
457 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
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| D | Mips16InstrInfo.cpp | 263 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 875 unsigned Reg1; member
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
1037 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, in addRegReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 515 unsigned Reg1 = Reg; in lowerCRSpilling() local
560 unsigned Reg1 = Reg; in lowerCRRestore() local
604 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
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| D | PPCVSXSwapRemoval.cpp | 866 unsigned Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 144 unsigned Reg1, bool isKill1, in addRegReg()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
614 uint16_t Reg1; variable
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 85 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1603 StringRef Reg1(R1); in processInstruction() local
1618 StringRef Reg1(R1); in processInstruction() local
1634 StringRef Reg1(R1); in processInstruction() local
1974 StringRef Reg1(R1); in processInstruction() local
2128 StringRef Reg1(R1); in processInstruction() local
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 118 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1477 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1490 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1545 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1592 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 78 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
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| D | StrongPHIElimination.cpp | 441 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { in unionRegs()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 461 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence()
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| D | Thumb2SizeReduction.cpp | 707 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 86 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 588 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups()
|