| /external/llvm/lib/Target/Lanai/InstPrinter/ |
| D | LanaiInstPrinter.cpp | 211 const MCOperand &RegOp) { in printMemoryBaseRegister()
237 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand() local
252 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRrOperand() local
273 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemSplsOperand() local
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| /external/llvm/lib/Target/BPF/InstPrinter/ |
| D | BPFInstPrinter.cpp | 68 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemOperand() local
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAsmPrinter.cpp | 132 unsigned RegOp = OpNo + 1; in PrintAsmOperand() local
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 201 struct RegOp { struct in __anoncba7d3b40111::SparcOperand
202 unsigned RegNum;
203 RegisterKind Kind;
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 145 struct RegOp { struct in __anon2fa8e53e0111::AMDGPUOperand
146 unsigned RegNo;
147 Modifiers Mods;
148 const MCRegisterInfo *TRI;
149 const MCSubtargetInfo *STI;
150 bool IsForcedVOP3;
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 263 unsigned RegOp = OpTbl2Addr[i][0]; in X86InstrInfo() local
373 unsigned RegOp = OpTbl0[i][0]; in X86InstrInfo() local
533 unsigned RegOp = OpTbl1[i][0]; in X86InstrInfo() local
894 unsigned RegOp = OpTbl2[i][0]; in X86InstrInfo() local
907 unsigned RegOp, unsigned MemOp, unsigned Flags) { in AddTableEntry()
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| D | X86MCInstLower.cpp | 260 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 86 struct RegOp { struct in __anon920606c00111::SystemZOperand
87 RegisterKind Kind;
88 unsigned Num;
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 44 struct RegOp { struct
45 unsigned RegNo;
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 105 struct RegOp { struct
106 unsigned RegNum;
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 395 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState()
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 511 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIEImpl() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 498 unsigned RegOp = OpNum; in PrintAsmOperand() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 177 struct RegOp { struct in __anon26fd99540211::AArch64Operand
178 unsigned RegNum;
179 bool isVector;
4000 AArch64Operand &RegOp = static_cast<AArch64Operand &>(*Operands[1]); in MatchAndEmitInstruction() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 361 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 310 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm() local
|
| D | X86InstrInfo.cpp | 107 uint16_t RegOp; member
2049 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) { in AddTableEntry()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 486 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1; in PrintAsmOperand() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
| D | DwarfCompileUnit.cpp | 1246 const MachineOperand RegOp = DVInsn->getOperand(0); in constructVariableDIE() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LiveIntervalAnalysis.cpp | 943 unsigned RegOp = 0; in getReMatImplicitUse() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1249 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode())) in getNodeRegMask() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 488 struct RegOp { struct in __anonef5d38c20311::ARMOperand
489 unsigned RegNum;
4763 unsigned RegOp = 4; in cvtThumbMultiply() local
|