1 /** @file 2 QuarkNcSocId Register Definitions 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 Definitions beginning with "R_" are registers 15 Definitions beginning with "B_" are bits within registers 16 Definitions beginning with "V_" are meaningful values of bits within the registers 17 Definitions beginning with "S_" are register sizes 18 Definitions beginning with "N_" are the bit position 19 20 **/ 21 22 #ifndef _QUARK_NC_SOC_ID_H_ 23 #define _QUARK_NC_SOC_ID_H_ 24 25 // 26 // QNC GMCH Equates 27 // 28 29 // 30 // DEVICE 0 (Memroy Controller Hub) 31 // 32 #define MC_BUS PCI_BUS_NUMBER_QNC 33 #define MC_DEV 0x00 34 #define MC_FUN 0x00 35 36 #define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID 37 #define QUARK_MC_DEVICE_ID 0x0958 38 #define QUARK2_MC_DEVICE_ID 0x12C0 39 #define QNC_MC_REV_ID_A0 0x00 40 41 42 // 43 // MCR - B0:D0:F0:RD0h (WO)- Message control register 44 // [31:24] Message opcode - D0 read; E0 write; 45 // [23:16] Message port 46 // [15:8 ] Message target register address 47 // [ 7:4 ] Message write byte enable : F is enable 48 // [ 3:0 ] Reserved 49 // 50 #define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register 51 // Always Set to 0xF0 52 53 // 54 //MDR - B0:D0:F0:RD4h (RW)- Message data register 55 // 56 #define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register 57 58 // 59 //MEA - B0:D0:F0:RD8h (RW)- Message extended address register 60 // 61 #define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register 62 63 #define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR 64 #define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR 65 #define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR 66 67 // 68 // Misc Useful Macros 69 // 70 71 #define LShift16(value) (value << 16) 72 73 // 74 // QNC Message OpCodes and Attributes 75 // 76 #define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode 77 #define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode 78 79 // 80 // Alternative opcodes for the SCSS block 81 // 82 #define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode 83 #define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode 84 85 // 86 // QNC Message OpCodes and Attributes for IO 87 // 88 #define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode 89 #define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode 90 91 92 #define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode 93 94 #define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode 95 #define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode 96 97 // 98 // QNC Message Ports and Registers 99 // 100 // Start of SB Port IDs 101 #define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00 102 #define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01 103 #define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03 104 #define QUARK_NC_RMU_SB_PORT_ID 0x04 105 #define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05 106 #define QUARK_SC_USB_AFE_SB_PORT_ID 0x14 107 #define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16 108 #define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31 109 #define QUARK_SCSS_FUSE_SB_PORT_ID 0x33 110 #define QUARK_ICLK_SB_PORT_ID 0x32 111 #define QUARK_SCSS_CRU_SB_PORT_ID 0x34 112 113 // 114 // Quark Memory Arbiter Registers. 115 // 116 #define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register. 117 #define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient 118 #define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh. 119 #define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing. 120 #define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing. 121 #define ASTATUS1_RASISED_BP (10) 122 #define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 123 #define ASTATUS0_RASISED_BP (8) 124 #define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 125 #define ASTATUS1_DEFAULT_BP (2) 126 #define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 127 #define ASTATUS0_DEFAULT_BP (0) 128 #define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 129 130 // 131 // Quark Memory Controller Registers. 132 // 133 #define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register. 134 #define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC. 135 136 // 137 // Quark Remote Management Unit Registers. 138 // 139 #define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address 140 141 #define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register. 142 #define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6) 143 #define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5) 144 145 #define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1. 146 #define OPTIONS_1_DMA_DISABLE (BIT0) 147 148 #define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register. 149 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18) 150 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18 151 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 152 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 153 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 154 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 155 156 #define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register. 157 #define TS_ENABLE (BIT15) 158 #define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register. 159 #define TS_HOT_TRIP_CLEAR_THOLD_BP 24 160 #define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP) 161 #define TS_CAT_TRIP_CLEAR_THOLD_BP 16 162 #define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP) 163 #define TS_HOT_TRIP_SET_THOLD_BP 8 164 #define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP) 165 #define TS_CAT_TRIP_SET_THOLD_BP 0 166 #define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP) 167 168 #define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50 169 #define SCRUB_CFG_INTERVAL_SHIFT 0x00 170 #define SCRUB_CFG_INTERVAL_MASK 0xFF 171 #define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08 172 #define SCRUB_CFG_BLOCKSIZE_MASK 0x1F 173 #define SCRUB_CFG_ACTIVE (BIT13) 174 #define SCRUB_CFG_INVALID 0x00000FFF 175 176 #define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76 177 #define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77 178 #define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C 179 180 #define SCRUB_RESUME_MSG() ((UINT32)( \ 181 (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \ 182 (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ 183 0xF0)) 184 185 #define SCRUB_PAUSE_MSG() ((UINT32)( \ 186 (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \ 187 (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ 188 0xF0)) 189 190 // 191 // Quark Memory Manager Registers 192 // 193 #define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82 194 #define BLOCK_ENABLE_PG (1 << 28) 195 #define BLOCK_DISABLE_PG (1 << 29) 196 #define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19 197 #define EnableIMRInt BIT31 198 #define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C 199 #define EnableSMMInt BIT31 200 #define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20 201 #define DRAM_NON_HOST_RQ_LIMIT_BP 0 202 #define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP) 203 204 #define QUARK_NC_TOTAL_IMR_SET 0x8 205 #define QUARK_NC_MEMORY_MANAGER_IMR0 0x40 206 #define QUARK_NC_MEMORY_MANAGER_IMR1 0x44 207 #define QUARK_NC_MEMORY_MANAGER_IMR2 0x48 208 #define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C 209 #define QUARK_NC_MEMORY_MANAGER_IMR4 0x50 210 #define QUARK_NC_MEMORY_MANAGER_IMR5 0x54 211 #define QUARK_NC_MEMORY_MANAGER_IMR6 0x58 212 #define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C 213 #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00 214 #define IMR_LOCK BIT31 215 #define IMR_EN BIT30 216 #define IMRL_MASK 0x00FFFFFC 217 #define IMRL_RESET 0x00000000 218 #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01 219 #define IMRH_MASK 0x00FFFFFC 220 #define IMRH_RESET 0x00000000 221 #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02 222 #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03 223 #define IMRX_ALL_ACCESS 0xFFFFFFFF 224 #define CPU_SNOOP BIT30 225 #define RMU BIT29 226 #define CPU0_NON_SMM BIT0 227 228 // 229 // Quark Host Bridge Registers 230 // 231 #define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls 232 #define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) 233 #define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control 234 #define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN 235 #define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN 236 #define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN 237 #define SMM_CTL_EN (BIT3) // SMM enable 238 #define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN 239 #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN 240 #define SMM_LOCKED (BIT0) // SMM Locked 241 #define SMM_START_MASK 0x0000FFF0 242 #define SMM_END_MASK 0xFFF00000 243 #define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08 244 #define HMBOUND_MASK 0x0FFFFF000 245 #define HMBOUND_LOCK BIT0 246 #define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A 247 #define HLEGACY_SMI_PIN_VALUE BIT12 248 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40 249 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41 250 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42 251 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44 252 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46 253 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48 254 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A 255 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C 256 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E 257 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50 258 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52 259 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54 260 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56 261 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58 262 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59 263 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A 264 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B 265 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C 266 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D 267 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E 268 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F 269 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60 270 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61 271 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62 272 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63 273 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64 274 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65 275 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66 276 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67 277 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68 278 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69 279 280 // 281 // System On Chip Unit (SOCUnit) Registers. 282 // 283 #define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00 284 #define B_STPDDRCFG_FORCE_RECOVERY BIT0 285 #define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25 286 #define B_ROM_FUSE_IN_SECURE_SKU BIT6 287 288 #define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31 289 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3) 290 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3 291 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) 292 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8 293 #define B_TSCGF1_CONFIG_IBGEN BIT17 294 #define B_TSCGF1_CONFIG_IBGEN_BP 17 295 #define B_TSCGF1_CONFIG_IBGCHOPEN BIT18 296 #define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18 297 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 298 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14 299 300 #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32 301 #define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF 302 #define B_TSCGF2_CONFIG_IDSCONTROL_BP 0 303 #define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000 304 #define B_TSCGF2_CONFIG_IDSTIMING_BP 16 305 306 #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33 307 #define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000 308 #define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24 309 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8) 310 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8 311 #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF 312 #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0 313 314 #define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34 315 #define B_TSCGF3_CONFIG_ITSRST BIT0 316 #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11 317 #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP) 318 319 #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 320 #define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20 321 #define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19 322 #define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18 323 #define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17 324 #define SOCCLKEN_CONFIG_BB_RST_B BIT16 325 326 #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 327 328 #define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51 329 #define B_CFG_STICKY_RW_SMM_VIOLATION BIT0 330 #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1 331 #define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 332 #define B_CFG_STICKY_RW_DECC_VIOLATION BIT3 333 #define B_CFG_STICKY_RW_WARM_RST BIT4 334 #define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9 335 #define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION) 336 #define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST) 337 338 // 339 // iCLK Registers. 340 // 341 #define QUARK_ICLK_MUXTOP 0x0140 342 #define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23) 343 #define B_MUXTOP_FLEX2_BP 23 344 #define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20) 345 #define B_MUXTOP_FLEX1_BP 20 346 347 #define QUARK_ICLK_SSC1 0x0314 348 #define QUARK_ICLK_SSC2 0x0414 349 #define QUARK_ICLK_SSC3 0x0514 350 #define QUARK_ICLK_REF2_DBUFF0 0x2000 351 352 // 353 // PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID). 354 // 355 #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080 356 #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180 357 #define OCFGPIMIXLOAD_1_0 BIT6 358 #define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F 359 360 // 361 // QNC ICH Equates 362 // 363 #define V_INTEL_VENDOR_ID 0x8086 364 365 #define PCI_BUS_NUMBER_QNC 0x00 366 367 // 368 // PCI to LPC Bridge Registers (D31:F0) 369 // 370 #define PCI_DEVICE_NUMBER_QNC_LPC 31 371 #define PCI_FUNCTION_NUMBER_QNC_LPC 0 372 373 #define R_QNC_LPC_VENDOR_ID 0x00 374 #define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID 375 #define R_QNC_LPC_DEVICE_ID 0x02 376 #define QUARK_V_LPC_DEVICE_ID_0 0x095E 377 #define R_QNC_LPC_REV_ID 0x08 378 379 #define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43 380 #define B_QNC_LPC_SMBUS_BASE_EN (BIT31) 381 #define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6] 382 // 383 // SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h) 384 // Suggested Value for SMBA = 0x1040 385 // 386 #define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W 387 #define B_QNC_SMBUS_START (BIT4) // Start/Stop 388 #define V_QNC_SMBUS_HCTL_CMD_QUICK 0 389 #define V_QNC_SMBUS_HCTL_CMD_BYTE 1 390 #define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2 391 #define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3 392 #define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4 393 #define V_QNC_SMBUS_HCTL_CMD_BLOCK 5 394 395 #define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W 396 #define B_QNC_SMBUS_BERR (BIT2) // BUS Error 397 #define B_QNC_SMBUS_DERR (BIT1) // Device Error 398 #define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status 399 #define B_QNC_SMBUS_HSTS_ALL 0x07 400 401 #define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W 402 #define V_QNC_SMBUS_HCLK_100KHZ 0x0054 403 404 #define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W 405 #define V_QNC_SMBUS_RW_SEL_READ 1 406 #define V_QNC_SMBUS_RW_SEL_WRITE 0 407 408 #define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W 409 #define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W 410 #define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W 411 #define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh 412 413 #define R_QNC_LPC_GBA_BASE 0x44 414 #define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0 415 // 416 // GPIO register offsets from GBA - "GPIO" (D31:F0:R44h) 417 // Suggested Value for GBA = 0x1080 418 // 419 #define R_QNC_GPIO_CGEN_CORE_WELL 0x00 420 #define R_QNC_GPIO_CGIO_CORE_WELL 0x04 421 #define R_QNC_GPIO_CGLVL_CORE_WELL 0x08 422 #define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable 423 #define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable 424 #define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable 425 #define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable 426 #define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status 427 #define R_QNC_GPIO_RGEN_RESUME_WELL 0x20 428 #define R_QNC_GPIO_RGIO_RESUME_WELL 0x24 429 #define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28 430 #define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable 431 #define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable 432 #define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable 433 #define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable 434 #define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status 435 #define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable 436 #define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable 437 438 #define R_QNC_LPC_PM1BLK 0x48 439 #define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0 440 // 441 // ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h) 442 // Suggested Value for PM1BLK = 0x1000 443 // 444 #define R_QNC_PM1BLK_PM1S 0x00 445 #define S_QNC_PM1BLK_PM1S 2 446 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) 447 #define B_QNC_PM1BLK_PM1S_WAKE (BIT15) 448 #define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) 449 #define B_QNC_PM1BLK_PM1S_RTC (BIT10) 450 #define B_QNC_PM1BLK_PM1S_GLOB (BIT5) 451 #define B_QNC_PM1BLK_PM1S_TO (BIT0) 452 #define N_QNC_PM1BLK_PM1S_RTC 10 453 454 455 #define R_QNC_PM1BLK_PM1E 0x02 456 #define S_QNC_PM1BLK_PM1E 2 457 #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) 458 #define B_QNC_PM1BLK_PM1E_RTC (BIT10) 459 #define B_QNC_PM1BLK_PM1E_GLOB (BIT5) 460 #define N_QNC_PM1BLK_PM1E_RTC 10 461 462 #define R_QNC_PM1BLK_PM1C 0x04 463 #define B_QNC_PM1BLK_PM1C_SLPEN (BIT13) 464 #define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10) 465 #define V_S0 0x00000000 466 #define V_S3 0x00001400 467 #define V_S4 0x00001800 468 #define V_S5 0x00001C00 469 #define B_QNC_PM1BLK_PM1C_SCIEN (BIT0) 470 471 #define R_QNC_PM1BLK_PM1T 0x08 472 473 #define R_QNC_LPC_GPE0BLK 0x4C 474 #define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0 475 // Suggested Value for GPE0BLK = 0x10C0 476 // 477 #define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status 478 #define S_QNC_GPE0BLK_GPE0S 4 479 #define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg 480 #define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE 481 #define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO 482 #define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE 483 #define N_QNC_GPE0BLK_GPE0S_THRM 12 484 485 #define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable 486 #define S_QNC_GPE0BLK_GPE0E 4 487 #define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE 488 #define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO 489 #define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE 490 #define N_QNC_GPE0BLK_GPE0E_THRM 12 491 492 #define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable 493 #define S_QNC_GPE0BLK_SMIE 4 494 #define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F 495 #define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM 496 #define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep 497 #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer 498 #define N_QNC_GPE0BLK_SMIE_GPIO 9 499 #define N_QNC_GPE0BLK_SMIE_ESMI 8 500 #define N_QNC_GPE0BLK_SMIE_APM 4 501 #define N_QNC_GPE0BLK_SMIE_SPI 3 502 #define N_QNC_GPE0BLK_SMIE_SLP 2 503 #define N_QNC_GPE0BLK_SMIE_SWT 1 504 505 #define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register. 506 #define S_QNC_GPE0BLK_SMIS 4 507 #define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F 508 #define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI 509 #define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM 510 #define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI 511 #define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep 512 #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer 513 #define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS 514 #define N_QNC_GPE0BLK_SMIS_GPIO 9 515 #define N_QNC_GPE0BLK_SMIS_APM 4 516 #define N_QNC_GPE0BLK_SMIS_SPI 3 517 #define N_QNC_GPE0BLK_SMIS_SLP 2 518 #define N_QNC_GPE0BLK_SMIS_SWT 1 519 520 #define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well 521 #define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable 522 523 #define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well 524 #define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad 525 526 #define R_QNC_LPC_ACTL 0x58 527 #define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00 528 529 // 530 // Number of PIRQs supported. PIRQA~PIRQH 531 // 532 #define QNC_NUMBER_PIRQS 8 533 #define R_QNC_LPC_PIRQA_ROUT 0x60 534 #define R_QNC_LPC_PIRQB_ROUT 0x61 535 #define R_QNC_LPC_PIRQC_ROUT 0x62 536 #define R_QNC_LPC_PIRQD_ROUT 0x63 537 #define R_QNC_LPC_PIRQE_ROUT 0x64 538 #define R_QNC_LPC_PIRQF_ROUT 0x65 539 #define R_QNC_LPC_PIRQG_ROUT 0x66 540 #define R_QNC_LPC_PIRQH_ROUT 0x67 541 542 // 543 // Bit values are the same for R_TNC_LPC_PIRQA_ROUT to 544 // R_TNC_LPC_PIRQH_ROUT 545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) 546 547 #define R_QNC_LPC_WDTBA 0x84 548 // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN 549 #define R_QNC_LPC_WDT_WDTCR 0x10 550 #define R_QNC_LPC_WDT_WDTLR 0x18 551 // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END 552 553 #define R_QNC_LPC_FWH_BIOS_DEC 0xD4 554 #define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31) 555 #define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30) 556 #define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29) 557 #define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28) 558 #define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27) 559 #define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26) 560 #define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25) 561 #define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24) 562 563 #define R_QNC_LPC_BIOS_CNTL 0xD8 564 #define S_QNC_LPC_BIOS_CNTL 4 565 #define B_QNC_LPC_BIOS_CNTL_PFE (BIT8) 566 #define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5) 567 #define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) 568 #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1) 569 #define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0) 570 #define N_QNC_LPC_BIOS_CNTL_BLE 1 571 #define N_QNC_LPC_BIOS_CNTL_BIOSWE 0 572 573 #define R_QNC_LPC_RCBA 0xF0 574 #define B_QNC_LPC_RCBA_MASK 0xFFFFC000 575 #define B_QNC_LPC_RCBA_EN (BIT0) 576 577 //--------------------------------------------------------------------------- 578 // Fixed IO Decode on QuarkNcSocId 579 // 580 // 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master 581 // 40h(3B): R/W 8254 582 // 43h(1B): W 8254 583 // 50h(3B): R/W 8254 584 // 53h(1B): W 8254 585 // 61h(1B): R/W NMI Controller 586 // 63h(1B): R/W NMI Controller - can be disabled 587 // 65h(1B): R/W NMI Controller - can be disabled 588 // 67h(1B): R/W NMI Controller - can be disabled 589 // 70h(1B): W NMI & RTC 590 // 71h(1B): R/W RTC 591 // 72h(1B): R RTC; W NMI&RTC 592 // 73h(1B): R/W RTC 593 // 74h(1B): R RTC; W NMI&RTC 594 // 75h(1B): R/W RTC 595 // 76h(1B): R RTC; W NMI&RTC 596 // 77h(1B): R/W RTC 597 // 84h(3B): R/W Internal/LPC 598 // 88h(1B): R/W Internal/LPC 599 // 8Ch(3B): R/W Internal/LPC 600 // A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave 601 // B2h(1B) B3h(1B): R/W Power management 602 // 3B0h-3BBh: R/W VGA 603 // 3C0h-3DFh: R/W VGA 604 // CF8h(4B): R/W Internal 605 // CF9h(1B): R/W LPC 606 // CFCh(4B): R/W Internal 607 //--------------------------------------------------------------------------- 608 609 #define R_APM_CNT 0xB2 610 611 // 612 // Reset Generator I/O Port 613 // 614 #define RST_CNT 0xCF9 615 #define B_RST_CNT_COLD_RST (BIT3) // Cold reset 616 #define B_RST_CNT_WARM_RST (BIT1) // Warm reset 617 618 // 619 // Processor interface registers (NMI) 620 // 621 622 #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20 623 #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21 624 #define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0 625 626 // 627 // Pci Express Root Ports (D23:F0/F1) 628 // 629 #define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23 630 #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0 631 #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1 632 633 #define MAX_PCI_EXPRESS_ROOT_PORTS 2 634 635 #define R_QNC_PCIE_BNUM 0x18 636 #define R_QNC_PCIE_CAP_PTR 0x34 637 638 #define PCIE_CAPID 0x10 //PCIE Capability ID 639 #define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID 640 #define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset 641 #define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset 642 #define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset 643 #define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset 644 #define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset 645 646 #define R_QNC_PCIE_XCAP 0x42 //~ 43h 647 #define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented 648 #define R_QNC_PCIE_DCAP 0x44 //~ 47h 649 #define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency 650 #define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency 651 #define R_QNC_PCIE_DCTL 0x48 //~ 49h 652 #define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable 653 #define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable 654 #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable 655 #define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable 656 #define R_QNC_PCIE_LCAP 0x4C //~ 4Fh 657 #define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported 658 #define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask 659 #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask 660 #define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask 661 #define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask 662 #define R_QNC_PCIE_LCTL 0x50 //~ 51h 663 #define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration 664 #define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link 665 #define R_QNC_PCIE_LSTS 0x52 //~ 53h 666 #define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration 667 #define B_QNC_PCIE_LSTS_LT (BIT11) //Link training 668 #define R_QNC_PCIE_SLCAP 0x54 //~ 57h 669 #define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F 670 #define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7] 671 #define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7] 672 #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19] 673 #define R_QNC_PCIE_SLCTL 0x58 //~ 59h 674 #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable 675 #define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable 676 #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable 677 #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh 678 #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected 679 #define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed 680 #define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed 681 #define R_QNC_PCIE_RCTL 0x5C //~ 5Dh 682 #define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable 683 #define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable 684 #define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable 685 #define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable 686 #define R_QNC_PCIE_SVID 0x94 //~ 97h 687 #define R_QNC_PCIE_CCFG 0xD0 //~ D3h 688 #define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable 689 #define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size 690 #define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size 691 #define R_QNC_PCIE_MPC2 0xD4 //~ D7h 692 #define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode 693 #define R_QNC_PCIE_MPC 0xD8 //~ DBh 694 #define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable 695 #define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable 696 697 #define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable 698 #define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable 699 #define R_QNC_PCIE_IOSFSBCTL 0xF6 700 #define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter. 701 #define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE. 702 703 #define V_PCIE_MAX_TRY_TIMES 200 704 705 // 706 // Misc PCI register offsets and sizes 707 // 708 #define R_EFI_PCI_SVID 0x2C 709 710 // 711 // IO_APIC 712 // 713 #define IOAPIC_BASE 0xFEC00000 714 #define IOAPIC_SIZE 0x1000 715 716 // 717 // Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h) 718 // Suggested Value for RCBA = 0xFED1C000 719 // 720 721 #define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB 722 #define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status 723 #define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown 724 #define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status 725 #define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status 726 #define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress 727 728 #define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control 729 #define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable 730 #define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64) 731 #define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer 732 #define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer 733 #define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence 734 #define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go 735 736 #define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address 737 #define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask 738 #define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0 739 #define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration 740 #define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration 741 #define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 742 #define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) 743 #define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) 744 #define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) 745 #define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU 746 747 #define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0. 748 #define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1. 749 #define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2. 750 #define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers. 751 752 #define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route 753 #define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route 754 #define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route 755 #define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route 756 757 #endif 758