1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TZC400_H__ 32 #define __TZC400_H__ 33 34 #include <stdint.h> 35 36 #define BUILD_CONFIG_OFF 0x000 37 #define ACTION_OFF 0x004 38 #define GATE_KEEPER_OFF 0x008 39 #define SPECULATION_CTRL_OFF 0x00c 40 #define INT_STATUS 0x010 41 #define INT_CLEAR 0x014 42 43 #define FAIL_ADDRESS_LOW_OFF 0x020 44 #define FAIL_ADDRESS_HIGH_OFF 0x024 45 #define FAIL_CONTROL_OFF 0x028 46 #define FAIL_ID 0x02c 47 48 #define REGION_BASE_LOW_OFF 0x100 49 #define REGION_BASE_HIGH_OFF 0x104 50 #define REGION_TOP_LOW_OFF 0x108 51 #define REGION_TOP_HIGH_OFF 0x10c 52 #define REGION_ATTRIBUTES_OFF 0x110 53 #define REGION_ID_ACCESS_OFF 0x114 54 #define REGION_NUM_OFF(region) (0x20 * region) 55 56 /* ID Registers */ 57 #define PID0_OFF 0xfe0 58 #define PID1_OFF 0xfe4 59 #define PID2_OFF 0xfe8 60 #define PID3_OFF 0xfec 61 #define PID4_OFF 0xfd0 62 #define PID5_OFF 0xfd4 63 #define PID6_OFF 0xfd8 64 #define PID7_OFF 0xfdc 65 #define CID0_OFF 0xff0 66 #define CID1_OFF 0xff4 67 #define CID2_OFF 0xff8 68 #define CID3_OFF 0xffc 69 70 #define BUILD_CONFIG_NF_SHIFT 24 71 #define BUILD_CONFIG_NF_MASK 0x3 72 #define BUILD_CONFIG_AW_SHIFT 8 73 #define BUILD_CONFIG_AW_MASK 0x3f 74 #define BUILD_CONFIG_NR_SHIFT 0 75 #define BUILD_CONFIG_NR_MASK 0x1f 76 77 /* Not describing the case where regions 1 to 8 overlap */ 78 #define ACTION_RV_SHIFT 0 79 #define ACTION_RV_MASK 0x3 80 #define ACTION_RV_LOWOK 0x0 81 #define ACTION_RV_LOWERR 0x1 82 #define ACTION_RV_HIGHOK 0x2 83 #define ACTION_RV_HIGHERR 0x3 84 85 /* 86 * Number of gate keepers is implementation defined. But we know the max for 87 * this device is 4. Get implementation details from BUILD_CONFIG. 88 */ 89 #define GATE_KEEPER_OS_SHIFT 16 90 #define GATE_KEEPER_OS_MASK 0xf 91 #define GATE_KEEPER_OR_SHIFT 0 92 #define GATE_KEEPER_OR_MASK 0xf 93 #define GATE_KEEPER_FILTER_MASK 0x1 94 95 /* Speculation is enabled by default. */ 96 #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) 97 #define SPECULATION_CTRL_READ_DISABLE (1 << 0) 98 99 /* Max number of filters allowed is 4. */ 100 #define INT_STATUS_OVERLAP_SHIFT 16 101 #define INT_STATUS_OVERLAP_MASK 0xf 102 #define INT_STATUS_OVERRUN_SHIFT 8 103 #define INT_STATUS_OVERRUN_MASK 0xf 104 #define INT_STATUS_STATUS_SHIFT 0 105 #define INT_STATUS_STATUS_MASK 0xf 106 107 #define INT_CLEAR_CLEAR_SHIFT 0 108 #define INT_CLEAR_CLEAR_MASK 0xf 109 110 #define FAIL_CONTROL_DIR_SHIFT (1 << 24) 111 #define FAIL_CONTROL_DIR_READ 0x0 112 #define FAIL_CONTROL_DIR_WRITE 0x1 113 #define FAIL_CONTROL_NS_SHIFT (1 << 21) 114 #define FAIL_CONTROL_NS_SECURE 0x0 115 #define FAIL_CONTROL_NS_NONSECURE 0x1 116 #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) 117 #define FAIL_CONTROL_PRIV_PRIV 0x0 118 #define FAIL_CONTROL_PRIV_UNPRIV 0x1 119 120 /* 121 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 122 * Platform should provide the value on initialisation. 123 */ 124 #define FAIL_ID_VNET_SHIFT 24 125 #define FAIL_ID_VNET_MASK 0xf 126 #define FAIL_ID_ID_SHIFT 0 127 128 /* Used along with 'tzc_region_attributes_t' below */ 129 #define REG_ATTR_SEC_SHIFT 30 130 #define REG_ATTR_F_EN_SHIFT 0 131 #define REG_ATTR_F_EN_MASK 0xf 132 #define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) 133 #define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ 134 REG_ATTR_F_EN_SHIFT) 135 136 #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 137 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 138 #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf 139 140 141 /* Macros for setting Region ID access permissions based on NSAID */ 142 #define TZC_REGION_ACCESS_RD(id) \ 143 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 144 REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 145 #define TZC_REGION_ACCESS_WR(id) \ 146 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 147 REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 148 #define TZC_REGION_ACCESS_RDWR(id) \ 149 (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) 150 151 /* Filters are bit mapped 0 to 3. */ 152 #define TZC400_COMPONENT_ID 0xb105f00d 153 154 /******************************************************************************* 155 * Function & variable prototypes 156 ******************************************************************************/ 157 158 /* 159 * What type of action is expected when an access violation occurs. 160 * The memory requested is zeroed. But we can also raise and event to 161 * let the system know it happened. 162 * We can raise an interrupt(INT) and/or cause an exception(ERR). 163 * TZC_ACTION_NONE - No interrupt, no Exception 164 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 165 * data abort 166 * TZC_ACTION_INT - Raise interrupt, no exception 167 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 168 * external data abort 169 */ 170 typedef enum { 171 TZC_ACTION_NONE = 0, 172 TZC_ACTION_ERR = 1, 173 TZC_ACTION_INT = 2, 174 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 175 } tzc_action_t; 176 177 /* 178 * Controls secure access to a region. If not enabled secure access is not 179 * allowed to region. 180 */ 181 typedef enum { 182 TZC_REGION_S_NONE = 0, 183 TZC_REGION_S_RD = 1, 184 TZC_REGION_S_WR = 2, 185 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 186 } tzc_region_attributes_t; 187 188 189 void tzc_init(uint64_t base); 190 void tzc_configure_region(uint32_t filters, 191 uint8_t region, 192 uint64_t region_base, 193 uint64_t region_top, 194 tzc_region_attributes_t sec_attr, 195 uint32_t ns_device_access); 196 void tzc_enable_filters(void); 197 void tzc_disable_filters(void); 198 void tzc_set_action(tzc_action_t action); 199 200 201 #endif /* __TZC400__ */ 202