1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Shengquan Yuan <shengquan.yuan@intel.com> 26 * Binglin Chen <binglin.chen@intel.com> 27 * Jason Hu <jason.hu@intel.com> 28 * Zeng Li <zeng.li@intel.com> 29 */ 30 31 #ifndef _PSB_OVERLAY_H_ 32 #define _PSB_OVERLAY_H_ 33 34 #include <va/va.h> 35 #define USE_OVERLAY 1 36 #define USE_DISPLAY_C_SPRITE 0 37 38 /* 39 * NOTE: Destination keying when enabled forces the overlay surface 40 * Z order to be below the primary display. Pixels that match the key 41 * value become transparent and the overlay becomes visible at that 42 * pixel. 43 */ 44 #define USE_DCLRK 1 45 /* 46 * NOTE: This is only for media player output 47 */ 48 #define USE_CLIP_FUNC 0 49 #define USE_SCALE_FUNC 1 50 #define USE_ROTATION_FUNC 0 51 52 #define Success 0 53 54 /* FIXME this will be removed later after using pvr2d */ 55 #if 1 56 #define RR_Rotate_0 1 57 #define RR_Rotate_90 2 58 #define RR_Rotate_180 4 59 #define RR_Rotate_270 8 60 #endif 61 62 #define OV_HUE_DEFAULT_VALUE 0 63 #define OV_HUE_MIN -30 64 #define OV_HUE_MAX 30 65 66 #define OV_BRIGHTNESS_DEFAULT_VALUE 0 67 #define OV_BRIGHTNESS_MIN -50 68 #define OV_BRIGHTNESS_MAX 50 69 70 #define OV_CONTRAST_DEFAULT_VALUE 0 71 #define OV_CONTRAST_MIN -100 72 #define OV_CONTRAST_MAX 100 73 74 #define OV_SATURATION_DEFAULT_VALUE 100 75 #define OV_SATURATION_MIN 0 76 #define OV_SATURATION_MAX 200 77 78 #define CLAMP_ATTR(a,max,min) (a>max?max:(a<min?min:a)) 79 80 /*DSPCNTR - Display Control Register*/ 81 #define DISPLAY_PLANE_ENABLE (1<<31) 82 #define DISPLAY_PLANE_DISABLE 0 83 #define DISPPLANE_GAMMA_ENABLE (1<<30) 84 #define DISPPLANE_GAMMA_DISABLE 0 85 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 86 #define DISPPLANE_8BPP (0x2<<26) 87 #define DISPPLANE_15_16BPP (0x4<<26) 88 #define DISPPLANE_16BPP (0x5<<26) 89 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 90 #define DISPPLANE_32BPP (0x7<<26) 91 #define DISPPLANE_BOTTOM (4) 92 93 /* 94 * OCMD - Overlay Command Register 95 */ 96 #define OCMD_REGISTER 0x30168 97 #define MIRROR_MODE (0x3<<17) 98 #define MIRROR_HORIZONTAL (0x1<<17) 99 #define MIRROR_VERTICAL (0x2<<17) 100 #define MIRROR_BOTH (0x3<<17) 101 #define OV_BYTE_ORDER (0x3<<14) 102 #define UV_SWAP (0x1<<14) 103 #define Y_SWAP (0x2<<14) 104 #define Y_AND_UV_SWAP (0x3<<14) 105 #define SOURCE_FORMAT (0xf<<10) 106 #define RGB_888 (0x1<<10) 107 #define RGB_555 (0x2<<10) 108 #define RGB_565 (0x3<<10) 109 #define NV12 (0xb<<10) 110 #define YUV_422 (0x8<<10) 111 #define YUV_411 (0x9<<10) 112 #define YUV_420 (0xc<<10) 113 #define YUV_422_PLANAR (0xd<<10) 114 #define YUV_410 (0xe<<10) 115 #define TVSYNC_FLIP_PARITY (0x1<<9) 116 #define TVSYNC_FLIP_ENABLE (0x1<<7) 117 #define BUF_TYPE (0x1<<5) 118 #define BUF_TYPE_FRAME (0x0<<5) 119 #define BUF_TYPE_FIELD (0x1<<5) 120 #define TEST_MODE (0x1<<4) 121 #define BUFFER_SELECT (0x3<<2) 122 #define BUFFER0 (0x0<<2) 123 #define BUFFER1 (0x1<<2) 124 #define FIELD_SELECT (0x1<<1) 125 #define FIELD0 (0x0<<1) 126 #define FIELD1 (0x1<<1) 127 #define OVERLAY_ENABLE 0x1 128 129 #define OFC_UPDATE 0x1 130 131 /* 132 * OVADD - Overlay Register Update Address Register 133 */ 134 #define OVADD_PIPE_A (0x0<<6) 135 #define OVADD_PIPE_B (0x2<<6) 136 #define OVADD_PIPE_C (0x1<<6) 137 #define LOAD_IEP_BW_EXPANSION (0x1<<4) 138 #define LOAD_IEP_BS_SCC (0x1<<3) 139 #define LOAD_IEP_CSC (0x1<<2) 140 #define LOAD_IEP_DEBUG (0x1<<1) 141 #define LOAD_COEFFICEINT (0x1<<0) 142 143 /* OCONFIG register */ 144 #define CC_OUT_8BIT (0x1<<3) 145 #define OVERLAY_PIPE_MASK (0x1<<18) 146 #define OVERLAY_PIPE_A (0x0<<18) 147 #define OVERLAY_PIPE_B (0x1<<18) 148 #define IEP_LITE_BYPASS (0x1<<27) 149 #define OVERLAY_C_PIPE_MASK (0x3<<17) 150 #define OVERLAY_C_PIPE_A (0x0<<17) 151 #define OVERLAY_C_PIPE_B (0x2<<17) 152 #define OVERLAY_C_PIPE_C (0x1<<17) 153 #define GAMMA2_ENBL (0x1<<16) 154 #define ZORDER_TOP (0x0<<15) 155 #define ZORDER_BOTTOM (0x1<<15) 156 #define CSC_MODE_BT709 (0x1<<5) 157 #define CSC_MODE_BT601 (0x0<<5) 158 #define CSC_BYPASS (0x1<<4) 159 #define THREE_LINE_BUFFERS (0x1<<0) 160 #define TWO_LINE_BUFFERS (0x0<<0) 161 162 /* DCLRKM register */ 163 #define DEST_KEY_ENABLE (0x1<<31) 164 #define CONST_ALPHA_ENABLE (0x1<<30) 165 166 /* Polyphase filter coefficients */ 167 #define N_HORIZ_Y_TAPS 5 168 #define N_VERT_Y_TAPS 3 169 #define N_HORIZ_UV_TAPS 3 170 #define N_VERT_UV_TAPS 3 171 #define N_PHASES 17 172 #define MAX_TAPS 5 173 174 /* Filter cutoff frequency limits. */ 175 #define MIN_CUTOFF_FREQ 1.0 176 #define MAX_CUTOFF_FREQ 3.0 177 178 #define RGB16ToColorKey(c) \ 179 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 180 181 #define RGB15ToColorKey(c) \ 182 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 183 184 typedef struct { 185 uint32_t x1; 186 uint32_t x2; 187 uint32_t y1; 188 uint32_t y2; 189 } BoxRec, *BoxPtr; 190 191 typedef struct { 192 uint32_t OBUF_0Y; 193 uint32_t OBUF_1Y; 194 uint32_t OBUF_0U; 195 uint32_t OBUF_0V; 196 uint32_t OBUF_1U; 197 uint32_t OBUF_1V; 198 uint32_t OSTRIDE; 199 uint32_t YRGB_VPH; 200 uint32_t UV_VPH; 201 uint32_t HORZ_PH; 202 uint32_t INIT_PHS; 203 uint32_t DWINPOS; 204 uint32_t DWINSZ; 205 uint32_t SWIDTH; 206 uint32_t SWIDTHSW; 207 uint32_t SHEIGHT; 208 uint32_t YRGBSCALE; 209 uint32_t UVSCALE; 210 uint32_t OCLRC0; 211 uint32_t OCLRC1; 212 uint32_t DCLRKV; 213 uint32_t DCLRKM; 214 uint32_t SCHRKVH; 215 uint32_t SCHRKVL; 216 uint32_t SCHRKEN; 217 uint32_t OCONFIG; 218 uint32_t OCMD; 219 uint32_t RESERVED1; /* 0x6C */ 220 uint32_t OSTART_0Y; /* for i965 */ 221 uint32_t OSTART_1Y; /* for i965 */ 222 uint32_t OSTART_0U; 223 uint32_t OSTART_0V; 224 uint32_t OSTART_1U; 225 uint32_t OSTART_1V; 226 uint32_t OTILEOFF_0Y; 227 uint32_t OTILEOFF_1Y; 228 uint32_t OTILEOFF_0U; 229 uint32_t OTILEOFF_0V; 230 uint32_t OTILEOFF_1U; 231 uint32_t OTILEOFF_1V; 232 uint32_t FASTHSCALE; /* 0xA0 */ 233 uint32_t UVSCALEV; /* 0xA4 */ 234 235 uint32_t RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 236 uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 237 uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 238 uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 239 uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 240 uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 241 uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 242 uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 243 uint16_t RESERVEDG[0xa00 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 244 uint32_t IEP_SPACE[(0x3401c - 0x31000)/4]; 245 } I830OverlayRegRec, *I830OverlayRegPtr; 246 247 248 #define Degree (2*PI / 360.0) 249 #define PI 3.1415927 250 251 252 typedef struct { 253 uint8_t sign; 254 uint16_t mantissa; 255 uint8_t exponent; 256 } coeffRec, *coeffPtr; 257 258 typedef struct _ov_psb_fixed32 { 259 union { 260 struct { 261 unsigned short Fraction; 262 short Value; 263 }; 264 long ll; 265 }; 266 } ov_psb_fixed32; 267 268 typedef struct _psb_subpictureKeyRec { 269 struct _psb_subpictureKeyRec *next; 270 unsigned int subpic_id; 271 272 int subpic_dstx; 273 int subpic_dsty; 274 int subpic_dstw; 275 int subpic_dsth; 276 } psb_subpictureKeyRec, *psb_subpictureKeyPtr; 277 278 typedef struct _PsbPortPrivRec { 279 int curBuf; 280 int is_mfld; 281 /*subpicture*/ 282 int subpicture_enabled; 283 int subpic_clear_flag; 284 unsigned int subpicture_enable_mask; 285 psb_subpictureKeyRec clear_key[6]; 286 287 /*overlay status*/ 288 int overlayA_pipeId; 289 int overlayC_pipeId; 290 int overlayA_enabled; 291 int overlayC_enabled; 292 293 /*window attribute*/ 294 int last_num_clipbox; 295 VARectangle last_clipbox[16]; 296 int x11_window_width; 297 int x11_window_height; 298 int display_width; 299 int display_height; 300 int extend_display_width; 301 int extend_display_height; 302 303 /* used to check downscale*/ 304 short width_save; 305 short height_save; 306 307 /* information of display attribute */ 308 ov_psb_fixed32 brightness; 309 ov_psb_fixed32 contrast; 310 ov_psb_fixed32 saturation; 311 ov_psb_fixed32 hue; 312 313 unsigned char * p_iep_lite_context; 314 315 /* hwoverlay */ 316 uint32_t gamma0; 317 uint32_t gamma1; 318 uint32_t gamma2; 319 uint32_t gamma3; 320 uint32_t gamma4; 321 uint32_t gamma5; 322 uint32_t colorKey; 323 324 int oneLineMode; 325 int scaleRatio; 326 int rotation; 327 328 struct _WsbmBufferObject *wsbo[2]; 329 uint32_t YBuf0offset; 330 uint32_t UBuf0offset; 331 uint32_t VBuf0offset; 332 uint32_t YBuf1offset; 333 uint32_t UBuf1offset; 334 uint32_t VBuf1offset; 335 unsigned char *regmap[2]; 336 } PsbPortPrivRec, *PsbPortPrivPtr; 337 338 339 int psb_coverlay_init(VADriverContextP ctx); 340 int psb_coverlay_stop(VADriverContextP ctx); 341 int psb_coverlay_exit(VADriverContextP ctx); 342 343 VAStatus psb_putsurface_overlay( 344 VADriverContextP ctx, 345 VASurfaceID surface, 346 short srcx, 347 short srcy, 348 unsigned short srcw, 349 unsigned short srch, 350 short destx, 351 short desty, 352 unsigned short destw, 353 unsigned short desth, 354 unsigned int flags, /* de-interlacing flags */ 355 int overlayId, 356 int pipeId 357 ); 358 359 enum pipe_id_t { 360 PIPEA = 0, 361 PIPEB, 362 PIPEC, 363 }; 364 365 enum overlay_id_t { 366 OVERLAY_A = 0, 367 OVERLAY_C, 368 }; 369 370 #endif /* _PSB_OVERLAY_H_ */ 371