1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform_def.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35ENTRY(bl1_entrypoint)
36
37MEMORY {
38    ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
39    RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
40}
41
42SECTIONS
43{
44    . = BL1_RO_BASE;
45    ASSERT(. == ALIGN(4096),
46           "BL1_RO_BASE address is not aligned on a page boundary.")
47
48    ro . : {
49        __RO_START__ = .;
50        *bl1_entrypoint.o(.text*)
51        *(.text*)
52        *(.rodata*)
53
54        /*
55         * Ensure 8-byte alignment for cpu_ops so that its fields are also
56         * aligned. Also ensure cpu_ops inclusion.
57         */
58        . = ALIGN(8);
59        __CPU_OPS_START__ = .;
60        KEEP(*(cpu_ops))
61        __CPU_OPS_END__ = .;
62
63        *(.vectors)
64        __RO_END__ = .;
65    } >ROM
66
67    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
68           "cpu_ops not defined for this platform.")
69
70    /*
71     * The .data section gets copied from ROM to RAM at runtime.
72     * Its LMA must be 16-byte aligned.
73     * Its VMA must be page-aligned as it marks the first read/write page.
74     */
75    . = BL1_RW_BASE;
76    ASSERT(. == ALIGN(4096),
77           "BL1_RW_BASE address is not aligned on a page boundary.")
78    .data . : ALIGN(16) {
79        __DATA_RAM_START__ = .;
80        *(.data*)
81        __DATA_RAM_END__ = .;
82    } >RAM AT>ROM
83
84    stacks . (NOLOAD) : {
85        __STACKS_START__ = .;
86        *(tzfw_normal_stacks)
87        __STACKS_END__ = .;
88    } >RAM
89
90    /*
91     * The .bss section gets initialised to 0 at runtime.
92     * Its base address must be 16-byte aligned.
93     */
94    .bss : ALIGN(16) {
95        __BSS_START__ = .;
96        *(.bss*)
97        *(COMMON)
98        __BSS_END__ = .;
99    } >RAM
100
101    /*
102     * The xlat_table section is for full, aligned page tables (4K).
103     * Removing them from .bss avoids forcing 4K alignment on
104     * the .bss section and eliminates the unecessary zero init
105     */
106    xlat_table (NOLOAD) : {
107        *(xlat_table)
108    } >RAM
109
110#if USE_COHERENT_MEM
111    /*
112     * The base address of the coherent memory section must be page-aligned (4K)
113     * to guarantee that the coherent data are stored on their own pages and
114     * are not mixed with normal data.  This is required to set up the correct
115     * memory attributes for the coherent data page tables.
116     */
117    coherent_ram (NOLOAD) : ALIGN(4096) {
118        __COHERENT_RAM_START__ = .;
119        *(tzfw_coherent_mem)
120        __COHERENT_RAM_END_UNALIGNED__ = .;
121        /*
122         * Memory page(s) mapped to this section will be marked
123         * as device memory.  No other unexpected data must creep in.
124         * Ensure the rest of the current memory page is unused.
125         */
126        . = NEXT(4096);
127        __COHERENT_RAM_END__ = .;
128    } >RAM
129#endif
130
131    __BL1_RAM_START__ = ADDR(.data);
132    __BL1_RAM_END__ = .;
133
134    __DATA_ROM_START__ = LOADADDR(.data);
135    __DATA_SIZE__ = SIZEOF(.data);
136    /*
137     * The .data section is the last PROGBITS section so its end marks the end
138     * of the read-only part of BL1's binary.
139     */
140    ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT,
141           "BL1's RO section has exceeded its limit.")
142
143    __BSS_SIZE__ = SIZEOF(.bss);
144
145#if USE_COHERENT_MEM
146    __COHERENT_RAM_UNALIGNED_SIZE__ =
147        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
148#endif
149
150    ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
151}
152