1 /*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <arch.h>
32 #include <arch_helpers.h>
33 #include <arm_gic.h>
34 #include <assert.h>
35 #include <bl_common.h>
36 #include <debug.h>
37 #include <gic_v2.h>
38 #include <gic_v3.h>
39 #include <interrupt_mgmt.h>
40 #include <platform.h>
41 #include <stdint.h>
42
43 /* Value used to initialize Non-Secure IRQ priorities four at a time */
44 #define GICD_IPRIORITYR_DEF_VAL \
45 (GIC_HIGHEST_NS_PRIORITY | \
46 (GIC_HIGHEST_NS_PRIORITY << 8) | \
47 (GIC_HIGHEST_NS_PRIORITY << 16) | \
48 (GIC_HIGHEST_NS_PRIORITY << 24))
49
50 static unsigned int g_gicc_base;
51 static unsigned int g_gicd_base;
52 static unsigned long g_gicr_base;
53 static const unsigned int *g_irq_sec_ptr;
54 static unsigned int g_num_irqs;
55
56
57 /*******************************************************************************
58 * This function does some minimal GICv3 configuration. The Firmware itself does
59 * not fully support GICv3 at this time and relies on GICv2 emulation as
60 * provided by GICv3. This function allows software (like Linux) in later stages
61 * to use full GICv3 features.
62 ******************************************************************************/
gicv3_cpuif_setup(void)63 static void gicv3_cpuif_setup(void)
64 {
65 unsigned int scr_val, val;
66 uintptr_t base;
67
68 /*
69 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
70 * bit set. In order to allow interrupts to get routed to the CPU we
71 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
72 * to clear (GICv3 Architecture specification 5.4.23).
73 * GICR_WAKER is NOT banked per CPU, compute the correct base address
74 * per CPU.
75 */
76 assert(g_gicr_base);
77 base = gicv3_get_rdist(g_gicr_base, read_mpidr());
78 if (base == (uintptr_t)NULL) {
79 /* No re-distributor base address. This interface cannot be
80 * configured.
81 */
82 panic();
83 }
84
85 val = gicr_read_waker(base);
86
87 val &= ~WAKER_PS;
88 gicr_write_waker(base, val);
89 dsb();
90
91 /* We need to wait for ChildrenAsleep to clear. */
92 val = gicr_read_waker(base);
93 while (val & WAKER_CA)
94 val = gicr_read_waker(base);
95
96 /*
97 * We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
98 * Restore SCR_EL3.NS again before exit.
99 */
100 scr_val = read_scr();
101 write_scr(scr_val | SCR_NS_BIT);
102 isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */
103
104 /*
105 * By default EL2 and NS-EL1 software should be able to enable GICv3
106 * System register access without any configuration at EL3. But it turns
107 * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
108 * we need to set it here again. In order to do that we need to enable
109 * register access. We leave it enabled as it should be fine and might
110 * prevent problems with later software trying to access GIC System
111 * Registers.
112 */
113 val = read_icc_sre_el3();
114 write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
115
116 val = read_icc_sre_el2();
117 write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
118
119 write_icc_pmr_el1(GIC_PRI_MASK);
120 isb(); /* commit ICC_* changes before setting NS=0 */
121
122 /* Restore SCR_EL3 */
123 write_scr(scr_val);
124 isb(); /* ensure NS=0 takes effect immediately */
125 }
126
127 /*******************************************************************************
128 * This function does some minimal GICv3 configuration when cores go
129 * down.
130 ******************************************************************************/
gicv3_cpuif_deactivate(void)131 static void gicv3_cpuif_deactivate(void)
132 {
133 unsigned int val;
134 uintptr_t base;
135
136 /*
137 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
138 * wait for GICR_WAKER.ChildrenAsleep to get set.
139 * (GICv3 Architecture specification 5.4.23).
140 * GICR_WAKER is NOT banked per CPU, compute the correct base address
141 * per CPU.
142 */
143 assert(g_gicr_base);
144 base = gicv3_get_rdist(g_gicr_base, read_mpidr());
145 if (base == (uintptr_t)NULL) {
146 /* No re-distributor base address. This interface cannot be
147 * configured.
148 */
149 panic();
150 }
151
152 val = gicr_read_waker(base);
153 val |= WAKER_PS;
154 gicr_write_waker(base, val);
155 dsb();
156
157 /* We need to wait for ChildrenAsleep to set. */
158 val = gicr_read_waker(base);
159 while ((val & WAKER_CA) == 0)
160 val = gicr_read_waker(base);
161 }
162
163
164 /*******************************************************************************
165 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
166 * and set the priority mask register to allow all interrupts to trickle in.
167 ******************************************************************************/
arm_gic_cpuif_setup(void)168 void arm_gic_cpuif_setup(void)
169 {
170 unsigned int val;
171
172 assert(g_gicc_base);
173 val = gicc_read_iidr(g_gicc_base);
174
175 /*
176 * If GICv3 we need to do a bit of additional setup. We want to
177 * allow default GICv2 behaviour but allow the next stage to
178 * enable full gicv3 features.
179 */
180 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
181 gicv3_cpuif_setup();
182
183 val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
184 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
185
186 gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
187 gicc_write_ctlr(g_gicc_base, val);
188 }
189
190 /*******************************************************************************
191 * Place the cpu interface in a state where it can never make a cpu exit wfi as
192 * as result of an asserted interrupt. This is critical for powering down a cpu
193 ******************************************************************************/
arm_gic_cpuif_deactivate(void)194 void arm_gic_cpuif_deactivate(void)
195 {
196 unsigned int val;
197
198 /* Disable secure, non-secure interrupts and disable their bypass */
199 assert(g_gicc_base);
200 val = gicc_read_ctlr(g_gicc_base);
201 val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
202 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
203 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
204 gicc_write_ctlr(g_gicc_base, val);
205
206 val = gicc_read_iidr(g_gicc_base);
207
208 /*
209 * If GICv3 we need to do a bit of additional setup. Make sure the
210 * RDIST is put to sleep.
211 */
212 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
213 gicv3_cpuif_deactivate();
214 }
215
216 /*******************************************************************************
217 * Per cpu gic distributor setup which will be done by all cpus after a cold
218 * boot/hotplug. This marks out the secure interrupts & enables them.
219 ******************************************************************************/
arm_gic_pcpu_distif_setup(void)220 void arm_gic_pcpu_distif_setup(void)
221 {
222 unsigned int index, irq_num;
223
224 assert(g_gicd_base);
225
226 /* Mark all 32 SGI+PPI interrupts as Group 1 (non-secure) */
227 gicd_write_igroupr(g_gicd_base, 0, ~0);
228
229 /* Setup PPI priorities doing four at a time */
230 for (index = 0; index < 32; index += 4) {
231 gicd_write_ipriorityr(g_gicd_base, index,
232 GICD_IPRIORITYR_DEF_VAL);
233 }
234
235 assert(g_irq_sec_ptr);
236 for (index = 0; index < g_num_irqs; index++) {
237 irq_num = g_irq_sec_ptr[index];
238 if (irq_num < MIN_SPI_ID) {
239 /* We have an SGI or a PPI */
240 gicd_clr_igroupr(g_gicd_base, irq_num);
241 gicd_set_ipriorityr(g_gicd_base, irq_num,
242 GIC_HIGHEST_SEC_PRIORITY);
243 gicd_set_isenabler(g_gicd_base, irq_num);
244 }
245 }
246 }
247
248 /*******************************************************************************
249 * Get the current CPU bit mask from GICD_ITARGETSR0
250 ******************************************************************************/
arm_gic_get_cpuif_id(void)251 static unsigned int arm_gic_get_cpuif_id(void)
252 {
253 unsigned int val;
254
255 val = gicd_read_itargetsr(g_gicd_base, 0);
256 return val & GIC_TARGET_CPU_MASK;
257 }
258
259 /*******************************************************************************
260 * Global gic distributor setup which will be done by the primary cpu after a
261 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
262 * then enables the secure GIC distributor interface.
263 ******************************************************************************/
arm_gic_distif_setup(void)264 static void arm_gic_distif_setup(void)
265 {
266 unsigned int num_ints, ctlr, index, irq_num;
267 uint8_t target_cpu;
268
269 /* Disable the distributor before going further */
270 assert(g_gicd_base);
271 ctlr = gicd_read_ctlr(g_gicd_base);
272 ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
273 gicd_write_ctlr(g_gicd_base, ctlr);
274
275 /*
276 * Mark out non-secure SPI interrupts. The number of interrupts is
277 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
278 */
279 num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
280 num_ints = (num_ints + 1) << 5;
281 for (index = MIN_SPI_ID; index < num_ints; index += 32)
282 gicd_write_igroupr(g_gicd_base, index, ~0);
283
284 /* Setup SPI priorities doing four at a time */
285 for (index = MIN_SPI_ID; index < num_ints; index += 4) {
286 gicd_write_ipriorityr(g_gicd_base, index,
287 GICD_IPRIORITYR_DEF_VAL);
288 }
289
290 /* Read the target CPU mask */
291 target_cpu = arm_gic_get_cpuif_id();
292
293 /* Configure SPI secure interrupts now */
294 assert(g_irq_sec_ptr);
295 for (index = 0; index < g_num_irqs; index++) {
296 irq_num = g_irq_sec_ptr[index];
297 if (irq_num >= MIN_SPI_ID) {
298 /* We have an SPI */
299 gicd_clr_igroupr(g_gicd_base, irq_num);
300 gicd_set_ipriorityr(g_gicd_base, irq_num,
301 GIC_HIGHEST_SEC_PRIORITY);
302 gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
303 gicd_set_isenabler(g_gicd_base, irq_num);
304 }
305 }
306
307 /*
308 * Configure the SGI and PPI. This is done in a separated function
309 * because each CPU is responsible for initializing its own private
310 * interrupts.
311 */
312 arm_gic_pcpu_distif_setup();
313
314 gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
315 }
316
317 /*******************************************************************************
318 * Initialize the ARM GIC driver with the provided platform inputs
319 ******************************************************************************/
arm_gic_init(unsigned int gicc_base,unsigned int gicd_base,unsigned long gicr_base,const unsigned int * irq_sec_ptr,unsigned int num_irqs)320 void arm_gic_init(unsigned int gicc_base,
321 unsigned int gicd_base,
322 unsigned long gicr_base,
323 const unsigned int *irq_sec_ptr,
324 unsigned int num_irqs
325 )
326 {
327 unsigned int val;
328
329 assert(gicc_base);
330 assert(gicd_base);
331 assert(irq_sec_ptr);
332
333 g_gicc_base = gicc_base;
334 g_gicd_base = gicd_base;
335
336 val = gicc_read_iidr(g_gicc_base);
337
338 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
339 assert(gicr_base);
340 g_gicr_base = gicr_base;
341 }
342
343 g_irq_sec_ptr = irq_sec_ptr;
344 g_num_irqs = num_irqs;
345 }
346
347 /*******************************************************************************
348 * Setup the ARM GIC CPU and distributor interfaces.
349 ******************************************************************************/
arm_gic_setup(void)350 void arm_gic_setup(void)
351 {
352 arm_gic_cpuif_setup();
353 arm_gic_distif_setup();
354 }
355
356 /*******************************************************************************
357 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
358 * The interrupt controller knows which pin/line it uses to signal a type of
359 * interrupt. This function provides a common implementation of
360 * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
361 * across platforms. It lets the interrupt management framework determine
362 * for a type of interrupt and security state, which line should be used in the
363 * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
364 * the bit position of the IRQ or FIQ bit in the SCR_EL3.
365 ******************************************************************************/
arm_gic_interrupt_type_to_line(uint32_t type,uint32_t security_state)366 uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
367 uint32_t security_state)
368 {
369 assert(type == INTR_TYPE_S_EL1 ||
370 type == INTR_TYPE_EL3 ||
371 type == INTR_TYPE_NS);
372
373 assert(sec_state_is_valid(security_state));
374
375 /*
376 * We ignore the security state parameter under the assumption that
377 * both normal and secure worlds are using ARM GICv2. This parameter
378 * will be used when the secure world starts using GICv3.
379 */
380 #if ARM_GIC_ARCH == 2
381 return gicv2_interrupt_type_to_line(g_gicc_base, type);
382 #else
383 #error "Invalid ARM GIC architecture version specified for platform port"
384 #endif /* ARM_GIC_ARCH */
385 }
386
387 #if ARM_GIC_ARCH == 2
388 /*******************************************************************************
389 * This function returns the type of the highest priority pending interrupt at
390 * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
391 * interrupt pending.
392 ******************************************************************************/
arm_gic_get_pending_interrupt_type(void)393 uint32_t arm_gic_get_pending_interrupt_type(void)
394 {
395 uint32_t id;
396
397 assert(g_gicc_base);
398 id = gicc_read_hppir(g_gicc_base);
399
400 /* Assume that all secure interrupts are S-EL1 interrupts */
401 if (id < 1022)
402 return INTR_TYPE_S_EL1;
403
404 if (id == GIC_SPURIOUS_INTERRUPT)
405 return INTR_TYPE_INVAL;
406
407 return INTR_TYPE_NS;
408 }
409
410 /*******************************************************************************
411 * This function returns the id of the highest priority pending interrupt at
412 * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
413 * interrupt pending.
414 ******************************************************************************/
arm_gic_get_pending_interrupt_id(void)415 uint32_t arm_gic_get_pending_interrupt_id(void)
416 {
417 uint32_t id;
418
419 assert(g_gicc_base);
420 id = gicc_read_hppir(g_gicc_base);
421
422 if (id < 1022)
423 return id;
424
425 if (id == 1023)
426 return INTR_ID_UNAVAILABLE;
427
428 /*
429 * Find out which non-secure interrupt it is under the assumption that
430 * the GICC_CTLR.AckCtl bit is 0.
431 */
432 return gicc_read_ahppir(g_gicc_base);
433 }
434
435 /*******************************************************************************
436 * This functions reads the GIC cpu interface Interrupt Acknowledge register
437 * to start handling the pending interrupt. It returns the contents of the IAR.
438 ******************************************************************************/
arm_gic_acknowledge_interrupt(void)439 uint32_t arm_gic_acknowledge_interrupt(void)
440 {
441 assert(g_gicc_base);
442 return gicc_read_IAR(g_gicc_base);
443 }
444
445 /*******************************************************************************
446 * This functions writes the GIC cpu interface End Of Interrupt register with
447 * the passed value to finish handling the active interrupt
448 ******************************************************************************/
arm_gic_end_of_interrupt(uint32_t id)449 void arm_gic_end_of_interrupt(uint32_t id)
450 {
451 assert(g_gicc_base);
452 gicc_write_EOIR(g_gicc_base, id);
453 }
454
455 /*******************************************************************************
456 * This function returns the type of the interrupt id depending upon the group
457 * this interrupt has been configured under by the interrupt controller i.e.
458 * group0 or group1.
459 ******************************************************************************/
arm_gic_get_interrupt_type(uint32_t id)460 uint32_t arm_gic_get_interrupt_type(uint32_t id)
461 {
462 uint32_t group;
463
464 assert(g_gicd_base);
465 group = gicd_get_igroupr(g_gicd_base, id);
466
467 /* Assume that all secure interrupts are S-EL1 interrupts */
468 if (group == GRP0)
469 return INTR_TYPE_S_EL1;
470 else
471 return INTR_TYPE_NS;
472 }
473
474 #else
475 #error "Invalid ARM GIC architecture version specified for platform port"
476 #endif /* ARM_GIC_ARCH */
477