1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33
34	.globl	bl1_entrypoint
35
36
37	/* -----------------------------------------------------
38	 * bl1_entrypoint() is the entry point into the trusted
39	 * firmware code when a cpu is released from warm or
40	 * cold reset.
41	 * -----------------------------------------------------
42	 */
43
44func bl1_entrypoint
45	/* ---------------------------------------------
46	 * Set the CPU endianness before doing anything
47	 * that might involve memory reads or writes.
48	 * ---------------------------------------------
49	 */
50	mrs	x0, sctlr_el3
51	bic	x0, x0, #SCTLR_EE_BIT
52	msr	sctlr_el3, x0
53	isb
54
55	/* ---------------------------------------------
56	 * Perform any processor specific actions upon
57	 * reset e.g. cache, tlb invalidations etc.
58	 * ---------------------------------------------
59	 */
60	bl	reset_handler
61
62	/* ---------------------------------------------
63	 * Enable the instruction cache, stack pointer
64	 * and data access alignment checks
65	 * ---------------------------------------------
66	 */
67	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
68	mrs	x0, sctlr_el3
69	orr	x0, x0, x1
70	msr	sctlr_el3, x0
71	isb
72
73	/* ---------------------------------------------
74	 * Set the exception vector to something sane.
75	 * ---------------------------------------------
76	 */
77	adr	x0, bl1_exceptions
78	msr	vbar_el3, x0
79	isb
80
81	/* ---------------------------------------------
82	 * Enable the SError interrupt now that the
83	 * exception vectors have been setup.
84	 * ---------------------------------------------
85	 */
86	msr	daifclr, #DAIF_ABT_BIT
87
88	/* ---------------------------------------------------------------------
89	 * The initial state of the Architectural feature trap register
90	 * (CPTR_EL3) is unknown and it must be set to a known state. All
91	 * feature traps are disabled. Some bits in this register are marked as
92	 * Reserved and should not be modified.
93	 *
94	 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
95	 *  or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
96	 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
97	 *  to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
98	 *  access to trace functionality is not supported, this bit is RES0.
99	 * CPTR_EL3.TFP: This causes instructions that access the registers
100	 *  associated with Floating Point and Advanced SIMD execution to trap
101	 *  to EL3 when executed from any exception level, unless trapped to EL1
102	 *  or EL2.
103	 * ---------------------------------------------------------------------
104	 */
105	mrs	x0, cptr_el3
106	bic	w0, w0, #TCPAC_BIT
107	bic	w0, w0, #TTA_BIT
108	bic	w0, w0, #TFP_BIT
109	msr	cptr_el3, x0
110
111	/* -------------------------------------------------------
112	 * Will not return from this macro if it is a warm boot.
113	 * -------------------------------------------------------
114	 */
115	wait_for_entrypoint
116
117	bl	platform_mem_init
118
119	/* ---------------------------------------------
120	 * Init C runtime environment.
121	 *   - Zero-initialise the NOBITS sections.
122	 *     There are 2 of them:
123	 *       - the .bss section;
124	 *       - the coherent memory section.
125	 *   - Copy the data section from BL1 image
126	 *     (stored in ROM) to the correct location
127	 *     in RAM.
128	 * ---------------------------------------------
129	 */
130	ldr	x0, =__BSS_START__
131	ldr	x1, =__BSS_SIZE__
132	bl	zeromem16
133
134#if USE_COHERENT_MEM
135	ldr	x0, =__COHERENT_RAM_START__
136	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
137	bl	zeromem16
138#endif
139
140	ldr	x0, =__DATA_RAM_START__
141	ldr	x1, =__DATA_ROM_START__
142	ldr	x2, =__DATA_SIZE__
143	bl	memcpy16
144
145	/* --------------------------------------------
146	 * Allocate a stack whose memory will be marked
147	 * as Normal-IS-WBWA when the MMU is enabled.
148	 * There is no risk of reading stale stack
149	 * memory after enabling the MMU as only the
150	 * primary cpu is running at the moment.
151	 * --------------------------------------------
152	 */
153	mrs	x0, mpidr_el1
154	bl	platform_set_stack
155
156	/* ---------------------------------------------
157	 * Architectural init. can be generic e.g.
158	 * enabling stack alignment and platform spec-
159	 * ific e.g. MMU & page table setup as per the
160	 * platform memory map. Perform the latter here
161	 * and the former in bl1_main.
162	 * ---------------------------------------------
163	 */
164	bl	bl1_early_platform_setup
165	bl	bl1_plat_arch_setup
166
167	/* --------------------------------------------------
168	 * Initialize platform and jump to our c-entry point
169	 * for this type of reset. Panic if it returns
170	 * --------------------------------------------------
171	 */
172	bl	bl1_main
173panic:
174	b	panic
175