1 /*
2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <arch_helpers.h>
33 #include <console.h>
34 #include <debug.h>
35 #include <errno.h>
36 #include <hi6220.h>
37 #include <hi6553.h>
38 #include <mmio.h>
39 #include <platform_def.h>
40 #include <sp804_timer.h>
41
init_pll(void)42 static void init_pll(void)
43 {
44 unsigned int data;
45
46 data = mmio_read_32((0xf7032000 + 0x000));
47 data |= 0x1;
48 mmio_write_32((0xf7032000 + 0x000), data);
49 dsb();
50 do {
51 data = mmio_read_32((0xf7032000 + 0x000));
52 } while (!(data & (1 << 28)));
53
54 data = mmio_read_32((0xf7800000 + 0x000));
55 data &= ~0x007;
56 data |= 0x004;
57 mmio_write_32((0xf7800000 + 0x000), data);
58 dsb();
59 do {
60 data = mmio_read_32((0xf7800000 + 0x014));
61 data &= 0x007;
62 } while (data != 0x004);
63
64 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
65 data = mmio_read_32(PERI_SC_PERIPH_STAT1);
66 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e);
67 data = mmio_read_32(0xf7032000 + 0x050);
68 data |= 1 << 28;
69 mmio_write_32(0xf7032000 + 0x050, data);
70 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
71 mdelay(1);
72 data = mmio_read_32(PERI_SC_PERIPH_STAT1);
73 NOTICE("syspll frequency:%dHz\n", data);
74 }
75
init_freq(void)76 static void init_freq(void)
77 {
78 unsigned int data, tmp;
79 unsigned int cpuext_cfg, ddr_cfg;
80
81 mmio_write_32((0xf7032000 + 0x374), 0x4a);
82 mmio_write_32((0xf7032000 + 0x368), 0xda);
83 mmio_write_32((0xf7032000 + 0x36c), 0x01);
84 mmio_write_32((0xf7032000 + 0x370), 0x01);
85 mmio_write_32((0xf7032000 + 0x360), 0x60);
86 mmio_write_32((0xf7032000 + 0x364), 0x60);
87
88 mmio_write_32((0xf7032000 + 0x114), 0x1000);
89
90 data = mmio_read_32((0xf7032000 + 0x110));
91 data |= (3 << 12);
92 mmio_write_32((0xf7032000 + 0x110), data);
93
94 data = mmio_read_32((0xf7032000 + 0x110));
95 data |= (1 << 4);
96 mmio_write_32((0xf7032000 + 0x110), data);
97
98
99 data = mmio_read_32((0xf7032000 + 0x110));
100 data &= ~0x7;
101 data |= 0x5;
102 mmio_write_32((0xf7032000 + 0x110), data);
103 dsb();
104 mdelay(10);
105
106
107 do {
108 data = mmio_read_32((0xf6504000 + 0x008));
109 data &= (3 << 20);
110 } while (data != (3 << 20));
111 dsb();
112 mdelay(10);
113
114
115 data = mmio_read_32((0xf6504000 + 0x054));
116 data &= ~((1 << 0) | (1 << 11));
117 mmio_write_32((0xf6504000 + 0x054), data);
118 mdelay(10);
119
120 data = mmio_read_32((0xf7032000 + 0x104));
121 data &= ~(3 << 8);
122 data |= (1 << 8);
123 mmio_write_32((0xf7032000 + 0x104), data);
124
125 data = mmio_read_32((0xf7032000 + 0x100));
126 data |= (1 << 0);
127 mmio_write_32((0xf7032000 + 0x100), data);
128 dsb();
129
130 do {
131 data = mmio_read_32((0xf7032000 + 0x100));
132 data &= (1 << 2);
133 } while (data != (1 << 2));
134
135 data = mmio_read_32((0xf6504000 + 0x06c));
136 data &= ~0xffff;
137 data |= 0x56;
138 mmio_write_32((0xf6504000 + 0x06c), data);
139
140 data = mmio_read_32((0xf6504000 + 0x06c));
141 data &= ~(0xffffff << 8);
142 data |= 0xc7a << 8;
143 mmio_write_32((0xf6504000 + 0x06c), data);
144
145 data = mmio_read_32((0xf6504000 + 0x058));
146 data &= ((1 << 13) - 1);
147 data |= 0xccb;
148 mmio_write_32((0xf6504000 + 0x058), data);
149
150 mmio_write_32((0xf6504000 + 0x060), 0x1fff);
151 mmio_write_32((0xf6504000 + 0x064), 0x1ffffff);
152 mmio_write_32((0xf6504000 + 0x068), 0x7fffffff);
153 mmio_write_32((0xf6504000 + 0x05c), 0x1);
154
155 data = mmio_read_32((0xf6504000 + 0x054));
156 data &= ~(0xf << 12);
157 data |= 1 << 12;
158 mmio_write_32((0xf6504000 + 0x054), data);
159 dsb();
160
161
162 data = mmio_read_32((0xf7032000 + 0x000));
163 data &= ~(1 << 0);
164 mmio_write_32((0xf7032000 + 0x000), data);
165
166 mmio_write_32((0xf7032000 + 0x004), 0x5110207d);
167 mmio_write_32((0xf7032000 + 0x134), 0x10000005);
168 data = mmio_read_32((0xf7032000 + 0x134));
169
170
171 data = mmio_read_32((0xf7032000 + 0x000));
172 data |= (1 << 0);
173 mmio_write_32((0xf7032000 + 0x000), data);
174
175 mmio_write_32((0xf7032000 + 0x368), 0x100da);
176 data = mmio_read_32((0xf7032000 + 0x378));
177 data &= ~((1 << 7) - 1);
178 data |= 0x6b;
179 mmio_write_32((0xf7032000 + 0x378), data);
180 dsb();
181 do {
182 data = mmio_read_32((0xf7032000 + 0x378));
183 tmp = data & 0x7f;
184 data = (data & (0x7f << 8)) >> 8;
185 if (data != tmp)
186 continue;
187 data = mmio_read_32((0xf7032000 + 0x37c));
188 } while (!(data & 1));
189
190 data = mmio_read_32((0xf7032000 + 0x104));
191 data &= ~((3 << 0) |
192 (3 << 8));
193 cpuext_cfg = 1;
194 ddr_cfg = 1;
195 data |= cpuext_cfg | (ddr_cfg << 8);
196 mmio_write_32((0xf7032000 + 0x104), data);
197 dsb();
198
199 do {
200 data = mmio_read_32((0xf7032000 + 0x104));
201 tmp = (data & (3 << 16)) >> 16;
202 if (cpuext_cfg != tmp)
203 continue;
204 tmp = (data & (3 << 24)) >> 24;
205 if (ddr_cfg != tmp)
206 continue;
207 data = mmio_read_32((0xf7032000 + 0x000));
208 data &= 1 << 28;
209 } while (!data);
210
211 data = mmio_read_32((0xf7032000 + 0x100));
212 data &= ~(1 << 0);
213 mmio_write_32((0xf7032000 + 0x100), data);
214 dsb();
215 do {
216 data = mmio_read_32((0xf7032000 + 0x100));
217 data &= (1 << 1);
218 } while (data != (1 << 1));
219 mdelay(1000);
220
221 data = mmio_read_32((0xf6504000 + 0x054));
222 data &= ~(1 << 28);
223 mmio_write_32((0xf6504000 + 0x054), data);
224 dsb();
225
226 data = mmio_read_32((0xf7032000 + 0x110));
227 data &= ~((1 << 4) |
228 (3 << 12));
229 mmio_write_32((0xf7032000 + 0x110), data);
230 }
231
cat_533mhz_800mhz(void)232 int cat_533mhz_800mhz(void)
233 {
234 unsigned int data, i;
235 unsigned int bdl[5];
236
237
238 data = mmio_read_32((0xf712c000 + 0x1c8));
239 data &= 0xfffff0f0;
240 data |= 0x100f0f;
241 mmio_write_32((0xf712c000 + 0x1c8), data);
242
243 for (i = 0; i < 0x20; i++) {
244 mmio_write_32((0xf712c000 + 0x1d4), 0xc0000);
245 data = (i << 0x10) + i;
246 mmio_write_32((0xf712c000 + 0x140), data);
247 mmio_write_32((0xf712c000 + 0x144), data);
248 mmio_write_32((0xf712c000 + 0x148), data);
249 mmio_write_32((0xf712c000 + 0x14c), data);
250 mmio_write_32((0xf712c000 + 0x150), data);
251
252
253 data = mmio_read_32((0xf712c000 + 0x070));
254 data |= 0x80000;
255 mmio_write_32((0xf712c000 + 0x070), data);
256 data = mmio_read_32((0xf712c000 + 0x070));
257 data &= 0xfff7ffff;
258 mmio_write_32((0xf712c000 + 0x070), data);
259
260
261 mmio_write_32((0xf712c000 + 0x004), 0x8000);
262 mmio_write_32((0xf712c000 + 0x004), 0x0);
263 mmio_write_32((0xf712c000 + 0x004), 0x801);
264 do {
265 data = mmio_read_32((0xf712c000 + 0x004));
266 } while (data & 1);
267
268 data = mmio_read_32((0xf712c000 + 0x008));
269 if (!(data & 0x400)) {
270 mdelay(10);
271 return 0;
272 }
273 tf_printf("WARN: " "lpddr3 cat fail\n");
274 data = mmio_read_32((0xf712c000 + 0x1d4));
275 if ((data & 0x1f00) && ((data & 0x1f) == 0)) {
276 bdl[0] = mmio_read_32((0xf712c000 + 0x140));
277 bdl[1] = mmio_read_32((0xf712c000 + 0x144));
278 bdl[2] = mmio_read_32((0xf712c000 + 0x148));
279 bdl[3] = mmio_read_32((0xf712c000 + 0x14c));
280 bdl[4] = mmio_read_32((0xf712c000 + 0x150));
281 if ((!(bdl[0] & 0x1f001f)) || (!(bdl[1] & 0x1f001f)) ||
282 (!(bdl[2] & 0x1f001f)) || (!(bdl[3] & 0x1f001f)) ||
283 (!(bdl[4] & 0x1f001f))) {
284 tf_printf("WARN: " "lpddr3 cat deskew error\n");
285 if (i == 0x1f) {
286 tf_printf("WARN: " "addrnbdl is max\n");
287 return -22;
288 }
289 mmio_write_32((0xf712c000 + 0x008), 0x400);
290 } else {
291 tf_printf("WARN: " "lpddr3 cat other error1\n");
292 return -22;
293 }
294 } else {
295 tf_printf("WARN: " "lpddr3 cat other error2\n");
296 return -22;
297 }
298 }
299 return -22;
300 }
301
ddrx_rdet(void)302 static void ddrx_rdet(void)
303 {
304 unsigned int data, rdet, bdl[4];
305
306 data = mmio_read_32((0xf712c000 + 0x0d0));
307 data &= 0xf800ffff;
308 data |= 0x8f0000;
309 mmio_write_32((0xf712c000 + 0x0d0), data);
310
311 data = mmio_read_32((0xf712c000 + 0x0dc));
312 data &= 0xfffffff0;
313 data |= 0xf;
314 mmio_write_32((0xf712c000 + 0x0dc), data);
315
316
317 data = mmio_read_32((0xf712c000 + 0x070));
318 data |= 0x80000;
319 mmio_write_32((0xf712c000 + 0x070), data);
320 data = mmio_read_32((0xf712c000 + 0x070));
321 data &= 0xfff7ffff;
322 mmio_write_32((0xf712c000 + 0x070), data);
323
324 mmio_write_32((0xf712c000 + 0x004), 0x8000);
325 mmio_write_32((0xf712c000 + 0x004), 0);
326
327 data = mmio_read_32((0xf712c000 + 0x0d0));
328 data &= ~0xf0000000;
329 data |= 0x80000000;
330 mmio_write_32((0xf712c000 + 0x0d0), data);
331
332 mmio_write_32((0xf712c000 + 0x004), 0x101);
333 do {
334 data = mmio_read_32((0xf712c000 + 0x004));
335 } while (!(data & 1));
336 data = mmio_read_32((0xf712c000 + 0x008));
337 if (data & 0x100)
338 tf_printf("WARN: " "rdet lbs fail\n");
339
340 bdl[0] = mmio_read_32((0xf712c000 + 0x22c)) & 0x7f;
341 bdl[1] = mmio_read_32((0xf712c000 + 0x2ac)) & 0x7f;
342 bdl[2] = mmio_read_32((0xf712c000 + 0x32c)) & 0x7f;
343 bdl[3] = mmio_read_32((0xf712c000 + 0x3ac)) & 0x7f;
344 do {
345 data = mmio_read_32((0xf712c000 + 0x22c));
346 data &= ~0x7f;
347 data |= bdl[0];
348 mmio_write_32((0xf712c000 + 0x22c), data);
349 data = mmio_read_32((0xf712c000 + 0x2ac));
350 data &= ~0x7f;
351 data |= bdl[1];
352 mmio_write_32((0xf712c000 + 0x2ac), data);
353 data = mmio_read_32((0xf712c000 + 0x32c));
354 data &= ~0x7f;
355 data |= bdl[2];
356 mmio_write_32((0xf712c000 + 0x32c), data);
357 data = mmio_read_32((0xf712c000 + 0x3ac));
358 data &= ~0x7f;
359 data |= bdl[3];
360 mmio_write_32((0xf712c000 + 0x3ac), data);
361
362
363 data = mmio_read_32((0xf712c000 + 0x070));
364 data |= 0x80000;
365 mmio_write_32((0xf712c000 + 0x070), data);
366 data = mmio_read_32((0xf712c000 + 0x070));
367 data &= 0xfff7ffff;
368 mmio_write_32((0xf712c000 + 0x070), data);
369
370 mmio_write_32((0xf712c000 + 0x004), 0x8000);
371 mmio_write_32((0xf712c000 + 0x004), 0);
372
373 data = mmio_read_32((0xf712c000 + 0x0d0));
374 data &= ~0xf0000000;
375 data |= 0x40000000;
376 mmio_write_32((0xf712c000 + 0x0d0), data);
377 mmio_write_32((0xf712c000 + 0x004), 0x101);
378 do {
379 data = mmio_read_32((0xf712c000 + 0x004));
380 } while (data & 1);
381
382 data = mmio_read_32((0xf712c000 + 0x008));
383 rdet = data & 0x100;
384 if (rdet) {
385 tf_printf("INFO: " "rdet ds fail\n");
386 mmio_write_32((0xf712c000 + 0x008), 0x100);
387 }
388 bdl[0]++;
389 bdl[1]++;
390 bdl[2]++;
391 bdl[3]++;
392 } while (rdet);
393
394 data = mmio_read_32((0xf712c000 + 0x0d0));
395 data &= ~0xf0000000;
396 data |= 0x30000000;
397 mmio_write_32((0xf712c000 + 0x0d0), data);
398
399 mmio_write_32((0xf712c000 + 0x004), 0x101);
400 do {
401 data = mmio_read_32((0xf712c000 + 0x004));
402 } while (data & 1);
403 data = mmio_read_32((0xf712c000 + 0x008));
404 if (data & 0x100)
405 tf_printf("INFO: " "rdet rbs av fail\n");
406 }
407
ddrx_wdet(void)408 static void ddrx_wdet(void)
409 {
410 unsigned int data, wdet, zero_bdl, dq[4];
411 int i;
412
413 data = mmio_read_32((0xf712c000 + 0x0d0));
414 data &= ~0xf;
415 data |= 0xf;
416 mmio_write_32((0xf712c000 + 0x0d0), data);
417
418 data = mmio_read_32((0xf712c000 + 0x070));
419 data |= 0x80000;
420 mmio_write_32((0xf712c000 + 0x070), data);
421 data = mmio_read_32((0xf712c000 + 0x070));
422 data &= ~0x80000;
423 mmio_write_32((0xf712c000 + 0x070), data);
424
425 mmio_write_32((0xf712c000 + 0x004), 0x8000);
426 mmio_write_32((0xf712c000 + 0x004), 0);
427 data = mmio_read_32((0xf712c000 + 0x0d0));
428 data &= ~0xf000;
429 data |= 0x8000;
430 mmio_write_32((0xf712c000 + 0x0d0), data);
431 mmio_write_32((0xf712c000 + 0x004), 0x201);
432 do {
433 data = mmio_read_32((0xf712c000 + 0x004));
434 } while (data & 1);
435 data = mmio_read_32((0xf712c000 + 0x008));
436 if (data & 0x200)
437 tf_printf("INFO: " "wdet lbs fail\n");
438
439 dq[0] = mmio_read_32((0xf712c000 + 0x234)) & 0x1f00;
440 dq[1] = mmio_read_32((0xf712c000 + 0x2b4)) & 0x1f00;
441 dq[2] = mmio_read_32((0xf712c000 + 0x334)) & 0x1f00;
442 dq[3] = mmio_read_32((0xf712c000 + 0x3b4)) & 0x1f00;
443
444 do {
445 mmio_write_32((0xf712c000 + 0x234), dq[0]);
446 mmio_write_32((0xf712c000 + 0x2b4), dq[1]);
447 mmio_write_32((0xf712c000 + 0x334), dq[2]);
448 mmio_write_32((0xf712c000 + 0x3b4), dq[3]);
449
450 data = mmio_read_32((0xf712c000 + 0x070));
451 data |= 0x80000;
452 mmio_write_32((0xf712c000 + 0x070), data);
453 data = mmio_read_32((0xf712c000 + 0x070));
454 data &= ~0x80000;
455 mmio_write_32((0xf712c000 + 0x070), data);
456 mmio_write_32((0xf712c000 + 0x004), 0x8000);
457 mmio_write_32((0xf712c000 + 0x004), 0);
458
459 data = mmio_read_32((0xf712c000 + 0x0d0));
460 data &= ~0xf000;
461 data |= 0x4000;
462 mmio_write_32((0xf712c000 + 0x0d0), data);
463 mmio_write_32((0xf712c000 + 0x004), 0x201);
464 do {
465 data = mmio_read_32((0xf712c000 + 0x004));
466 } while (data & 1);
467
468 data = mmio_read_32((0xf712c000 + 0x008));
469 wdet = data & 0x200;
470 if (wdet) {
471 tf_printf("INFO: " "wdet ds fail\n");
472 mmio_write_32((0xf712c000 + 0x008), 0x200);
473 }
474 mdelay(10);
475
476 for (i = 0; i < 4; i++) {
477 data = mmio_read_32((0xf712c000 + 0x210 + i * 0x80));
478 if ((!(data & 0x1f)) || (!(data & 0x1f00)) ||
479 (!(data & 0x1f0000)) || (!(data & 0x1f000000)))
480 zero_bdl = 1;
481 data = mmio_read_32((0xf712c000 + 0x214 + i * 0x80));
482 if ((!(data & 0x1f)) || (!(data & 0x1f00)) ||
483 (!(data & 0x1f0000)) || (!(data & 0x1f000000)))
484 zero_bdl = 1;
485 data = mmio_read_32((0xf712c000 + 0x218 + i * 0x80));
486 if (!(data & 0x1f))
487 zero_bdl = 1;
488 if (zero_bdl) {
489 if (i == 0)
490 dq[0] = dq[0] - 0x100;
491 if (i == 1)
492 dq[1] = dq[1] - 0x100;
493 if (i == 2)
494 dq[2] = dq[2] - 0x100;
495 if (i == 3)
496 dq[3] = dq[3] - 0x100;
497 }
498 }
499 } while (wdet);
500
501 data = mmio_read_32((0xf712c000 + 0x0d0));
502 data &= ~0xf000;
503 data |= 0x3000;
504 mmio_write_32((0xf712c000 + 0x0d0), data);
505 mmio_write_32((0xf712c000 + 0x004), 0x201);
506 do {
507 data = mmio_read_32((0xf712c000 + 0x004));
508 } while (data & 1);
509 data = mmio_read_32((0xf712c000 + 0x008));
510 if (data & 0x200)
511 tf_printf("INFO: " "wdet rbs av fail\n");
512 }
513
set_ddrc_533mhz(void)514 static void set_ddrc_533mhz(void)
515 {
516 unsigned int data;
517
518 mmio_write_32((0xf7032000 + 0x580), 0x3);
519 mmio_write_32((0xf7032000 + 0x5a8), 0x11111);
520 data = mmio_read_32((0xf7032000 + 0x104));
521 data |= 0x100;
522 mmio_write_32((0xf7032000 + 0x104), data);
523
524 mmio_write_32((0xf7030000 + 0x050), 0x30);
525 mmio_write_32((0xf7030000 + 0x240), 0x5ffff);
526 mmio_write_32((0xf7030000 + 0x344), 0xf5ff);
527 mmio_write_32((0xf712c000 + 0x00c), 0x400);
528 mmio_write_32((0xf712c000 + 0x018), 0x7);
529 mmio_write_32((0xf712c000 + 0x090), 0x6400000);
530 mmio_write_32((0xf712c000 + 0x258), 0x640);
531 mmio_write_32((0xf712c000 + 0x2d8), 0x640);
532 mmio_write_32((0xf712c000 + 0x358), 0x640);
533 mmio_write_32((0xf712c000 + 0x3d8), 0x640);
534 mmio_write_32((0xf712c000 + 0x018), 0x0);
535 mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f);
536 mmio_write_32((0xf712c000 + 0x0b4), 0xf);
537 mmio_write_32((0xf712c000 + 0x088), 0x3fff801);
538 mmio_write_32((0xf712c000 + 0x070), 0x8940000);
539
540 data = mmio_read_32((0xf712c000 + 0x078));
541 data |= 4;
542 mmio_write_32((0xf712c000 + 0x078), data);
543 mmio_write_32((0xf712c000 + 0x01c), 0x8000080);
544 data = mmio_read_32((0xf712c000 + 0x020));
545 data &= 0xfffffffe;
546 mmio_write_32((0xf712c000 + 0x020), data);
547 mmio_write_32((0xf712c000 + 0x1d4), 0xc0000);
548 mmio_write_32((0xf712c000 + 0x010), 0x500000f);
549 mmio_write_32((0xf712c000 + 0x014), 0x10);
550 data = mmio_read_32((0xf712c000 + 0x1e4));
551 data &= 0xffffff00;
552 mmio_write_32((0xf712c000 + 0x1e4), data);
553 mmio_write_32((0xf712c000 + 0x030), 0x9dd87855);
554 mmio_write_32((0xf712c000 + 0x034), 0xa7138bb);
555 mmio_write_32((0xf712c000 + 0x038), 0x20091477);
556 mmio_write_32((0xf712c000 + 0x03c), 0x84534e16);
557 mmio_write_32((0xf712c000 + 0x040), 0x3008817);
558 mmio_write_32((0xf712c000 + 0x064), 0x106c3);
559 mmio_write_32((0xf712c000 + 0x068), 0xff0a0000);
560 data = mmio_read_32((0xf712c000 + 0x070));
561 data &= 0xffff0000;
562 data |= 0x305;
563 mmio_write_32((0xf712c000 + 0x070), data);
564 data = mmio_read_32((0xf712c000 + 0x048));
565 data |= 0x40000000;
566 mmio_write_32((0xf712c000 + 0x048), data);
567 data = mmio_read_32((0xf712c000 + 0x020));
568 data &= ~0x10;
569 mmio_write_32((0xf712c000 + 0x020), data);
570 data = mmio_read_32((0xf712c000 + 0x080));
571 data &= ~0x2000;
572 mmio_write_32((0xf712c000 + 0x080), data);
573 mmio_write_32((0xf712c000 + 0x270), 0x3);
574 mmio_write_32((0xf712c000 + 0x2f0), 0x3);
575 mmio_write_32((0xf712c000 + 0x370), 0x3);
576 mmio_write_32((0xf712c000 + 0x3f0), 0x3);
577 mmio_write_32((0xf712c000 + 0x048), 0xd0420900);
578
579 mmio_write_32((0xf7128000 + 0x040), 0x0);
580 mmio_write_32((0xf712c000 + 0x004), 0x140f);
581 do {
582 data = mmio_read_32((0xf712c000 + 0x004));
583 } while (data & 1);
584 data = mmio_read_32((0xf712c000 + 0x008));
585 if (data & 0x7fe) {
586 tf_printf("NOTICE: " "failed to init lpddr3 rank0 dram phy\n");
587 return;
588 }
589 tf_printf("NOTICE: " "succeed to init lpddr3 rank0 dram phy\n");
590 }
591
set_ddrc_800mhz(void)592 static void set_ddrc_800mhz(void)
593 {
594 unsigned int data;
595
596 mmio_write_32((0xf7032000 + 0x580), 0x2);
597 mmio_write_32((0xf7032000 + 0x5a8), 0x1003);
598 data = mmio_read_32((0xf7032000 + 0x104));
599 data &= 0xfffffcff;
600 mmio_write_32((0xf7032000 + 0x104), data);
601
602 mmio_write_32((0xf7030000 + 0x050), 0x30);
603 mmio_write_32((0xf7030000 + 0x240), 0x5ffff);
604 mmio_write_32((0xf7030000 + 0x344), 0xf5ff);
605 mmio_write_32((0xf712c000 + 0x00c), 0x400);
606 mmio_write_32((0xf712c000 + 0x018), 0x7);
607 mmio_write_32((0xf712c000 + 0x090), 0x5400000);
608 mmio_write_32((0xf712c000 + 0x258), 0x540);
609 mmio_write_32((0xf712c000 + 0x2d8), 0x540);
610 mmio_write_32((0xf712c000 + 0x358), 0x540);
611 mmio_write_32((0xf712c000 + 0x3d8), 0x540);
612 mmio_write_32((0xf712c000 + 0x018), 0x0);
613 mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f);
614 mmio_write_32((0xf712c000 + 0x0b4), 0xf);
615 mmio_write_32((0xf712c000 + 0x088), 0x3fff801);
616 mmio_write_32((0xf712c000 + 0x070), 0x8940000);
617
618 data = mmio_read_32((0xf712c000 + 0x078));
619 data |= 4;
620 mmio_write_32((0xf712c000 + 0x078), data);
621 mmio_write_32((0xf712c000 + 0x01c), 0x8000080);
622 data = mmio_read_32((0xf712c000 + 0x020));
623 data &= 0xfffffffe;
624 mmio_write_32((0xf712c000 + 0x020), data);
625 mmio_write_32((0xf712c000 + 0x1d4), 0xc0000);
626 mmio_write_32((0xf712c000 + 0x010), 0x500000f);
627 mmio_write_32((0xf712c000 + 0x014), 0x10);
628 data = mmio_read_32((0xf712c000 + 0x1e4));
629 data &= 0xffffff00;
630 mmio_write_32((0xf712c000 + 0x1e4), data);
631 mmio_write_32((0xf712c000 + 0x030), 0xe663ab77);
632 mmio_write_32((0xf712c000 + 0x034), 0xea952db);
633 mmio_write_32((0xf712c000 + 0x038), 0x200d1cb1);
634 mmio_write_32((0xf712c000 + 0x03c), 0xc67d0721);
635 mmio_write_32((0xf712c000 + 0x040), 0x3008aa1);
636 mmio_write_32((0xf712c000 + 0x064), 0x11a43);
637 mmio_write_32((0xf712c000 + 0x068), 0xff0a0000);
638 data = mmio_read_32((0xf712c000 + 0x070));
639 data &= 0xffff0000;
640 data |= 0x507;
641 mmio_write_32((0xf712c000 + 0x070), data);
642 data = mmio_read_32((0xf712c000 + 0x048));
643 data |= 0x40000000;
644 mmio_write_32((0xf712c000 + 0x048), data);
645 data = mmio_read_32((0xf712c000 + 0x020));
646 data &= 0xffffffef;
647 mmio_write_32((0xf712c000 + 0x020), data);
648 data = mmio_read_32((0xf712c000 + 0x080));
649 data &= 0xffffdfff;
650 mmio_write_32((0xf712c000 + 0x080), data);
651 mmio_write_32((0xf712c000 + 0x270), 0x3);
652 mmio_write_32((0xf712c000 + 0x2f0), 0x3);
653 mmio_write_32((0xf712c000 + 0x370), 0x3);
654 mmio_write_32((0xf712c000 + 0x3f0), 0x3);
655 mmio_write_32((0xf712c000 + 0x048), 0xd0420900);
656
657 mmio_write_32((0xf7128000 + 0x040), 0x2001);
658 mmio_write_32((0xf712c000 + 0x004), 0x140f);
659 do {
660 data = mmio_read_32((0xf712c000 + 0x004));
661 } while (data & 1);
662 data = mmio_read_32((0xf712c000 + 0x008));
663 if (data & 0x7fe) {
664 WARN("failed to init lpddr3 rank0 dram phy\n");
665 return;
666 }
667 }
668
ddrc_common_init(int ddr800)669 static void ddrc_common_init(int ddr800)
670 {
671 unsigned int data;
672
673 mmio_write_32((0xf7120000 + 0x020), 0x1);
674 mmio_write_32((0xf7120000 + 0x100), 0x1700);
675 mmio_write_32((0xf7120000 + 0x104), 0x71040004);
676 mmio_write_32((0xf7121400 + 0x104), 0xf);
677 mmio_write_32((0xf7121800 + 0x104), 0xf);
678 mmio_write_32((0xf7121800 + 0x104), 0xf);
679 mmio_write_32((0xf7121c00 + 0x104), 0xf);
680 mmio_write_32((0xf7122000 + 0x104), 0xf);
681 mmio_write_32((0xf7128000 + 0x02c), 0x6);
682 mmio_write_32((0xf7128000 + 0x020), 0x1);
683 mmio_write_32((0xf7128000 + 0x028), 0x310201);
684 mmio_write_32((0xf712c000 + 0x1e4), 0xfe007600);
685 mmio_write_32((0xf7128000 + 0x01c), 0xaf001);
686
687
688 data = mmio_read_32((0xf7128000 + 0x280));
689 data |= 1 << 7;
690 mmio_write_32((0xf7128000 + 0x280), data);
691 mmio_write_32((0xf7128000 + 0x244), 0x3);
692
693 if (ddr800)
694 mmio_write_32((0xf7128000 + 0x240), 167 * 400000 / 1024);
695 else
696 mmio_write_32((0xf7128000 + 0x240), 167 * 533000 / 1024);
697
698 data = mmio_read_32((0xf712c000 + 0x080));
699 data &= 0xffff;
700 data |= 0x4002000;
701 mmio_write_32((0xf712c000 + 0x080), data);
702 mmio_write_32((0xf7128000 + 0x000), 0x0);
703 do {
704 data = mmio_read_32((0xf7128000 + 0x294));
705 } while (data & 1);
706 mmio_write_32((0xf7128000 + 0x000), 0x2);
707 }
708
709
dienum_det_and_rowcol_cfg(void)710 static int dienum_det_and_rowcol_cfg(void)
711 {
712 unsigned int data;
713
714 mmio_write_32((0xf7128000 + 0x210), 0x87);
715 mmio_write_32((0xf7128000 + 0x218), 0x10000);
716 mmio_write_32((0xf7128000 + 0x00c), 0x1);
717 do {
718 data = mmio_read_32((0xf7128000 + 0x00c));
719 } while (data & 1);
720 data = mmio_read_32((0xf7128000 + 0x4a8)) & 0xfc;
721 switch (data) {
722 case 0x18:
723 mmio_write_32((0xf7128000 + 0x060), 0x132);
724 mmio_write_32((0xf7128000 + 0x064), 0x132);
725 mmio_write_32((0xf7120000 + 0x100), 0x1600);
726 mmio_write_32((0xf7120000 + 0x104), 0x71040004);
727 break;
728 case 0x1c:
729 mmio_write_32((0xf7128000 + 0x060), 0x142);
730 mmio_write_32((0xf7128000 + 0x064), 0x142);
731 mmio_write_32((0xf7120000 + 0x100), 0x1700);
732 mmio_write_32((0xf7120000 + 0x104), 0x71040004);
733 break;
734 case 0x58:
735 mmio_write_32((0xf7128000 + 0x060), 0x133);
736 mmio_write_32((0xf7128000 + 0x064), 0x133);
737 mmio_write_32((0xf7120000 + 0x100), 0x1700);
738 mmio_write_32((0xf7120000 + 0x104), 0x71040004);
739 break;
740 default:
741 break;
742 }
743 if (!data)
744 return -22;
745 return 0;
746 }
747
detect_ddr_chip_info(void)748 static int detect_ddr_chip_info(void)
749 {
750 unsigned int data, mr5, mr6, mr7;
751
752 mmio_write_32((0xf7128000 + 0x210), 0x57);
753 mmio_write_32((0xf7128000 + 0x218), 0x10000);
754 mmio_write_32((0xf7128000 + 0x00c), 0x1);
755
756 do {
757 data = mmio_read_32((0xf7128000 + 0x00c));
758 } while (data & 1);
759
760 data = mmio_read_32((0xf7128000 + 0x4a8));
761 mr5 = data & 0xff;
762 switch (mr5) {
763 case 1:
764 tf_printf("INFO: " "Samsung DDR\n");
765 break;
766 case 6:
767 tf_printf("INFO: " "Hynix DDR\n");
768 break;
769 case 3:
770 tf_printf("INFO: " "Elpida DDR\n");
771 break;
772 default:
773 tf_printf("INFO: " "DDR from other vendors\n");
774 break;
775 }
776
777 mmio_write_32((0xf7128000 + 0x210), 0x67);
778 mmio_write_32((0xf7128000 + 0x218), 0x10000);
779 mmio_write_32((0xf7128000 + 0x00c), 0x1);
780 do {
781 data = mmio_read_32((0xf7128000 + 0x00c));
782 } while (data & 1);
783 data = mmio_read_32((0xf7128000 + 0x4a8));
784 mr6 = data & 0xff;
785 mmio_write_32((0xf7128000 + 0x210), 0x77);
786 mmio_write_32((0xf7128000 + 0x218), 0x10000);
787 mmio_write_32((0xf7128000 + 0x00c), 0x1);
788 do {
789 data = mmio_read_32((0xf7128000 + 0x00c));
790 } while (data & 1);
791 data = mmio_read_32((0xf7128000 + 0x4a8));
792 mr7 = data & 0xff;
793 data = mr5 + (mr6 << 8) + (mr7 << 16);
794 return data;
795 }
796
lpddr3_freq_init(int ddr800)797 int lpddr3_freq_init(int ddr800)
798 {
799 unsigned int data;
800
801 if (ddr800) {
802 set_ddrc_800mhz();
803 tf_printf("INFO: " "%s, set ddrc 800mhz\n", __func__);
804 } else {
805 set_ddrc_533mhz();
806 tf_printf("INFO: " "%s, set ddrc 533mhz\n", __func__);
807 }
808
809 data = cat_533mhz_800mhz();
810 if (data)
811 tf_printf("NOTICE: " "fail to set eye diagram\n");
812
813 mmio_write_32((0xf712c000 + 0x004), 0xf1);
814 if (ddr800)
815 mmio_write_32((0xf7128000 + 0x050), 0x100023);
816 else
817 mmio_write_32((0xf7128000 + 0x050), 0x100123);
818 mmio_write_32((0xf7128000 + 0x060), 0x133);
819 mmio_write_32((0xf7128000 + 0x064), 0x133);
820 mmio_write_32((0xf7128000 + 0x200), 0xa1000);
821 if (ddr800) {
822 mmio_write_32((0xf7128000 + 0x100), 0x755a9d12);
823 mmio_write_32((0xf7128000 + 0x104), 0x1753b055);
824 mmio_write_32((0xf7128000 + 0x108), 0x7401505f);
825 mmio_write_32((0xf7128000 + 0x10c), 0x578ca244);
826 mmio_write_32((0xf7128000 + 0x110), 0x10700000);
827 mmio_write_32((0xf7128000 + 0x114), 0x13141306);
828 } else {
829 mmio_write_32((0xf7128000 + 0x100), 0xb77b6718);
830 mmio_write_32((0xf7128000 + 0x104), 0x1e82a071);
831 mmio_write_32((0xf7128000 + 0x108), 0x9501c07e);
832 mmio_write_32((0xf7128000 + 0x10c), 0xaf50c255);
833 mmio_write_32((0xf7128000 + 0x110), 0x10b00000);
834 mmio_write_32((0xf7128000 + 0x114), 0x13181908);
835 }
836 mmio_write_32((0xf7128000 + 0x118), 0x44);
837 do {
838 data = mmio_read_32((0xf712c000 + 0x004));
839 } while (data & 1);
840
841 data = mmio_read_32((0xf712c000 + 0x008));
842 if (data & 0x7fe) {
843 tf_printf("NOTICE: " "fail to init ddr3 rank0\n");
844 return -14;
845 }
846 tf_printf("INFO: " "init ddr3 rank0\n");
847 ddrx_rdet();
848 ddrx_wdet();
849
850 data = mmio_read_32((0xf712c000 + 0x048));
851 data |= 1;
852 mmio_write_32((0xf712c000 + 0x048), data);
853 mmio_write_32((0xf712c000 + 0x004), 0x21);
854 do {
855 data = mmio_read_32((0xf712c000 + 0x004));
856 } while (data & 1);
857
858 data = mmio_read_32((0xf712c000 + 0x008));
859 if (data & 0x7fe)
860 tf_printf("NOTICE: " "ddr3 rank1 init failure\n");
861 else
862 tf_printf("INFO: " "ddr3 rank1 init pass\n");
863
864 data = mmio_read_32((0xf712c000 + 0x048));
865 data &= ~0xf;
866 mmio_write_32((0xf712c000 + 0x048), data);
867 return 0;
868 }
869
init_ddr(int ddr800)870 static void init_ddr(int ddr800)
871 {
872 unsigned int data;
873 int ret;
874
875
876 data = mmio_read_32((0xf7032000 + 0x030));
877 data |= 1;
878 mmio_write_32((0xf7032000 + 0x030), data);
879 data = mmio_read_32((0xf7032000 + 0x010));
880 data |= 1;
881 mmio_write_32((0xf7032000 + 0x010), data);
882
883 udelay(100);
884 do {
885 data = mmio_read_32((0xf7032000 + 0x030));
886 data &= 3 << 28;
887 } while (data != (3 << 28));
888 do {
889 data = mmio_read_32((0xf7032000 + 0x010));
890 data &= 3 << 28;
891 } while (data != (3 << 28));
892
893 ret = lpddr3_freq_init(ddr800);
894 if (ret)
895 return;
896 }
897
init_ddrc_qos(void)898 static void init_ddrc_qos(void)
899 {
900 unsigned int port, data;
901
902 mmio_write_32((0xf7124000 + 0x088), 1);
903
904
905 port = 0;
906 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210);
907 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x11111111);
908 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x11111111);
909 mmio_write_32((0xf7120000 + 0x400 + 0 * 0x10), 0x001d0007);
910
911
912 for (port = 3; port <= 4; port++) {
913 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210);
914 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x77777777);
915 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x77777777);
916 }
917
918
919 port = 1;
920 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000);
921 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567);
922 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567);
923
924
925 mmio_write_32((0xf7124000 + 0x1f0), 0);
926 mmio_write_32((0xf7124000 + 0x0bc), 0x3020100);
927 mmio_write_32((0xf7124000 + 0x0d0), 0x3020100);
928 mmio_write_32((0xf7124000 + 0x1f4), 0x01000100);
929 mmio_write_32((0xf7124000 + 0x08c + 0 * 4), 0xd0670402);
930 mmio_write_32((0xf7124000 + 0x068 + 0 * 4), 0x31);
931 mmio_write_32((0xf7124000 + 0x000), 0x7);
932
933 data = mmio_read_32((0xf7124000 + 0x09c));
934 data &= ~0xff0000;
935 data |= 0x400000;
936 mmio_write_32((0xf7124000 + 0x09c), data);
937 data = mmio_read_32((0xf7124000 + 0x0ac));
938 data &= ~0xff0000;
939 data |= 0x400000;
940 mmio_write_32((0xf7124000 + 0x0ac), data);
941 port = 2;
942 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000);
943 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567);
944 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567);
945
946
947 mmio_write_32((0xf7124000 + 0x09c), 0xff7fff);
948 mmio_write_32((0xf7124000 + 0x0a0), 0xff);
949 mmio_write_32((0xf7124000 + 0x0ac), 0xff7fff);
950 mmio_write_32((0xf7124000 + 0x0b0), 0xff);
951 mmio_write_32((0xf7124000 + 0x0bc), 0x3020100);
952 mmio_write_32((0xf7124000 + 0x0d0), 0x3020100);
953 }
954
init_mmc0_pll(void)955 static void init_mmc0_pll(void)
956 {
957 unsigned int data;
958
959 data = hi6553_read_8(0x084);
960 data |= 0x7;
961 hi6553_write_8(0x084, data);
962
963 /* select SYSPLL as the source of MMC0 */
964 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
965 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21);
966 do {
967 data = mmio_read_32(PERI_SC_CLK_SEL0);
968 } while (!(data & (1 << 5)));
969 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
970 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29);
971 do {
972 data = mmio_read_32(PERI_SC_CLK_SEL0);
973 } while (data & (1 << 13));
974
975 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0));
976 do {
977 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
978 } while (!(data & (1 << 0)));
979
980 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
981 data |= 1 << 1;
982 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
983
984 do {
985 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb);
986 data = mmio_read_32(PERI_SC_CLKCFG8BIT1);
987 } while ((data & 0xb) != 0xb);
988 }
989
reset_mmc0_clk(void)990 static void reset_mmc0_clk(void)
991 {
992 unsigned int data;
993
994 /* disable mmc0 bus clock */
995 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
996 do {
997 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
998 } while (data & PERI_CLK0_MMC0);
999 /* enable mmc0 bus clock */
1000 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
1001 do {
1002 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
1003 } while (!(data & PERI_CLK0_MMC0));
1004 /* reset mmc0 clock domain */
1005 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
1006
1007 /* bypass mmc0 clock phase */
1008 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
1009 data |= 3;
1010 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
1011
1012 /* disable low power */
1013 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
1014 data |= 1 << 3;
1015 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
1016 do {
1017 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
1018 } while (!(data & PERI_RST0_MMC0));
1019
1020 /* unreset mmc0 clock domain */
1021 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
1022 do {
1023 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
1024 } while (data & PERI_RST0_MMC0);
1025 }
1026
init_media_clk(void)1027 static void init_media_clk(void)
1028 {
1029 unsigned int data, value;
1030
1031 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
1032 data |= 1;
1033 mmio_write_32(PMCTRL_MEDPLLCTRL, data);
1034
1035 for (;;) {
1036 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
1037 value = 1 << 28;
1038 if ((data & value) == value)
1039 break;
1040 }
1041
1042 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
1043 data = 1 << 10;
1044 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
1045 }
1046
init_mmc1_pll(void)1047 static void init_mmc1_pll(void)
1048 {
1049 uint32_t data;
1050
1051 /* select SYSPLL as the source of MMC1 */
1052 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
1053 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27);
1054 do {
1055 data = mmio_read_32(PERI_SC_CLK_SEL0);
1056 } while (!(data & (1 << 11)));
1057 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
1058 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30);
1059 do {
1060 data = mmio_read_32(PERI_SC_CLK_SEL0);
1061 } while (data & (1 << 14));
1062
1063 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1));
1064 do {
1065 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
1066 } while (!(data & (1 << 1)));
1067
1068 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
1069 data |= 1 << 2;
1070 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
1071
1072 do {
1073 /* 1.2GHz / 50 = 24MHz */
1074 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7));
1075 data = mmio_read_32(PERI_SC_CLKCFG8BIT2);
1076 } while ((data & 0x31) != 0x31);
1077 }
1078
reset_mmc1_clk(void)1079 static void reset_mmc1_clk(void)
1080 {
1081 unsigned int data;
1082
1083 /* disable mmc1 bus clock */
1084 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1);
1085 do {
1086 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
1087 } while (data & PERI_CLK0_MMC1);
1088 /* enable mmc1 bus clock */
1089 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1);
1090 do {
1091 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
1092 } while (!(data & PERI_CLK0_MMC1));
1093 /* reset mmc1 clock domain */
1094 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1);
1095
1096 /* bypass mmc1 clock phase */
1097 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
1098 data |= 3 << 2;
1099 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
1100
1101 /* disable low power */
1102 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
1103 data |= 1 << 4;
1104 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
1105 do {
1106 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
1107 } while (!(data & PERI_RST0_MMC1));
1108
1109 /* unreset mmc0 clock domain */
1110 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1);
1111 do {
1112 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
1113 } while (data & PERI_RST0_MMC1);
1114 }
1115
ddr_phy_reset(void)1116 static void ddr_phy_reset(void)
1117 {
1118 mmio_write_32(0xf7030340, 0xa000);
1119 mmio_write_32(0xf7030344, 0xa000);
1120 }
1121
hi6220_pll_init(void)1122 void hi6220_pll_init(void)
1123 {
1124 uint32_t data;
1125
1126 init_pll();
1127 init_freq();
1128
1129 /*
1130 * Init DDR with 533MHz. Otherwise, DDR initialization
1131 * may fail on 800MHz on some boards.
1132 */
1133 ddr_phy_reset();
1134 init_ddr(0);
1135 /* Init DDR with 800MHz. */
1136 ddr_phy_reset();
1137 init_ddr(1);
1138
1139
1140 ddrc_common_init(1);
1141 dienum_det_and_rowcol_cfg();
1142 detect_ddr_chip_info();
1143
1144 data = mmio_read_32(0xf7032000 + 0x010);
1145 data &= ~0x1;
1146 mmio_write_32(0xf7032000 + 0x010, data);
1147 data = mmio_read_32(0xf7032000 + 0x010);
1148
1149 /*
1150 * Test memory access. Do not use address 0x0 because the compiler
1151 * may assume it is not a valid address and generate incorrect code
1152 * (GCC 4.9.1 without -fno-delete-null-pointer-checks for instance).
1153 */
1154 mmio_write_32(0x4, 0xa5a55a5a);
1155 INFO("ddr test value:0x%x\n", mmio_read_32(0x4));
1156 init_ddrc_qos();
1157
1158 init_mmc0_pll();
1159 reset_mmc0_clk();
1160 init_media_clk();
1161
1162 dsb();
1163
1164 init_mmc1_pll();
1165 reset_mmc1_clk();
1166 }
1167