1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*!
21 **************************************************************************
22 * \file ih264d_utils.c
23 *
24 * \brief
25 * Contains routines that handle of start and end of pic processing
26 *
27 * \date
28 * 19/12/2002
29 *
30 * \author AI
31 **************************************************************************
32 */
33
34 #include <string.h>
35 #include "ih264_typedefs.h"
36 #include "ithread.h"
37 #include "ih264d_deblocking.h"
38 #include "ih264d_parse_slice.h"
39 #include "ih264d_parse_cavlc.h"
40 #include "ih264d_dpb_manager.h"
41 #include "ih264d_defs.h"
42 #include "ih264d_structs.h"
43 #include "ih264d_mem_request.h"
44 #include "ih264_typedefs.h"
45 #include "ih264_macros.h"
46 #include "ih264_platform_macros.h"
47 #include "ih264d_tables.h"
48 #include "ih264d_debug.h"
49 #include "ih264d_mb_utils.h"
50 #include "ih264d_error_handler.h"
51 #include "ih264d_dpb_manager.h"
52 #include "ih264d_utils.h"
53 #include "ih264d_defs.h"
54 #include "ih264d_tables.h"
55 #include "ih264d_inter_pred.h"
56 #include "ih264d_dpb_manager.h"
57 #include "iv.h"
58 #include "ivd.h"
59 #include "ih264d_format_conv.h"
60 #include "ih264_error.h"
61 #include "ih264_disp_mgr.h"
62 #include "ih264_buf_mgr.h"
63 #include "ih264d_utils.h"
64
65 /*!
66 **************************************************************************
67 * \if Function name : ih264d_is_end_of_pic \endif
68 *
69 * \brief
70 * Determines whether current slice is first slice of a new picture as
71 * defined in 7.4.1.2.4 of 14496-10.
72 *
73 * \return
74 * Return 1 if current slice is first slice of a new picture
75 * Otherwise it returns 0
76 **************************************************************************
77 */
ih264d_is_end_of_pic(UWORD16 u2_frame_num,UWORD8 u1_nal_ref_idc,pocstruct_t * ps_cur_poc,pocstruct_t * ps_prev_poc,dec_slice_params_t * ps_prev_slice,UWORD8 u1_pic_order_cnt_type,UWORD8 u1_nal_unit_type,UWORD32 u4_idr_pic_id,UWORD8 u1_field_pic_flag,UWORD8 u1_bottom_field_flag)78 UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num,
79 UWORD8 u1_nal_ref_idc,
80 pocstruct_t *ps_cur_poc,
81 pocstruct_t *ps_prev_poc,
82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/
83 UWORD8 u1_pic_order_cnt_type,
84 UWORD8 u1_nal_unit_type,
85 UWORD32 u4_idr_pic_id,
86 UWORD8 u1_field_pic_flag,
87 UWORD8 u1_bottom_field_flag)
88 {
89 WORD8 i1_is_end_of_pic;
90 WORD8 a, b, c, d, e, f, g, h;
91
92 a = b = c = d = e = f = g = h = 0;
93 a = (ps_prev_slice->u2_frame_num != u2_frame_num);
94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag);
95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag)
96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag);
97 d =
98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0)
99 || (u1_nal_ref_idc != 0
100 && ps_prev_slice->u1_nal_ref_idc
101 == 0);
102 if(!a)
103 {
104 if((u1_pic_order_cnt_type == 0)
105 && (ps_prev_slice->u1_pic_order_cnt_type == 0))
106 {
107 e =
108 ((ps_cur_poc->i4_pic_order_cnt_lsb
109 != ps_prev_poc->i4_pic_order_cnt_lsb)
110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom
111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom));
112 }
113
114 if((u1_pic_order_cnt_type == 1)
115 && (ps_prev_slice->u1_pic_order_cnt_type == 1))
116 {
117 f =
118 ((ps_cur_poc->i4_delta_pic_order_cnt[0]
119 != ps_prev_poc->i4_delta_pic_order_cnt[0])
120 || (ps_cur_poc->i4_delta_pic_order_cnt[1]
121 != ps_prev_poc->i4_delta_pic_order_cnt[1]));
122 }
123 }
124
125 if((u1_nal_unit_type == IDR_SLICE_NAL)
126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL))
127 {
128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id);
129 }
130
131 if((u1_nal_unit_type == IDR_SLICE_NAL)
132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL))
133 {
134 h = 1;
135 }
136 i1_is_end_of_pic = a + b + c + d + e + f + g + h;
137 return (i1_is_end_of_pic);
138 }
139
140 /*!
141 **************************************************************************
142 * \if Function name : ih264d_decode_pic_order_cnt \endif
143 *
144 * \brief
145 * Calculates picture order count of picture.
146 *
147 * \return
148 * Returns the pic order count of the picture to which current
149 * Slice belongs.
150 *
151 **************************************************************************
152 */
ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice,UWORD32 u2_frame_num,pocstruct_t * ps_prev_poc,pocstruct_t * ps_cur_poc,dec_slice_params_t * ps_cur_slice,dec_pic_params_t * ps_pps,UWORD8 u1_nal_ref_idc,UWORD8 u1_bottom_field_flag,UWORD8 u1_field_pic_flag,WORD32 * pi4_poc)153 WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice,
154 UWORD32 u2_frame_num,
155 pocstruct_t *ps_prev_poc,
156 pocstruct_t *ps_cur_poc,
157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/
158 dec_pic_params_t * ps_pps,
159 UWORD8 u1_nal_ref_idc,
160 UWORD8 u1_bottom_field_flag,
161 UWORD8 u1_field_pic_flag,
162 WORD32 *pi4_poc)
163 {
164 WORD16 i1_pic_msb;
165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0;
166 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
167 WORD32 i4_prev_frame_num_ofst;
168
169 switch(ps_seq->u1_pic_order_cnt_type)
170 {
171 case 0:
172 /* POC TYPE 0 */
173 if(u1_is_idr_slice)
174 {
175 ps_prev_poc->i4_pic_order_cnt_msb = 0;
176 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
177 }
178 if(ps_prev_poc->u1_mmco_equalto5)
179 {
180 if(ps_prev_poc->u1_bot_field != 1)
181 {
182 ps_prev_poc->i4_pic_order_cnt_msb = 0;
183 ps_prev_poc->i4_pic_order_cnt_lsb =
184 ps_prev_poc->i4_top_field_order_count;
185 }
186 else
187 {
188 ps_prev_poc->i4_pic_order_cnt_msb = 0;
189 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
190 }
191 }
192
193 if((ps_cur_poc->i4_pic_order_cnt_lsb
194 < ps_prev_poc->i4_pic_order_cnt_lsb)
195 && ((ps_prev_poc->i4_pic_order_cnt_lsb
196 - ps_cur_poc->i4_pic_order_cnt_lsb)
197 >= (ps_seq->i4_max_pic_order_cntLsb
198 >> 1)))
199 {
200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb
201 + ps_seq->i4_max_pic_order_cntLsb;
202 }
203 else if((ps_cur_poc->i4_pic_order_cnt_lsb
204 > ps_prev_poc->i4_pic_order_cnt_lsb)
205 && ((ps_cur_poc->i4_pic_order_cnt_lsb
206 - ps_prev_poc->i4_pic_order_cnt_lsb)
207 >= (ps_seq->i4_max_pic_order_cntLsb
208 >> 1)))
209 {
210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb
211 - ps_seq->i4_max_pic_order_cntLsb;
212 }
213 else
214 {
215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb;
216 }
217
218 if(!u1_field_pic_flag || !u1_bottom_field_flag)
219 i4_top_field_order_cnt = i1_pic_msb
220 + ps_cur_poc->i4_pic_order_cnt_lsb;
221
222 if(!u1_field_pic_flag)
223 {
224 i4_bottom_field_order_cnt = i4_top_field_order_cnt
225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom;
226 }
227 else if(u1_bottom_field_flag)
228 {
229 i4_bottom_field_order_cnt = i1_pic_msb
230 + ps_cur_poc->i4_pic_order_cnt_lsb;
231 }
232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb;
233 break;
234
235 case 1:
236 {
237 /* POC TYPE 1 */
238 UWORD8 i;
239 WORD32 prev_frame_num;
240 WORD32 frame_num_ofst;
241 WORD32 abs_frm_num;
242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle;
243 WORD32 expected_delta_poc_cycle;
244 WORD32 expected_poc;
245
246 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
247 if(!u1_is_idr_slice)
248 {
249 if(ps_cur_slice->u1_mmco_equalto5)
250 {
251 prev_frame_num = 0;
252 i4_prev_frame_num_ofst = 0;
253 }
254 else
255 {
256 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
257 }
258 }
259 else
260 i4_prev_frame_num_ofst = 0;
261
262 /* 1. Derivation for FrameNumOffset */
263 if(u1_is_idr_slice)
264 {
265 frame_num_ofst = 0;
266 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
267 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
268 }
269 else if(prev_frame_num > ((WORD32)u2_frame_num))
270 {
271 frame_num_ofst = i4_prev_frame_num_ofst
272 + ps_seq->u2_u4_max_pic_num_minus1 + 1;
273 }
274 else
275 frame_num_ofst = i4_prev_frame_num_ofst;
276
277 /* 2. Derivation for absFrameNum */
278 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle)
279 abs_frm_num = frame_num_ofst + u2_frame_num;
280 else
281 abs_frm_num = 0;
282 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0))
283 abs_frm_num = abs_frm_num - 1;
284
285 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */
286 expected_delta_poc_cycle = 0;
287 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle;
288 i++)
289 {
290 expected_delta_poc_cycle +=
291 ps_seq->i4_ofst_for_ref_frame[i];
292 }
293
294 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and
295 frame_num_in_poc_cycle are derived as : */
296 /* 5. expectedPicOrderCnt is derived as : */
297 if(abs_frm_num > 0)
298 {
299 poc_cycle_cnt =
300 DIV((abs_frm_num - 1),
301 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
302 frame_num_in_poc_cycle =
303 MOD((abs_frm_num - 1),
304 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
305
306 expected_poc = poc_cycle_cnt
307 * expected_delta_poc_cycle;
308 for(i = 0; i <= frame_num_in_poc_cycle; i++)
309 {
310 expected_poc = expected_poc
311 + ps_seq->i4_ofst_for_ref_frame[i];
312 }
313 }
314 else
315 expected_poc = 0;
316
317 if(u1_nal_ref_idc == 0)
318 {
319 expected_poc = expected_poc
320 + ps_seq->i4_ofst_for_non_ref_pic;
321 }
322
323 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
324 if(!u1_field_pic_flag)
325 {
326 i4_top_field_order_cnt = expected_poc
327 + ps_cur_poc->i4_delta_pic_order_cnt[0];
328 i4_bottom_field_order_cnt = i4_top_field_order_cnt
329 + ps_seq->i4_ofst_for_top_to_bottom_field
330 + ps_cur_poc->i4_delta_pic_order_cnt[1];
331 }
332 else if(!u1_bottom_field_flag)
333 {
334 i4_top_field_order_cnt = expected_poc
335 + ps_cur_poc->i4_delta_pic_order_cnt[0];
336 }
337 else
338 {
339 i4_bottom_field_order_cnt = expected_poc
340 + ps_seq->i4_ofst_for_top_to_bottom_field
341 + ps_cur_poc->i4_delta_pic_order_cnt[0];
342 }
343 /* Copy the current POC info into Previous POC structure */
344 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
345 }
346
347 break;
348 case 2:
349 {
350 /* POC TYPE 2 */
351 WORD32 prev_frame_num;
352 WORD32 frame_num_ofst;
353 WORD32 tmp_poc;
354
355 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
356 if(!u1_is_idr_slice)
357 {
358 if(ps_cur_slice->u1_mmco_equalto5)
359 {
360 prev_frame_num = 0;
361 i4_prev_frame_num_ofst = 0;
362 }
363 else
364 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
365 }
366 else
367 i4_prev_frame_num_ofst = 0;
368
369 /* 1. Derivation for FrameNumOffset */
370 if(u1_is_idr_slice)
371 {
372 frame_num_ofst = 0;
373 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
374 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
375 }
376 else if(prev_frame_num > ((WORD32)u2_frame_num))
377 {
378 frame_num_ofst = i4_prev_frame_num_ofst
379 + ps_seq->u2_u4_max_pic_num_minus1 + 1;
380 }
381 else
382 frame_num_ofst = i4_prev_frame_num_ofst;
383
384 /* 2. Derivation for tempPicOrderCnt */
385 if(u1_is_idr_slice)
386 tmp_poc = 0;
387 else if(u1_nal_ref_idc == 0)
388 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1)
389 - 1;
390 else
391 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1);
392
393 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
394 if(!u1_field_pic_flag)
395 {
396 i4_top_field_order_cnt = tmp_poc;
397 i4_bottom_field_order_cnt = tmp_poc;
398 }
399 else if(!u1_bottom_field_flag)
400 i4_top_field_order_cnt = tmp_poc;
401 else
402 i4_bottom_field_order_cnt = tmp_poc;
403
404 /* Copy the current POC info into Previous POC structure */
405 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst;
406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
407 }
408 break;
409 default:
410 return ERROR_INV_POC_TYPE_T;
411 break;
412 }
413
414 if(!u1_field_pic_flag) // or a complementary field pair
415 {
416 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt);
417 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
418 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
419 }
420 else if(!u1_bottom_field_flag)
421 {
422 *pi4_poc = i4_top_field_order_cnt;
423 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
424 }
425 else
426 {
427 *pi4_poc = i4_bottom_field_order_cnt;
428 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
429 }
430
431 ps_pps->i4_avg_poc = *pi4_poc;
432
433 return OK;
434 }
435
436 /*!
437 **************************************************************************
438 * \if Function name : ih264d_end_of_pic_processing \endif
439 *
440 * \brief
441 * Performs the end of picture processing.
442 *
443 * It performs deblocking on the current picture and sets the i4_status of
444 * current picture as decoded.
445 *
446 * \return
447 * 0 on Success and Error code otherwise.
448 **************************************************************************
449 */
ih264d_end_of_pic_processing(dec_struct_t * ps_dec)450 WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec)
451 {
452 UWORD8 u1_pic_type, u1_nal_ref_idc;
453 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice;
454
455 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL
456 unit of a particular picture, it shall be equal to 0 for all slice and
457 slice data partition NAL units of the picture. nal_ref_idc greater
458 than 0 indicates that the content of the NAL unit belongs to a decoded
459 picture that is stored and marked for use as a reference picture in the
460 decoded picture buffer. */
461
462 /* 1. Do MMCO
463 2. Add Cur Pic to list of reference pics.
464 */
465
466 /* Call MMCO */
467 u1_pic_type = 0;
468 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc;
469
470 if(u1_nal_ref_idc)
471 {
472 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
473 {
474 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0)
475 {
476 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
477 /* ignore DPB errors */
478 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
479 ps_dec->ps_cur_pic,
480 ps_dec->u1_pic_buf_id,
481 ps_cur_slice->u2_frame_num);
482 }
483 else
484 {
485 /* Equivalent of inserting a pic directly as longterm Pic */
486
487 {
488 /* ignore DPB errors */
489 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
490 ps_dec->ps_cur_pic,
491 ps_dec->u1_pic_buf_id,
492 ps_cur_slice->u2_frame_num);
493
494 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */
495 ih264d_delete_st_node_or_make_lt(
496 ps_dec->ps_dpb_mgr,
497 ps_cur_slice->u2_frame_num, 0,
498 ps_cur_slice->u1_field_pic_flag);
499
500 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1;
501 }
502 }
503 }
504 else
505 {
506
507 {
508 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num;
509
510 /* ignore DPB errors */
511 ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr,
512 ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num,
513 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1),
514 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic,
515 ps_dec->u1_pic_buf_id,
516 ps_cur_slice->u1_field_pic_flag,
517 ps_dec->e_dec_status);
518
519
520 }
521 }
522 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr);
523 }
524
525 if(ps_cur_slice->u1_field_pic_flag)
526 {
527 if(ps_cur_slice->u1_bottom_field_flag)
528 {
529 if(u1_nal_ref_idc)
530 u1_pic_type = u1_pic_type | BOT_REF;
531 u1_pic_type = u1_pic_type | BOT_FLD;
532 }
533 else
534 {
535 if(u1_nal_ref_idc)
536 u1_pic_type = u1_pic_type | TOP_REF;
537 u1_pic_type = u1_pic_type | TOP_FLD;
538 }
539 }
540 else
541 u1_pic_type = TOP_REF | BOT_REF;
542 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type;
543
544
545 if(ps_cur_slice->u1_field_pic_flag)
546 {
547 H264_DEC_DEBUG_PRINT("Toggling secondField\n");
548 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field;
549 }
550
551 return OK;
552 }
553
554 /*****************************************************************************/
555 /* */
556 /* Function Name : init_dpb_size */
557 /* */
558 /* Description : This function calculates the DBP i4_size in frames */
559 /* Inputs : ps_seq - current sequence params */
560 /* */
561 /* Globals : None */
562 /* */
563 /* Outputs : None */
564 /* */
565 /* Returns : DPB in frames */
566 /* */
567 /* Issues : None */
568 /* */
569 /* Revision History: */
570 /* */
571 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
572 /* 28 04 2005 NS Draft */
573 /* */
574 /*****************************************************************************/
ih264d_get_dpb_size(dec_seq_params_t * ps_seq)575 WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq)
576 {
577 WORD32 i4_size;
578 UWORD8 u1_level_idc;
579
580 u1_level_idc = ps_seq->u1_level_idc;
581
582 switch(u1_level_idc)
583 {
584 case 10:
585 i4_size = 152064;
586 break;
587 case 11:
588 i4_size = 345600;
589 break;
590 case 12:
591 i4_size = 912384;
592 break;
593 case 13:
594 i4_size = 912384;
595 break;
596 case 20:
597 i4_size = 912384;
598 break;
599 case 21:
600 i4_size = 1824768;
601 break;
602 case 22:
603 i4_size = 3110400;
604 break;
605 case 30:
606 i4_size = 3110400;
607 break;
608 case 31:
609 i4_size = 6912000;
610 break;
611 case 32:
612 i4_size = 7864320;
613 break;
614 case 40:
615 i4_size = 12582912;
616 break;
617 case 41:
618 i4_size = 12582912;
619 break;
620 case 42:
621 i4_size = 12582912;
622 break;
623 case 50:
624 i4_size = 42393600;
625 break;
626 case 51:
627 i4_size = 70778880;
628 break;
629 case 52:
630 i4_size = 70778880;
631 break;
632 default:
633 i4_size = 70778880;
634 break;
635 }
636
637 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag)));
638 i4_size /= 384;
639 i4_size = MIN(i4_size, 16);
640 i4_size = MAX(i4_size, 1);
641 return (i4_size);
642 }
643
644 /***************************************************************************/
645 /* If change in Level or the required PicBuffers i4_size is more than the */
646 /* current one FREE the current PicBuffers and allocate affresh */
647 /***************************************************************************/
ih264d_is_sps_changed(prev_seq_params_t * ps_prv,dec_seq_params_t * ps_cur)648 UWORD8 ih264d_is_sps_changed(prev_seq_params_t * ps_prv,
649 dec_seq_params_t * ps_cur)
650 {
651
652 if((ps_prv->u2_frm_wd_in_mbs != ps_cur->u2_frm_wd_in_mbs)
653 || (ps_prv->u1_level_idc != ps_cur->u1_level_idc)
654 || (ps_prv->u1_profile_idc != ps_cur->u1_profile_idc)
655 || (ps_cur->u2_frm_ht_in_mbs != ps_prv->u2_frm_ht_in_mbs)
656 || (ps_cur->u1_frame_mbs_only_flag
657 != ps_prv->u1_frame_mbs_only_flag)
658 || (ps_cur->u1_direct_8x8_inference_flag
659 != ps_prv->u1_direct_8x8_inference_flag))
660 return 1;
661
662 return 0;
663 }
664
665 /**************************************************************************/
666 /* This function initialises the value of ps_dec->u1_recon_mb_grp */
667 /* ps_dec->u1_recon_mb_grp must satisfy the following criteria */
668 /* - multiple of 2 (required for N/2 parse-mvpred design) */
669 /* - multiple of 4 (if it is not a frame_mbs_only sequence), */
670 /* in this case N/2 itself needs to be even for mbpair processing */
671 /* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */
672 /* should make a row to ensure proper MvTop transferring) */
673 /**************************************************************************/
ih264d_init_dec_mb_grp(dec_struct_t * ps_dec)674 WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec)
675 {
676 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps;
677 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag;
678
679 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag;
680
681 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1;
682
683 if(!ps_dec->u1_recon_mb_grp)
684 {
685 return ERROR_MB_GROUP_ASSGN_T;
686 }
687
688 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp;
689
690 return OK;
691 }
692
693
694 /*!
695 **************************************************************************
696 * \if Function name : ih264d_init_pic \endif
697 *
698 * \brief
699 * Initializes the picture.
700 *
701 * \return
702 * 0 on Success and Error code otherwise
703 *
704 * \note
705 * This function is called when first slice of the
706 * NON -IDR picture is encountered.
707 **************************************************************************
708 */
ih264d_init_pic(dec_struct_t * ps_dec,UWORD16 u2_frame_num,WORD32 i4_poc,dec_pic_params_t * ps_pps)709 WORD32 ih264d_init_pic(dec_struct_t *ps_dec,
710 UWORD16 u2_frame_num,
711 WORD32 i4_poc,
712 dec_pic_params_t *ps_pps)
713 {
714 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
715 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params;
716 WORD32 i4_pic_bufs;
717 WORD32 ret;
718
719 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num;
720 ps_dec->ps_cur_slice->i4_poc = i4_poc;
721 ps_dec->ps_cur_pps = ps_pps;
722 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec;
723
724 ps_dec->ps_cur_sps = ps_seq;
725 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1
726 + 1;
727
728 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht;
729 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd;
730 ps_dec->i4_pic_type = -1;
731 ps_dec->i4_frametype = -1;
732 ps_dec->i4_content_type = -1;
733
734 /*--------------------------------------------------------------------*/
735 /* Get the value of MaxMbAddress and frmheight in Mbs */
736 /*--------------------------------------------------------------------*/
737 ps_seq->u2_max_mb_addr =
738 (ps_seq->u2_frm_wd_in_mbs
739 * (ps_dec->u2_pic_ht
740 >> (4
741 + ps_dec->ps_cur_slice->u1_field_pic_flag)))
742 - 1;
743 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht
744 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag));
745
746 /***************************************************************************/
747 /* If change in Level or the required PicBuffers i4_size is more than the */
748 /* current one FREE the current PicBuffers and allocate affresh */
749 /***************************************************************************/
750 if(!ps_dec->u1_init_dec_flag
751 || ih264d_is_sps_changed(ps_prev_seq_params, ps_seq))
752 {
753 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq);
754
755 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering;
756 if((1 == ps_seq->u1_vui_parameters_present_flag) &&
757 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag))
758 {
759 if(ps_seq->u1_frame_mbs_only_flag == 1)
760 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1;
761 else
762 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2;
763 }
764
765 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
766 ps_dec->i4_display_delay = 0;
767
768 if(ps_dec->u4_share_disp_buf == 0)
769 {
770 if(ps_seq->u1_frame_mbs_only_flag == 1)
771 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1;
772 else
773 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2;
774 }
775 else
776 {
777 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs;
778 }
779
780 /* Ensure at least two buffers are allocated */
781 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2);
782
783 if(ps_dec->u4_share_disp_buf == 0)
784 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs,
785 (H264_MAX_REF_PICS * 2));
786
787 ps_dec->u1_max_dec_frame_buffering = MIN(
788 ps_dec->u1_max_dec_frame_buffering,
789 ps_dec->u1_pic_bufs);
790
791 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/
792 if(ps_dec->u1_init_dec_flag)
793 {
794 ih264d_release_pics_in_dpb((void *)ps_dec,
795 ps_dec->u1_pic_bufs);
796 ih264d_release_display_bufs(ps_dec);
797 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
798 }
799
800 /*********************************************************************/
801 /* Configuring decoder parameters based on level and then */
802 /* fresh pointer initialisation in decoder scratch and state buffers */
803 /*********************************************************************/
804 if(!ps_dec->u1_init_dec_flag ||
805 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0)))
806 {
807 ret = ih264d_init_dec_mb_grp(ps_dec);
808 if(ret != OK)
809 return ret;
810 }
811
812 ret = ih264d_allocate_dynamic_bufs(ps_dec);
813 if(ret != OK)
814 {
815 /* Free any dynamic buffers that are allocated */
816 ih264d_free_dynamic_bufs(ps_dec);
817 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED;
818 return IVD_MEM_ALLOC_FAILED;
819 }
820
821 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs,
822 ps_dec);
823 if(ret != OK)
824 return ret;
825
826
827
828 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd,
829 ps_dec->u2_pic_ht);
830 if(ret != OK)
831 return ret;
832
833 /* In shared mode, set all of them as used by display */
834 if(ps_dec->u4_share_disp_buf == 1)
835 {
836 WORD32 i;
837
838 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
839 {
840 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
841 BUF_MGR_IO);
842 }
843 }
844
845 ps_dec->u1_init_dec_flag = 1;
846 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs;
847 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc;
848 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc;
849 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs;
850 ps_prev_seq_params->u1_frame_mbs_only_flag =
851 ps_seq->u1_frame_mbs_only_flag;
852 ps_prev_seq_params->u1_direct_8x8_inference_flag =
853 ps_seq->u1_direct_8x8_inference_flag;
854
855 ps_dec->i4_cur_display_seq = 0;
856 ps_dec->i4_prev_max_display_seq = 0;
857 ps_dec->i4_max_poc = 0;
858
859 {
860 /* 0th entry of CtxtIncMbMap will be always be containing default values
861 for CABAC context representing MB not available */
862 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1;
863 UWORD8 *pu1_temp;
864 WORD8 i;
865 p_DefCtxt->u1_mb_type = CAB_SKIP;
866
867 p_DefCtxt->u1_cbp = 0x0f;
868 p_DefCtxt->u1_intra_chroma_pred_mode = 0;
869
870 p_DefCtxt->u1_yuv_dc_csbp = 0x7;
871
872 p_DefCtxt->u1_transform8x8_ctxt = 0;
873
874 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx;
875 for(i = 0; i < 4; i++, pu1_temp++)
876 (*pu1_temp) = 0;
877 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv;
878 for(i = 0; i < 16; i++, pu1_temp++)
879 (*pu1_temp) = 0;
880 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt;
881 }
882
883 }
884 /* reset DBP commands read u4_flag */
885 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0;
886
887 return OK;
888 }
889
890 /*****************************************************************************/
891 /* */
892 /* Function Name : ih264d_get_next_display_field */
893 /* */
894 /* Description : Application calls this module to get the next field */
895 /* to be displayed */
896 /* */
897 /* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */
898 /* 2. IH264DEC_DispUnit Pointer to the display struct */
899 /* */
900 /* Globals : */
901 /* */
902 /* */
903 /* Processing : None */
904 /* Outputs : None */
905 /* Returns : None */
906 /* Issues : None */
907 /* */
908 /* Revision History: */
909 /* */
910 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
911 /* 27 05 2005 Ittiam Draft */
912 /* */
913 /*****************************************************************************/
914
ih264d_get_next_display_field(dec_struct_t * ps_dec,ivd_out_bufdesc_t * ps_out_buffer,ivd_get_display_frame_op_t * pv_disp_op)915 WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec,
916 ivd_out_bufdesc_t *ps_out_buffer,
917 ivd_get_display_frame_op_t *pv_disp_op)
918 {
919 pic_buffer_t *pic_buf;
920
921 UWORD8 i1_cur_fld;
922 WORD32 u4_api_ret = -1;
923 WORD32 i4_disp_buf_id;
924 iv_yuv_buf_t *ps_op_frm;
925
926
927
928 ps_op_frm = &(ps_dec->s_disp_frame_info);
929 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
930 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get(
931 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id);
932 ps_dec->u4_num_fld_in_frm = 0;
933 u4_api_ret = -1;
934 pv_disp_op->u4_ts = -1;
935 pv_disp_op->e_output_format = ps_dec->u1_chroma_format;
936
937 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0];
938 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1];
939 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2];
940 if(pic_buf != NULL)
941 {
942 pv_disp_op->e4_fld_type = 0;
943 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id;
944
945 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1;
946 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1;
947 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width;
948
949 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1;
950
951 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y;
952 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv;
953
954 /* ! */
955 pv_disp_op->u4_ts = pic_buf->u4_ts;
956
957 /* set the start of the Y, U and V buffer pointer for display */
958 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y;
959 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv;
960 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv;
961 ps_dec->u4_num_fld_in_frm++;
962 ps_dec->u4_num_fld_in_frm++;
963 u4_api_ret = 0;
964
965 if(pic_buf->u1_picturetype == 0)
966 pv_disp_op->u4_progressive_frame_flag = 1;
967 else
968 pv_disp_op->u4_progressive_frame_flag = 0;
969
970 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
971 pv_disp_op->u4_error_code = u4_api_ret;
972 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk;
973
974 if(u4_api_ret)
975 {
976 pv_disp_op->u4_error_code = 1; //put a proper error code here
977 }
978 else
979 {
980
981 //Release the buffer if being sent for display
982 UWORD32 temp;
983 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0;
984
985 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd,
986 ps_op_frm->u4_y_strd);
987 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
988 >> 1;
989 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
990 >> 1;
991
992 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht;
993 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
994 >> 1;
995 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
996 >> 1;
997 if(0 == ps_dec->u4_share_disp_buf)
998 {
999 pv_disp_op->s_disp_frm_buf.u4_y_strd =
1000 pv_disp_op->s_disp_frm_buf.u4_y_wd;
1001 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1002 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1003 pv_disp_op->s_disp_frm_buf.u4_v_strd =
1004 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1005
1006 }
1007 else
1008 {
1009 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd;
1010 }
1011
1012 if(ps_dec->u4_app_disp_width)
1013 {
1014 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX(
1015 ps_dec->u4_app_disp_width,
1016 pv_disp_op->s_disp_frm_buf.u4_y_strd);
1017 }
1018
1019 pv_disp_op->u4_error_code = 0;
1020 if(pv_disp_op->e_output_format == IV_YUV_420P)
1021 {
1022 UWORD32 i;
1023 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1024 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1025 pv_disp_op->s_disp_frm_buf.u4_v_strd =
1026 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1027
1028 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1;
1029 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1030
1031 if(1 == ps_dec->u4_share_disp_buf)
1032 {
1033 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1034
1035 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1036 {
1037 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1038 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1039 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1040 - pic_buf->u2_crop_offset_y) == buf)
1041 {
1042 buf = ps_dec->disp_bufs[i].buf[1];
1043 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1044 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1045 + pic_buf->u2_crop_offset_uv;
1046
1047 buf = ps_dec->disp_bufs[i].buf[2];
1048 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1049 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1050 + pic_buf->u2_crop_offset_uv;
1051 }
1052 }
1053 }
1054
1055 }
1056 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV)
1057 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU))
1058 {
1059 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1060 pv_disp_op->s_disp_frm_buf.u4_y_strd;
1061 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1062
1063 if(1 == ps_dec->u4_share_disp_buf)
1064 {
1065 UWORD32 i;
1066
1067 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1068
1069 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1070 {
1071 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1072 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1073 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1074 - pic_buf->u2_crop_offset_y == buf)
1075 {
1076 buf = ps_dec->disp_bufs[i].buf[1];
1077 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1078 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1079 + pic_buf->u2_crop_offset_uv;
1080 ;
1081
1082 buf = ps_dec->disp_bufs[i].buf[2];
1083 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1084 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1085 + pic_buf->u2_crop_offset_uv;
1086 ;
1087 }
1088 }
1089 }
1090 pv_disp_op->s_disp_frm_buf.u4_u_wd =
1091 pv_disp_op->s_disp_frm_buf.u4_y_wd;
1092 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1093
1094 }
1095 else if((pv_disp_op->e_output_format == IV_RGB_565)
1096 || (pv_disp_op->e_output_format == IV_YUV_422ILE))
1097 {
1098
1099 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0;
1100 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1101 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0;
1102 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1103 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0;
1104 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0;
1105
1106 }
1107
1108
1109 }
1110
1111 return u4_api_ret;
1112 }
1113
1114
1115 /*****************************************************************************/
1116 /* Function Name : ih264d_release_display_field */
1117 /* */
1118 /* Description : This function releases the display field that was returned */
1119 /* here. */
1120 /* Inputs : ps_dec - Decoder parameters */
1121 /* Globals : None */
1122 /* Processing : Refer bumping process in the standard */
1123 /* Outputs : Assigns display sequence number. */
1124 /* Returns : None */
1125 /* */
1126 /* Issues : None */
1127 /* */
1128 /* Revision History: */
1129 /* */
1130 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1131 /* 27 04 2005 NS Draft */
1132 /* */
1133 /*****************************************************************************/
ih264d_release_display_field(dec_struct_t * ps_dec,ivd_get_display_frame_op_t * pv_disp_op)1134 void ih264d_release_display_field(dec_struct_t *ps_dec,
1135 ivd_get_display_frame_op_t *pv_disp_op)
1136 {
1137 if(1 == pv_disp_op->u4_error_code)
1138 {
1139 if(1 == ps_dec->u1_flushfrm)
1140 {
1141 UWORD32 i;
1142
1143 if(1 == ps_dec->u4_share_disp_buf)
1144 {
1145 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1146 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1147 {
1148 if(1 == ps_dec->u4_disp_buf_mapping[i])
1149 {
1150 ih264_buf_mgr_release(
1151 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
1152 BUF_MGR_IO);
1153 ps_dec->u4_disp_buf_mapping[i] = 0;
1154 }
1155 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1156
1157 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1158 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1159 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1160 ps_dec->u4_disp_buf_mapping[i] = 1;
1161 }
1162 ps_dec->u1_flushfrm = 0;
1163
1164 }
1165 }
1166 else
1167 {
1168 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1169
1170 if(0 == ps_dec->u4_share_disp_buf)
1171 {
1172 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1173 pv_disp_op->u4_disp_buf_id,
1174 BUF_MGR_IO);
1175
1176 }
1177 else
1178 {
1179 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1;
1180 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1181
1182 }
1183 }
1184 /*****************************************************************************/
1185 /* Function Name : ih264d_assign_display_seq */
1186 /* */
1187 /* Description : This function implments bumping process. Every outgoing */
1188 /* frame from DPB is assigned a display sequence number */
1189 /* which increases monotonically. System looks for this */
1190 /* number to display a frame. */
1191 /* here. */
1192 /* Inputs : ps_dec - Decoder parameters */
1193 /* Globals : None */
1194 /* Processing : Refer bumping process in the standard */
1195 /* Outputs : Assigns display sequence number. */
1196 /* Returns : None */
1197 /* */
1198 /* Issues : None */
1199 /* */
1200 /* Revision History: */
1201 /* */
1202 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1203 /* 27 04 2005 NS Draft */
1204 /* */
1205 /*****************************************************************************/
ih264d_assign_display_seq(dec_struct_t * ps_dec)1206 WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec)
1207 {
1208 WORD32 i;
1209 WORD32 i4_min_poc;
1210 WORD32 i4_min_poc_buf_id;
1211 WORD32 i4_min_index;
1212 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1213 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1214
1215 i4_min_poc = 0x7fffffff;
1216 i4_min_poc_buf_id = -1;
1217 i4_min_index = -1;
1218
1219 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay)
1220 {
1221 for(i = 0; i < MAX_FRAMES; i++)
1222 {
1223 if((i4_poc_buf_id_map[i][0] != -1)
1224 && (DO_NOT_DISP
1225 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0]))
1226 {
1227 if(i4_poc_buf_id_map[i][1] < i4_min_poc)
1228 {
1229 i4_min_poc = i4_poc_buf_id_map[i][1];
1230 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1231 i4_min_index = i;
1232 }
1233 }
1234 }
1235
1236 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id))
1237 {
1238 ps_dec->i4_cur_display_seq++;
1239 ih264_disp_mgr_add(
1240 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1241 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1242 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1243 i4_poc_buf_id_map[i4_min_index][0] = -1;
1244 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1245 ps_dpb_mgr->i1_poc_buf_id_entries--;
1246 }
1247 else if(DO_NOT_DISP == i4_min_poc_buf_id)
1248 {
1249 WORD32 i4_error_code;
1250 i4_error_code = ERROR_GAPS_IN_FRM_NUM;
1251 // i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1252 return i4_error_code;
1253 }
1254 }
1255 return OK;
1256 }
1257
1258 /*****************************************************************************/
1259 /* */
1260 /* Function Name : ih264d_release_display_bufs */
1261 /* */
1262 /* Description : This function implments bumping process when mmco = 5. */
1263 /* Each outgoing frame from DPB is assigned a display */
1264 /* sequence number which increases monotonically. System */
1265 /* looks for this number to display a frame. */
1266 /* Inputs : ps_dec - Decoder parameters */
1267 /* Globals : None */
1268 /* Processing : Refer bumping process in the standard for mmco = 5 */
1269 /* Outputs : Assigns display sequence number. */
1270 /* Returns : None */
1271 /* */
1272 /* Issues : None */
1273 /* */
1274 /* Revision History: */
1275 /* */
1276 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1277 /* 27 04 2005 NS Draft */
1278 /* */
1279 /*****************************************************************************/
ih264d_release_display_bufs(dec_struct_t * ps_dec)1280 void ih264d_release_display_bufs(dec_struct_t *ps_dec)
1281 {
1282 WORD32 i, j;
1283 WORD32 i4_min_poc;
1284 WORD32 i4_min_poc_buf_id;
1285 WORD32 i4_min_index;
1286 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1287 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1288
1289 i4_min_poc = 0x7fffffff;
1290 i4_min_poc_buf_id = -1;
1291 i4_min_index = -1;
1292
1293 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1294
1295 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++)
1296 {
1297 i4_min_poc = 0x7fffffff;
1298 for(i = 0; i < MAX_FRAMES; i++)
1299 {
1300 if(i4_poc_buf_id_map[i][0] != -1)
1301 {
1302 if(i4_poc_buf_id_map[i][1] < i4_min_poc)
1303 {
1304 i4_min_poc = i4_poc_buf_id_map[i][1];
1305 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1306 i4_min_index = i;
1307 }
1308 }
1309 }
1310
1311 if(DO_NOT_DISP != i4_min_poc_buf_id)
1312 {
1313 ps_dec->i4_cur_display_seq++;
1314 ih264_disp_mgr_add(
1315 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1316 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1317 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1318 i4_poc_buf_id_map[i4_min_index][0] = -1;
1319 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1320 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1321 }
1322 else
1323 {
1324 i4_poc_buf_id_map[i4_min_index][0] = -1;
1325 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1326 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1327 }
1328 }
1329 ps_dpb_mgr->i1_poc_buf_id_entries = 0;
1330 ps_dec->i4_prev_max_display_seq = ps_dec->i4_prev_max_display_seq
1331 + ps_dec->i4_max_poc + ps_dec->u1_max_dec_frame_buffering
1332 + 1;
1333 ps_dec->i4_max_poc = 0;
1334 }
1335
1336 /*****************************************************************************/
1337 /* */
1338 /* Function Name : ih264d_assign_pic_num */
1339 /* */
1340 /* Description : This function assigns pic num to each reference frame */
1341 /* depending on the cur_frame_num as speified in section */
1342 /* 8.2.4.1 */
1343 /* */
1344 /* Inputs : ps_dec */
1345 /* */
1346 /* Globals : NO globals used */
1347 /* */
1348 /* Processing : for all ST pictures */
1349 /* if( FrameNum > cur_frame_num) */
1350 /* PicNum = FrameNum - MaxFrameNum */
1351 /* else */
1352 /* PicNum = FrameNum */
1353 /* */
1354 /* Returns : void */
1355 /* */
1356 /* Issues : NO */
1357 /* */
1358 /* Revision History: */
1359 /* */
1360 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1361 /* 13 07 2002 Jay Draft */
1362 /* */
1363 /*****************************************************************************/
1364
ih264d_assign_pic_num(dec_struct_t * ps_dec)1365 void ih264d_assign_pic_num(dec_struct_t *ps_dec)
1366 {
1367 dpb_manager_t *ps_dpb_mgr;
1368 struct dpb_info_t *ps_next_dpb;
1369 WORD8 i;
1370 WORD32 i4_cur_frame_num, i4_max_frame_num;
1371 WORD32 i4_ref_frame_num;
1372 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag;
1373
1374 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1375 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num;
1376 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1377
1378 /* Start from ST head */
1379 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head;
1380 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++)
1381 {
1382 WORD32 i4_pic_num;
1383
1384 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num;
1385 if(i4_ref_frame_num > i4_cur_frame_num)
1386 {
1387 /* RefPic Buf frame_num is before Current frame_num in decode order */
1388 i4_pic_num = i4_ref_frame_num - i4_max_frame_num;
1389 }
1390 else
1391 {
1392 /* RefPic Buf frame_num is after Current frame_num in decode order */
1393 i4_pic_num = i4_ref_frame_num;
1394 }
1395
1396 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num;
1397 ps_next_dpb->i4_frame_num = i4_pic_num;
1398 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1399 if(u1_fld_pic_flag)
1400 {
1401 /* Assign the pic num to top fields and bot fields */
1402
1403 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2
1404 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag);
1405 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2
1406 + ps_dec->ps_cur_slice->u1_bottom_field_flag;
1407 }
1408 /* Chase the next link */
1409 ps_next_dpb = ps_next_dpb->ps_prev_short;
1410 }
1411
1412 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag
1413 && ps_dpb_mgr->u1_num_gaps)
1414 {
1415 WORD32 i4_start_frm, i4_end_frm;
1416 /* Assign pic numbers for gaps */
1417 for(i = 0; i < MAX_FRAMES; i++)
1418 {
1419 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i];
1420 if(i4_start_frm != INVALID_FRAME_NUM)
1421 {
1422 if(i4_start_frm > i4_cur_frame_num)
1423 {
1424 /* gap's frame_num is before Current frame_num in
1425 decode order */
1426 i4_start_frm -= i4_max_frame_num;
1427 }
1428 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm;
1429 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i];
1430
1431 if(i4_end_frm > i4_cur_frame_num)
1432 {
1433 /* gap's frame_num is before Current frame_num in
1434 decode order */
1435 i4_end_frm -= i4_max_frame_num;
1436 }
1437 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm;
1438 }
1439 }
1440 }
1441 }
1442
1443 /*!
1444 **************************************************************************
1445 * \if Function name : ih264d_update_qp \endif
1446 *
1447 * \brief
1448 * Updates the values of QP and its related entities
1449 *
1450 * \return
1451 * 0 on Success and Error code otherwise
1452 *
1453 **************************************************************************
1454 */
ih264d_update_qp(dec_struct_t * ps_dec,const WORD8 i1_qp)1455 WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp)
1456 {
1457 WORD32 i_temp;
1458 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52;
1459
1460 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25))
1461 return ERROR_INV_RANGE_QP_T;
1462
1463 ps_dec->u1_qp = i_temp;
1464 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6;
1465 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6;
1466 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset);
1467 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1468 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1469
1470 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset);
1471 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1472 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1473
1474 ps_dec->pu2_quant_scale_y =
1475 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6];
1476 ps_dec->pu2_quant_scale_u =
1477 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6];
1478 ps_dec->pu2_quant_scale_v =
1479 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6];
1480 return OK;
1481 }
1482
1483 /*****************************************************************************/
1484 /* */
1485 /* Function Name : ih264d_decode_gaps_in_frame_num */
1486 /* */
1487 /* Description : This function decodes gaps in frame number */
1488 /* */
1489 /* Inputs : ps_dec Decoder parameters */
1490 /* u2_frame_num current frame number */
1491 /* */
1492 /* Globals : None */
1493 /* Processing : This functionality needs to be implemented */
1494 /* Outputs : None */
1495 /* Returns : None */
1496 /* */
1497 /* Issues : Not implemented */
1498 /* */
1499 /* Revision History: */
1500 /* */
1501 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1502 /* 06 05 2002 NS Draft */
1503 /* */
1504 /*****************************************************************************/
ih264d_decode_gaps_in_frame_num(dec_struct_t * ps_dec,UWORD16 u2_frame_num)1505 WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec,
1506 UWORD16 u2_frame_num)
1507 {
1508 UWORD32 u4_next_frm_num, u4_start_frm_num;
1509 UWORD32 u4_max_frm_num;
1510 pocstruct_t s_tmp_poc;
1511 WORD32 i4_poc;
1512 dec_slice_params_t *ps_cur_slice;
1513
1514 dec_pic_params_t *ps_pic_params;
1515 WORD8 i1_gap_idx;
1516 WORD32 *i4_gaps_start_frm_num;
1517 dpb_manager_t *ps_dpb_mgr;
1518 WORD32 i4_frame_gaps;
1519 WORD8 *pi1_gaps_per_seq;
1520 WORD32 ret;
1521
1522 ps_cur_slice = ps_dec->ps_cur_slice;
1523 if(ps_cur_slice->u1_field_pic_flag)
1524 {
1525 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num)
1526 return 0;
1527 }
1528
1529 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1;
1530 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1531
1532 // check
1533 if(u4_next_frm_num >= u4_max_frm_num)
1534 {
1535 u4_next_frm_num -= u4_max_frm_num;
1536 }
1537
1538 if(u4_next_frm_num == u2_frame_num)
1539 {
1540 return (0);
1541 }
1542
1543 // check
1544 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL)
1545 && (u4_next_frm_num >= u2_frame_num))
1546 {
1547 return (0);
1548 }
1549 u4_start_frm_num = u4_next_frm_num;
1550
1551 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1552 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1553 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1554 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1555 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0;
1556 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0;
1557
1558 ps_cur_slice = ps_dec->ps_cur_slice;
1559 ps_pic_params = ps_dec->ps_cur_pps;
1560
1561 i4_frame_gaps = 0;
1562 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1563
1564 /* Find a empty slot to store gap seqn info */
1565 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num;
1566 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++)
1567 {
1568 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx])
1569 break;
1570 }
1571 if(MAX_FRAMES == i1_gap_idx)
1572 {
1573 UWORD32 i4_error_code;
1574 i4_error_code = ERROR_DBP_MANAGER_T;
1575 // i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1576 return i4_error_code;
1577 }
1578
1579 i4_poc = 0;
1580 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num;
1581 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1;
1582 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq;
1583 pi1_gaps_per_seq[i1_gap_idx] = 0;
1584 while(u4_next_frm_num != u2_frame_num)
1585 {
1586 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1587 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type)
1588 {
1589 /* allocate a picture buffer and insert it as ST node */
1590 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num,
1591 &ps_dec->s_prev_pic_poc,
1592 &s_tmp_poc, ps_cur_slice,
1593 ps_pic_params, 1, 0, 0,
1594 &i4_poc);
1595 if(ret != OK)
1596 return ret;
1597
1598 /* Display seq no calculations */
1599 if(i4_poc >= ps_dec->i4_max_poc)
1600 ps_dec->i4_max_poc = i4_poc;
1601 /* IDR Picture or POC wrap around */
1602 if(i4_poc == 0)
1603 {
1604 ps_dec->i4_prev_max_display_seq =
1605 ps_dec->i4_prev_max_display_seq
1606 + ps_dec->i4_max_poc
1607 + ps_dec->u1_max_dec_frame_buffering
1608 + 1;
1609 ps_dec->i4_max_poc = 0;
1610 }
1611
1612 ps_cur_slice->u1_mmco_equalto5 = 0;
1613 ps_cur_slice->u2_frame_num = u4_next_frm_num;
1614 }
1615
1616 // check
1617 if(ps_dpb_mgr->i1_poc_buf_id_entries
1618 >= ps_dec->u1_max_dec_frame_buffering)
1619 {
1620 ret = ih264d_assign_display_seq(ps_dec);
1621 if(ret != OK)
1622 return ret;
1623 }
1624
1625 ret = ih264d_insert_pic_in_display_list(
1626 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP,
1627 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc),
1628 u4_next_frm_num);
1629 if(ret != OK)
1630 return ret;
1631
1632 pi1_gaps_per_seq[i1_gap_idx]++;
1633 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr,
1634 ps_dec->ps_cur_sps->u1_num_ref_frames);
1635 if(ret != OK)
1636 return ret;
1637
1638 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1639
1640 u4_next_frm_num++;
1641 if(u4_next_frm_num >= u4_max_frm_num)
1642 {
1643 u4_next_frm_num -= u4_max_frm_num;
1644 }
1645
1646 i4_frame_gaps++;
1647 }
1648
1649 return OK;
1650 }
1651
1652 /*!
1653 **************************************************************************
1654 * \if Function name : ih264d_create_pic_buffers \endif
1655 *
1656 * \brief
1657 * This function creates Picture Buffers.
1658 *
1659 * \return
1660 * 0 on Success and -1 on error
1661 **************************************************************************
1662 */
ih264d_create_pic_buffers(UWORD8 u1_num_of_buf,dec_struct_t * ps_dec)1663 WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf,
1664 dec_struct_t *ps_dec)
1665 {
1666 struct pic_buffer_t *ps_pic_buf;
1667 UWORD8 i;
1668 UWORD32 u4_luma_size, u4_chroma_size;
1669 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag;
1670 WORD32 j;
1671 UWORD8 *pu1_buf;
1672
1673 ps_pic_buf = ps_dec->ps_pic_buf_base;
1674 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr);
1675 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
1676 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
1677 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
1678
1679 {
1680 if(ps_dec->u4_share_disp_buf == 1)
1681 {
1682 /* In case of buffers getting shared between application and library
1683 there is no need of reference memtabs. Instead of setting the i4_size
1684 to zero, it is reduced to a small i4_size to ensure that changes
1685 in the code are minimal */
1686 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1687 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
1688 || (ps_dec->u1_chroma_format == IV_YUV_420P))
1689 {
1690 u4_luma_size = 64;
1691 }
1692
1693 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1694 {
1695 u4_chroma_size = 64;
1696 }
1697
1698 }
1699 }
1700
1701 pu1_buf = ps_dec->pu1_pic_buf_base;
1702
1703 /* Allocate memory for refernce buffers */
1704 for(i = 0; i < u1_num_of_buf; i++)
1705 {
1706 UWORD32 u4_offset;
1707 WORD32 buf_ret;
1708 UWORD8 *pu1_luma, *pu1_chroma;
1709 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1710
1711 pu1_luma = pu1_buf;
1712 pu1_buf += ALIGN64(u4_luma_size);
1713 pu1_chroma = pu1_buf;
1714 pu1_buf += ALIGN64(u4_chroma_size);
1715
1716 /* Offset to the start of the pic from the top left corner of the frame
1717 buffer */
1718
1719 if((0 == ps_dec->u4_share_disp_buf)
1720 || (NULL == ps_dec->disp_bufs[i].buf[0]))
1721 {
1722 UWORD32 pad_len_h, pad_len_v;
1723
1724 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1725 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset;
1726
1727 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1));
1728 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1729
1730 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1731
1732 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1733 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1734
1735 }
1736 else
1737 {
1738 UWORD32 pad_len_h, pad_len_v;
1739 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1740 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0]
1741 + u4_offset;
1742
1743 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset;
1744
1745 if(ps_dec->u1_chroma_format == IV_YUV_420P)
1746 {
1747 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1748 (PAD_LEN_Y_H >> 1));
1749 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1750
1751 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1752 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1753 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1754
1755 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1756 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1757
1758 }
1759 else
1760 {
1761 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1762 (PAD_LEN_Y_H >> 1));
1763 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1764
1765 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1766 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1767 + u4_offset;
1768 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1769 + u4_offset;
1770
1771 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1772 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1773 }
1774 }
1775
1776 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y;
1777 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv;
1778 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y;
1779 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv;
1780
1781 ps_pic_buf->u1_pic_buf_id = i;
1782
1783 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1784 ps_pic_buf, i);
1785 if(0 != buf_ret)
1786 {
1787 ps_dec->i4_error_code = ERROR_BUF_MGR;
1788 return ERROR_BUF_MGR;
1789 }
1790
1791 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf;
1792 ps_pic_buf++;
1793 }
1794
1795 if(1 == ps_dec->u4_share_disp_buf)
1796 {
1797 for(i = 0; i < u1_num_of_buf; i++)
1798 ps_dec->u4_disp_buf_mapping[i] = 1;
1799 }
1800 return OK;
1801 }
1802
1803 /*!
1804 **************************************************************************
1805 * \if Function name : ih264d_allocate_dynamic_bufs \endif
1806 *
1807 * \brief
1808 * This function allocates memory required by Decoder.
1809 *
1810 * \param ps_dec: Pointer to dec_struct_t.
1811 *
1812 * \return
1813 * Returns i4_status as returned by MemManager.
1814 *
1815 **************************************************************************
1816 */
ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec)1817 WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec)
1818 {
1819 struct MemReq s_MemReq;
1820 struct MemBlock *p_MemBlock;
1821
1822 pred_info_t *ps_pred_frame;
1823 dec_mb_info_t *ps_frm_mb_info;
1824 dec_slice_struct_t *ps_dec_slice_buf;
1825 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map;
1826 UWORD16 *pu2_slice_num_map;
1827
1828 WORD16 *pi16_res_coeff;
1829 WORD16 i16_status = 0;
1830 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag);
1831 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y;
1832 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv;
1833 WORD8 c_i = 0;
1834 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps;
1835 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld;
1836 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs;
1837 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs;
1838 UWORD32 u4_blk_wd;
1839 UWORD32 ui_size = 0;
1840 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0;
1841 UWORD8 *pu1_buf;
1842 WORD32 num_entries;
1843 WORD32 size;
1844 void *pv_buf;
1845 UWORD32 u4_num_bufs;
1846 UWORD32 u4_luma_size, u4_chroma_size;
1847 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1848
1849 size = u4_total_mbs;
1850 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1851 RETURN_IF((NULL == pv_buf), IV_FAIL);
1852 ps_dec->pu1_dec_mb_map = pv_buf;
1853
1854 size = u4_total_mbs;
1855 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1856 RETURN_IF((NULL == pv_buf), IV_FAIL);
1857 ps_dec->pu1_recon_mb_map = pv_buf;
1858
1859 size = u4_total_mbs * sizeof(UWORD16);
1860 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1861 RETURN_IF((NULL == pv_buf), IV_FAIL);
1862 ps_dec->pu2_slice_num_map = pv_buf;
1863
1864 /************************************************************/
1865 /* Post allocation Initialisations */
1866 /************************************************************/
1867 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1868 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1869 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1870
1871 ps_dec->ps_pred_start = ps_dec->ps_pred;
1872
1873 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp);
1874 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1875 RETURN_IF((NULL == pv_buf), IV_FAIL);
1876 memset(pv_buf, 0, size);
1877 ps_dec->ps_parse_mb_data = pv_buf;
1878
1879 size = sizeof(parse_part_params_t)
1880 * ((ps_dec->u1_recon_mb_grp) << 4);
1881 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1882 RETURN_IF((NULL == pv_buf), IV_FAIL);
1883 ps_dec->ps_parse_part_params = pv_buf;
1884
1885 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld);
1886 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1887 RETURN_IF((NULL == pv_buf), IV_FAIL);
1888 ps_dec->ps_deblk_top_mb = pv_buf;
1889
1890 size = ((sizeof(ctxt_inc_mb_info_t))
1891 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1));
1892 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1893 RETURN_IF((NULL == pv_buf), IV_FAIL);
1894 ps_dec->p_ctxt_inc_mb_map = pv_buf;
1895
1896 /* 0th entry of CtxtIncMbMap will be always be containing default values
1897 for CABAC context representing MB not available */
1898 ps_dec->p_ctxt_inc_mb_map += 1;
1899
1900 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1901 * 16);
1902 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1903 RETURN_IF((NULL == pv_buf), IV_FAIL);
1904 ps_dec->ps_mv_p[0] = pv_buf;
1905
1906 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1907 * 16);
1908 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1909 RETURN_IF((NULL == pv_buf), IV_FAIL);
1910 ps_dec->ps_mv_p[1] = pv_buf;
1911
1912 {
1913 UWORD8 i;
1914 for(i = 0; i < MV_SCRATCH_BUFS; i++)
1915 {
1916 size = (sizeof(mv_pred_t)
1917 * ps_dec->u1_recon_mb_grp * 4);
1918 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1919 RETURN_IF((NULL == pv_buf), IV_FAIL);
1920 ps_dec->ps_mv_top_p[i] = pv_buf;
1921 }
1922 }
1923
1924 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
1925 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1926 RETURN_IF((NULL == pv_buf), IV_FAIL);
1927 ps_dec->pu1_y_intra_pred_line = pv_buf;
1928 memset(ps_dec->pu1_y_intra_pred_line, 0, size);
1929 ps_dec->pu1_y_intra_pred_line += MB_SIZE;
1930
1931 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
1932 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1933 RETURN_IF((NULL == pv_buf), IV_FAIL);
1934 ps_dec->pu1_u_intra_pred_line = pv_buf;
1935 memset(ps_dec->pu1_u_intra_pred_line, 0, size);
1936 ps_dec->pu1_u_intra_pred_line += MB_SIZE;
1937
1938 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
1939 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1940 RETURN_IF((NULL == pv_buf), IV_FAIL);
1941 ps_dec->pu1_v_intra_pred_line = pv_buf;
1942 memset(ps_dec->pu1_v_intra_pred_line, 0, size);
1943 ps_dec->pu1_v_intra_pred_line += MB_SIZE;
1944
1945 if(ps_dec->u1_separate_parse)
1946 {
1947 /* Needs one extra row of info, to hold top row data */
1948 size = sizeof(mb_neigbour_params_t)
1949 * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1));
1950 }
1951 else
1952 {
1953 size = sizeof(mb_neigbour_params_t)
1954 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld);
1955 }
1956 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1957 RETURN_IF((NULL == pv_buf), IV_FAIL);
1958
1959 ps_dec->ps_nbr_mb_row = pv_buf;
1960 memset(ps_dec->ps_nbr_mb_row, 0, size);
1961
1962 /* Allocate deblock MB info */
1963 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t);
1964
1965 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1966 RETURN_IF((NULL == pv_buf), IV_FAIL);
1967 ps_dec->ps_deblk_pic = pv_buf;
1968
1969 memset(ps_dec->ps_deblk_pic, 0, size);
1970
1971 /* Allocate frame level mb info */
1972 size = sizeof(dec_mb_info_t) * u4_total_mbs;
1973 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1974 RETURN_IF((NULL == pv_buf), IV_FAIL);
1975 ps_dec->ps_frm_mb_info = pv_buf;
1976 memset(ps_dec->ps_frm_mb_info, 0, size);
1977
1978 /* Allocate memory for slice headers dec_slice_struct_t */
1979 num_entries = MAX_FRAMES;
1980 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) &&
1981 (0 == ps_dec->i4_display_delay))
1982 {
1983 num_entries = 1;
1984 }
1985 num_entries = ((2 * num_entries) + 1);
1986 if(BASE_PROFILE_IDC != ps_dec->ps_cur_sps->u1_profile_idc)
1987 {
1988 num_entries *= 2;
1989 }
1990
1991 size = num_entries * sizeof(void *);
1992 size += PAD_MAP_IDX_POC * sizeof(void *);
1993 size *= u4_total_mbs;
1994 size += sizeof(dec_slice_struct_t) * u4_total_mbs;
1995 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1996 RETURN_IF((NULL == pv_buf), IV_FAIL);
1997
1998 ps_dec->ps_dec_slice_buf = pv_buf;
1999 memset(ps_dec->ps_dec_slice_buf, 0, size);
2000 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf;
2001 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs;
2002 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf;
2003
2004 /* Allocate memory for packed pred info */
2005 num_entries = u4_total_mbs;
2006 num_entries *= 16 * 2;
2007
2008 size = sizeof(pred_info_pkd_t) * num_entries;
2009 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2010 RETURN_IF((NULL == pv_buf), IV_FAIL);
2011 ps_dec->ps_pred_pkd = pv_buf;
2012
2013 /* Allocate memory for coeff data */
2014 size = MB_LUM_SIZE * sizeof(WORD16);
2015 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2016 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2017 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
2018 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2019 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2020 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2021 size += u4_total_mbs * 32;
2022 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2023 RETURN_IF((NULL == pv_buf), IV_FAIL);
2024
2025 ps_dec->pi2_coeff_data = pv_buf;
2026
2027 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE);
2028
2029 /* Allocate MV bank buffer */
2030 {
2031 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2032
2033 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4);
2034 mvpred_buffer_size = sizeof(mv_pred_t)
2035 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4);
2036
2037 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
2038
2039 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2040 u4_num_bufs = MAX(u4_num_bufs, 2);
2041 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size);
2042 size *= u4_num_bufs;
2043 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2044 RETURN_IF((NULL == pv_buf), IV_FAIL);
2045 ps_dec->pu1_mv_bank_buf_base = pv_buf;
2046 }
2047
2048 /* Allocate Pic buffer */
2049 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
2050 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
2051
2052 {
2053 if(ps_dec->u4_share_disp_buf == 1)
2054 {
2055 /* In case of buffers getting shared between application and library
2056 there is no need of reference memtabs. Instead of setting the i4_size
2057 to zero, it is reduced to a small i4_size to ensure that changes
2058 in the code are minimal */
2059 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2060 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
2061 || (ps_dec->u1_chroma_format == IV_YUV_420P))
2062 {
2063 u4_luma_size = 64;
2064 }
2065
2066 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2067 {
2068 u4_chroma_size = 64;
2069 }
2070
2071 }
2072 }
2073
2074 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size);
2075 size *= ps_dec->u1_pic_bufs;
2076 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2077 RETURN_IF((NULL == pv_buf), IV_FAIL);
2078 ps_dec->pu1_pic_buf_base = pv_buf;
2079
2080 /* Post allocation Increment Actions */
2081
2082 /***************************************************************************/
2083 /*Initialize cabac context pointers for every SE that has fixed contextIdx */
2084 /***************************************************************************/
2085 {
2086 bin_ctxt_model_t * const p_cabac_ctxt_table_t =
2087 ps_dec->p_cabac_ctxt_table_t;
2088 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t =
2089 ps_dec->p_coeff_abs_level_minus1_t;
2090 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t;
2091
2092 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t
2093 + MB_FIELD_DECODING_FLAG;
2094 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t
2095 + PREV_INTRA4X4_PRED_MODE_FLAG;
2096 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t
2097 + REM_INTRA4X4_PRED_MODE;
2098 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t
2099 + INTRA_CHROMA_PRED_MODE;
2100 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA;
2101 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX;
2102 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X;
2103 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y;
2104 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0;
2105 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4;
2106 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8;
2107 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12;
2108 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16;
2109 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA;
2110 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA;
2111
2112 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2113 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET;
2114
2115 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2116 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET;
2117
2118 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t
2119 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET;
2120
2121 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2122 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET;
2123
2124 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2125 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET;
2126
2127 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t
2128 + COEFF_ABS_LEVEL_MINUS1_8X8
2129 + COEFF_ABS_LEVEL_CAT_5_OFFSET;
2130
2131 /********************************************************/
2132 /* context for the high profile related syntax elements */
2133 /* This is maintained seperately in s_high_profile */
2134 /********************************************************/
2135 {
2136
2137 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t
2138 + TRANSFORM_SIZE_8X8_FLAG;
2139
2140 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t
2141 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2142
2143 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame =
2144 p_cabac_ctxt_table_t
2145 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2146
2147 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 =
2148 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8;
2149
2150 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t
2151 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2152
2153 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field =
2154 p_cabac_ctxt_table_t
2155 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2156 }
2157 }
2158 return (i16_status);
2159 }
2160
2161 /*!
2162 **************************************************************************
2163 * \if Function name : ih264d_free_dynamic_bufs \endif
2164 *
2165 * \brief
2166 * This function frees dynamic memory allocated by Decoder.
2167 *
2168 * \param ps_dec: Pointer to dec_struct_t.
2169 *
2170 * \return
2171 * Returns i4_status as returned by MemManager.
2172 *
2173 **************************************************************************
2174 */
ih264d_free_dynamic_bufs(dec_struct_t * ps_dec)2175 WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec)
2176 {
2177 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
2178
2179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic);
2180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map);
2181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map);
2182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map);
2183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf);
2184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info);
2185 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data);
2186 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data);
2187 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params);
2188 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb);
2189
2190 if(ps_dec->p_ctxt_inc_mb_map)
2191 {
2192 ps_dec->p_ctxt_inc_mb_map -= 1;
2193 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map);
2194 }
2195
2196 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]);
2197 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]);
2198 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd);
2199 {
2200 UWORD8 i;
2201 for(i = 0; i < MV_SCRATCH_BUFS; i++)
2202 {
2203 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]);
2204 }
2205 }
2206
2207 if(ps_dec->pu1_y_intra_pred_line)
2208 {
2209 ps_dec->pu1_y_intra_pred_line -= MB_SIZE;
2210 }
2211 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line);
2212
2213 if(ps_dec->pu1_u_intra_pred_line)
2214 {
2215 ps_dec->pu1_u_intra_pred_line -= MB_SIZE;
2216 }
2217 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line);
2218
2219 if(ps_dec->pu1_v_intra_pred_line)
2220 {
2221 ps_dec->pu1_v_intra_pred_line -= MB_SIZE;
2222 }
2223 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line);
2224 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row);
2225 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base);
2226 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base);
2227 return 0;
2228 }
2229
2230 /*!
2231 **************************************************************************
2232 * \if Function name : ih264d_create_mv_bank \endif
2233 *
2234 * \brief
2235 * This function creates MV bank.
2236 *
2237 * \param memType : Type of memory being handled
2238 * 0: Display Buffer
2239 * 1: Decoder Buffer
2240 * 2: Internal Buffer
2241 * \param u1_num_of_buf: Number of decode or display buffers.
2242 * \param u4_wd : Frame width.
2243 * \param u4_ht : Frame Height.
2244 * \param ps_pic_buf_api : Pointer to Picture Buffer API.
2245 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system.
2246 *
2247 * \return
2248 * 0 on Success and -1 on error
2249 *
2250 **************************************************************************
2251 */
ih264d_create_mv_bank(void * pv_dec,UWORD32 ui_width,UWORD32 ui_height)2252 WORD32 ih264d_create_mv_bank(void *pv_dec,
2253 UWORD32 ui_width,
2254 UWORD32 ui_height)
2255 {
2256 UWORD8 i;
2257 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2258 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base;
2259 col_mv_buf_t *ps_col_mv;
2260 mv_pred_t *ps_mv;
2261 UWORD8 *pu1_col_zero_flag_buf;
2262 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec;
2263 WORD32 buf_ret;
2264 UWORD32 u4_num_bufs;
2265 UWORD8 *pu1_buf;
2266 WORD32 size;
2267 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2268
2269 col_flag_buffer_size = ((ui_width * ui_height) >> 4);
2270 mvpred_buffer_size = sizeof(mv_pred_t)
2271 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4);
2272
2273 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
2274
2275 ps_col_mv = ps_dec->ps_col_mv_base;
2276
2277 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
2278
2279 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2280 u4_num_bufs = MAX(u4_num_bufs, 2);
2281 pu1_buf = ps_dec->pu1_mv_bank_buf_base;
2282 for(i = 0 ; i < u4_num_bufs ; i++)
2283 {
2284 pu1_col_zero_flag_buf = pu1_buf;
2285 pu1_buf += ALIGN64(col_flag_buffer_size);
2286
2287 ps_mv = (mv_pred_t *)pu1_buf;
2288 pu1_buf += ALIGN64(mvpred_buffer_size);
2289
2290 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t));
2291 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4;
2292
2293 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf;
2294 ps_col_mv->pv_mv = (void *)ps_mv;
2295 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i);
2296 if(0 != buf_ret)
2297 {
2298 ps_dec->i4_error_code = ERROR_BUF_MGR;
2299 return ERROR_BUF_MGR;
2300 }
2301 ps_col_mv++;
2302 }
2303 return OK;
2304 }
2305
ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t * ps_tu_4x4,WORD16 * pi2_out_coeff_data,UWORD8 * pu1_inv_scan)2306 void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4,
2307 WORD16 *pi2_out_coeff_data,
2308 UWORD8 *pu1_inv_scan)
2309 {
2310 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map;
2311 WORD32 idx;
2312 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0];
2313
2314 while(u2_sig_coeff_map)
2315 {
2316 idx = CLZ(u2_sig_coeff_map);
2317
2318 idx = 31 - idx;
2319 RESET_BIT(u2_sig_coeff_map,idx);
2320
2321 idx = pu1_inv_scan[idx];
2322 pi2_out_coeff_data[idx] = *pi2_coeff_data++;
2323
2324 }
2325 }
2326