1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef __ANDROID__
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128
129 /*****************************************************************************/
130 /* */
131 /* Function Name : impeg2d_api_rel_display_frame */
132 /* */
133 /* Description : Release displ buffers that will be shared between decoder */
134 /* and application */
135 /* Inputs : Error message */
136 /* Globals : None */
137 /* Processing : Just prints error message to console */
138 /* Outputs : Error mesage to the console */
139 /* Returns : None */
140 /* */
141 /* Issues : <List any issues or problems with this function> */
142 /* */
143 /* Revision History: */
144 /* */
145 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
146 /* 27 05 2006 Sankar Creation */
147 /* */
148 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)149 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
150 void *pv_api_ip,
151 void *pv_api_op)
152 {
153
154 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
155 ivd_rel_display_frame_op_t *dec_rel_disp_op;
156
157 dec_state_t *ps_dec_state;
158 dec_state_multi_core_t *ps_dec_state_multi_core;
159
160
161 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
162 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
163
164 dec_rel_disp_op->u4_error_code = 0;
165 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
166 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
167
168
169 /* If not in shared disp buf mode, return */
170 if(0 == ps_dec_state->u4_share_disp_buf)
171 return IV_SUCCESS;
172
173 if(NULL == ps_dec_state->pv_pic_buf_mg)
174 return IV_SUCCESS;
175
176
177 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
178
179 return IV_SUCCESS;
180 }
181
182 /*****************************************************************************/
183 /* */
184 /* Function Name : impeg2d_api_set_display_frame */
185 /* */
186 /* Description : Sets display buffers that will be shared between decoder */
187 /* and application */
188 /* Inputs : Error message */
189 /* Globals : None */
190 /* Processing : Just prints error message to console */
191 /* Outputs : Error mesage to the console */
192 /* Returns : None */
193 /* */
194 /* Issues : <List any issues or problems with this function> */
195 /* */
196 /* Revision History: */
197 /* */
198 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
199 /* 27 05 2006 Sankar Creation */
200 /* */
201 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)202 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
203 void *pv_api_ip,
204 void *pv_api_op)
205 {
206
207 ivd_set_display_frame_ip_t *dec_disp_ip;
208 ivd_set_display_frame_op_t *dec_disp_op;
209
210 UWORD32 i;
211 dec_state_t *ps_dec_state;
212 dec_state_multi_core_t *ps_dec_state_multi_core;
213 UWORD32 u4_num_disp_bufs;
214
215
216 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
217 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
218 dec_disp_op->u4_error_code = 0;
219
220 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
221 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
222 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
223
224 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
225 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
226
227 if(ps_dec_state->u4_share_disp_buf)
228 {
229 pic_buf_t *ps_pic_buf;
230 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
231 for(i = 0; i < u4_num_disp_bufs; i++)
232 {
233
234 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
235 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
236 {
237 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
238 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
239 }
240 else
241 {
242 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
243 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
244 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
245 }
246
247 ps_pic_buf->i4_buf_id = i;
248
249 ps_pic_buf->u1_used_as_ref = 0;
250
251 ps_pic_buf->u4_ts = 0;
252
253 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
254 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
255 ps_pic_buf++;
256
257 }
258 }
259 memcpy(&(ps_dec_state->as_disp_buffers[0]),
260 &(dec_disp_ip->s_disp_buffer),
261 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
262
263 return IV_SUCCESS;
264
265 }
266
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)267 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
268 void *pv_api_ip,
269 void *pv_api_op)
270 {
271 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
272 impeg2d_ctl_set_num_cores_op_t *ps_op;
273 dec_state_t *ps_dec_state;
274 dec_state_multi_core_t *ps_dec_state_multi_core;
275
276 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
277 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
278
279 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
280 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
281
282 if(ps_ip->u4_num_cores > 0)
283 {
284
285
286 WORD32 i;
287 for(i = 0; i < MAX_THREADS; i++)
288 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
289 }
290 else
291 {
292 ps_dec_state->i4_num_cores = 1;
293 }
294 ps_op->u4_error_code = IV_SUCCESS;
295
296 return IV_SUCCESS;
297 }
298
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
304 impeg2d_ctl_get_seq_info_op_t *ps_op;
305 dec_state_t *ps_codec;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
313 UNUSED(ps_ip);
314 if(ps_codec->u2_header_done == 1)
315 {
316 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
317 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
318 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
319 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
320 if(ps_codec->u1_seq_disp_extn_present == 1)
321 {
322 ps_op->u1_video_format = ps_codec->u1_video_format;
323 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
324 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
325 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
326 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
327 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
328 }
329 else
330 {
331 ps_op->u1_video_format = 5;
332 ps_op->u1_colour_primaries = 2;
333 ps_op->u1_transfer_characteristics = 2;
334 ps_op->u1_matrix_coefficients = 2;
335 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
336 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
337 }
338 ps_op->u4_error_code = IV_SUCCESS;
339 return IV_SUCCESS;
340 }
341 else
342 {
343 ps_op->u4_error_code = IV_FAIL;
344 return IV_FAIL;
345 }
346 }
347
348 /**
349 *******************************************************************************
350 *
351 * @brief
352 * Sets Processor type
353 *
354 * @par Description:
355 * Sets Processor type
356 *
357 * @param[in] ps_codec_obj
358 * Pointer to codec object at API level
359 *
360 * @param[in] pv_api_ip
361 * Pointer to input argument structure
362 *
363 * @param[out] pv_api_op
364 * Pointer to output argument structure
365 *
366 * @returns Status
367 *
368 * @remarks
369 *
370 *
371 *******************************************************************************
372 */
373
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)374 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
375 void *pv_api_ip,
376 void *pv_api_op)
377 {
378 impeg2d_ctl_set_processor_ip_t *ps_ip;
379 impeg2d_ctl_set_processor_op_t *ps_op;
380 dec_state_t *ps_codec;
381 dec_state_multi_core_t *ps_dec_state_multi_core;
382
383 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
384 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
385
386 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
387 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
388
389 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
390 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
391
392 impeg2d_init_function_ptr(ps_codec);
393
394
395 ps_op->u4_error_code = 0;
396 return IV_SUCCESS;
397 }
398 /*****************************************************************************/
399 /* */
400 /* Function Name : impeg2d_fill_mem_rec */
401 /* */
402 /* Description : */
403 /* Inputs : */
404 /* Globals : */
405 /* Processing : */
406 /* Outputs : */
407 /* Returns : */
408 /* */
409 /* Issues : */
410 /* */
411 /* Revision History: */
412 /* */
413 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
414 /* 17 09 2007 Rajendra C Y Draft */
415 /* */
416 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)417 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
418 impeg2d_fill_mem_rec_op_t *ps_op)
419 {
420 UWORD32 u4_i;
421
422 UWORD8 u1_no_rec = 0;
423 UWORD32 max_frm_width,max_frm_height,max_frm_size;
424 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
425 WORD32 i4_num_threads;
426 WORD32 i4_share_disp_buf, i4_chroma_format;
427 WORD32 i4_chroma_size;
428 UWORD32 u4_deinterlace;
429 UNUSED(u4_deinterlace);
430 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
431 max_frm_height = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht);
432
433 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
434
435 i4_chroma_size = max_frm_width * max_frm_height / 4;
436
437 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
438 {
439 #ifndef LOGO_EN
440 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
441 #else
442 i4_share_disp_buf = 0;
443 #endif
444 }
445 else
446 {
447 i4_share_disp_buf = 0;
448 }
449 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
450 {
451 i4_chroma_format = ps_ip->e_output_format;
452 }
453 else
454 {
455 i4_chroma_format = -1;
456 }
457
458 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
459 {
460 u4_deinterlace = ps_ip->u4_deinterlace;
461 }
462 else
463 {
464 u4_deinterlace = 0;
465 }
466
467
468 if( (i4_chroma_format != IV_YUV_420P) &&
469 (i4_chroma_format != IV_YUV_420SP_UV) &&
470 (i4_chroma_format != IV_YUV_420SP_VU))
471 {
472 i4_share_disp_buf = 0;
473 }
474
475 /* Disable deinterlacer in shared mode */
476 if(i4_share_disp_buf)
477 {
478 u4_deinterlace = 0;
479 }
480
481 /*************************************************************************/
482 /* Fill the memory requirement XDM Handle */
483 /*************************************************************************/
484 /* ! */
485 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
486 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
487 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
488
489 ps_mem_rec++;
490 u1_no_rec++;
491
492 {
493 /*************************************************************************/
494 /* Fill the memory requirement for threads context */
495 /*************************************************************************/
496 /* ! */
497 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
498 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
499 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
500
501 ps_mem_rec++;
502 u1_no_rec++;
503 }
504
505 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
506 {
507 /*************************************************************************/
508 /* Fill the memory requirement for MPEG2 Decoder Context */
509 /*************************************************************************/
510 /* ! */
511 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
512 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
513 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
514
515 ps_mem_rec++;
516 u1_no_rec++;
517
518 /* To store thread handle */
519 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
520 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
521 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
522
523 ps_mem_rec++;
524 u1_no_rec++;
525
526 /*************************************************************************/
527 /* Fill the memory requirement for Motion Compensation Buffers */
528 /*************************************************************************/
529 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
530 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
531
532 /* for mc_fw_buf.pu1_y */
533 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
534
535 /* for mc_fw_buf.pu1_u */
536 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
537
538 /* for mc_fw_buf.pu1_v */
539 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
540
541 /* for mc_bk_buf.pu1_y */
542 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
543
544 /* for mc_bk_buf.pu1_u */
545 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
546
547 /* for mc_bk_buf.pu1_v */
548 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
549
550 /* for mc_buf.pu1_y */
551 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
552
553 /* for mc_buf.pu1_u */
554 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
555
556 /* for mc_buf.pu1_v */
557 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
558
559 ps_mem_rec++;
560 u1_no_rec++;
561
562
563 /*************************************************************************/
564 /* Fill the memory requirement Stack Context */
565 /*************************************************************************/
566 /* ! */
567 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
568 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
569 ps_mem_rec->u4_mem_size = 392;
570
571 ps_mem_rec++;
572 u1_no_rec++;
573 }
574
575
576
577 {
578 /*************************************************************************/
579 /* Fill the memory requirement for Picture Buffer Manager */
580 /*************************************************************************/
581 /* ! */
582 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
583 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
584 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
585
586 ps_mem_rec++;
587 u1_no_rec++;
588 }
589 /*************************************************************************/
590 /* Internal Frame Buffers */
591 /*************************************************************************/
592 /* ! */
593
594 {
595 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
596 {
597 /* ! */
598 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
599 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
600 if(0 == i4_share_disp_buf)
601 ps_mem_rec->u4_mem_size = max_frm_size;
602 else if(IV_YUV_420P != i4_chroma_format)
603 {
604 /* If color format is not 420P and it is shared, then allocate for chroma */
605 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
606 }
607 else
608 ps_mem_rec->u4_mem_size = 64;
609 ps_mem_rec++;
610 u1_no_rec++;
611 }
612 }
613
614
615
616 {
617 WORD32 i4_job_queue_size;
618 WORD32 i4_num_jobs;
619
620 /* One job per row of MBs */
621 i4_num_jobs = max_frm_height >> 4;
622
623 /* One format convert/frame copy job per row of MBs for non-shared mode*/
624 i4_num_jobs += max_frm_height >> 4;
625
626
627 i4_job_queue_size = impeg2_jobq_ctxt_size();
628 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
629 ps_mem_rec->u4_mem_size = i4_job_queue_size;
630 ps_mem_rec->u4_mem_alignment = 128;
631 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
632
633 ps_mem_rec++;
634 u1_no_rec++;
635
636 }
637
638 ps_mem_rec->u4_mem_alignment = 128;
639 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
640 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
641 ps_mem_rec++;
642 u1_no_rec++;
643
644 ps_mem_rec->u4_mem_alignment = 128;
645 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
646
647 if(IV_YUV_420P != i4_chroma_format)
648 ps_mem_rec->u4_mem_size = max_frm_size;
649 else
650 ps_mem_rec->u4_mem_size = 64;
651
652 ps_mem_rec++;
653 u1_no_rec++;
654
655 ps_mem_rec->u4_mem_alignment = 128;
656 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
657 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
658 ps_mem_rec++;
659 u1_no_rec++;
660 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
661 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
662 }
663
664
665 /*****************************************************************************/
666 /* */
667 /* Function Name : impeg2d_api_get_version */
668 /* */
669 /* Description : */
670 /* */
671 /* Inputs : */
672 /* Globals : <Does it use any global variables?> */
673 /* Outputs : */
674 /* Returns : void */
675 /* */
676 /* Issues : none */
677 /* */
678 /* Revision History: */
679 /* */
680 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
681 /* 22 10 2008 100356 Draft */
682 /* */
683 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)684 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
685 void *pv_api_ip,
686 void *pv_api_op)
687 {
688 char au1_version_string[512];
689
690 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
691 impeg2d_ctl_getversioninfo_op_t *ps_op;
692
693 UNUSED(ps_dechdl);
694
695 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
696 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
697
698 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
699
700 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
701 CODEC_VENDOR);
702
703 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
704 {
705 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
706 return (IV_FAIL);
707 }
708
709 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
710 >= (strlen(au1_version_string) + 1))
711 {
712 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
713 au1_version_string, (strlen(au1_version_string) + 1));
714 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
715 }
716 else
717 {
718 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
719 }
720
721 return (IV_SUCCESS);
722 }
723
724 /*****************************************************************************/
725 /* */
726 /* Function Name : impeg2d_api_get_buf_info */
727 /* */
728 /* Description : */
729 /* */
730 /* Inputs : */
731 /* Globals : <Does it use any global variables?> */
732 /* Outputs : */
733 /* Returns : void */
734 /* */
735 /* Issues : none */
736 /* */
737 /* Revision History: */
738 /* */
739 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
740 /* 22 10 2008 100356 Draft */
741 /* */
742 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)743 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
744 void *pv_api_ip,
745 void *pv_api_op)
746 {
747 dec_state_t *ps_dec_state;
748 dec_state_multi_core_t *ps_dec_state_multi_core;
749 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
750 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
751 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
752 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
753 UWORD32 u4_i, u4_stride, u4_height;
754 UNUSED(ps_ctl_bufinfo_ip);
755
756 ps_dec_state_multi_core =
757 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
758 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
759
760 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
761 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
762
763 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
764 {
765 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
766 MIN_OUT_BUFS_420;
767 }
768 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
769 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
770 {
771 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
772 MIN_OUT_BUFS_420SP;
773 }
774 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
775 {
776 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
777 MIN_OUT_BUFS_422ILE;
778 }
779 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
780 {
781 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
782 MIN_OUT_BUFS_RGB565;
783 }
784 else
785 {
786 //Invalid chroma format; Error code may be updated, verify in testing if needed
787 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
788 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
789 return IV_FAIL;
790 }
791
792 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
793 {
794 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
795 0;
796 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
797 0;
798 }
799
800 for(u4_i = 0;
801 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
802 u4_i++)
803 {
804 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
805 MAX_BITSTREAM_BUFFER_SIZE;
806 }
807
808 if (0 == ps_dec_state->u4_frm_buf_stride)
809 {
810 if (1 == ps_dec_state->u2_header_done)
811 {
812 u4_stride = ps_dec_state->u2_horizontal_size;
813 }
814 else
815 {
816 u4_stride = ps_dec_state->u2_create_max_width;
817 }
818 }
819 else
820 {
821 u4_stride = ps_dec_state->u4_frm_buf_stride;
822 }
823 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
824
825 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
826 {
827 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
828 (u4_stride * u4_height);
829 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
830 (u4_stride * u4_height) >> 2;
831 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
832 (u4_stride * u4_height) >> 2;
833 }
834 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
835 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
836 {
837 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
838 (u4_stride * u4_height);
839 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
840 (u4_stride * u4_height) >> 1;
841 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 0;
842 }
843 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
844 {
845 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
846 (u4_stride * u4_height) * 2;
847 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
848 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
849 0;
850 }
851
852 /* Adding initialization for 2 uninitialized values */
853 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
854 if(ps_dec_state->u4_share_disp_buf)
855 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
856 NUM_INT_FRAME_BUFFERS;
857 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
858
859 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
860
861 return (IV_SUCCESS);
862 }
863
864 /*****************************************************************************/
865 /* */
866 /* Function Name : impeg2d_api_set_flush_mode */
867 /* */
868 /* Description : */
869 /* */
870 /* Inputs : */
871 /* Globals : <Does it use any global variables?> */
872 /* Outputs : */
873 /* Returns : void */
874 /* */
875 /* Issues : none */
876 /* */
877 /* Revision History: */
878 /* */
879 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
880 /* 08 06 2009 100356 RAVI */
881 /* */
882 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)883 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
884 void *pv_api_ip,
885 void *pv_api_op)
886 {
887 dec_state_t *ps_dec_state;
888 dec_state_multi_core_t *ps_dec_state_multi_core;
889 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
890 (impeg2d_ctl_flush_op_t*)pv_api_op;
891
892 UNUSED(pv_api_ip);
893
894 ps_dec_state_multi_core =
895 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
896 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
897
898 ps_dec_state->u1_flushfrm = 1;
899
900 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
901 sizeof(impeg2d_ctl_flush_op_t);
902 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
903
904 return (IV_SUCCESS);
905 }
906
907 /*****************************************************************************/
908 /* */
909 /* Function Name : impeg2d_api_set_default */
910 /* */
911 /* Description : */
912 /* */
913 /* Inputs : */
914 /* Globals : <Does it use any global variables?> */
915 /* Outputs : */
916 /* Returns : void */
917 /* */
918 /* Issues : none */
919 /* */
920 /* Revision History: */
921 /* */
922 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
923 /* 08 06 2009 100356 RAVI */
924 /* */
925 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)926 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
927 void *pv_api_ip,
928 void *pv_api_op)
929 {
930 dec_state_t *ps_dec_state;
931 dec_state_multi_core_t *ps_dec_state_multi_core;
932 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
933 (impeg2d_ctl_set_config_op_t *)pv_api_op;
934
935 UNUSED(pv_api_ip);
936
937 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
938 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
939 sizeof(impeg2d_ctl_set_config_op_t);
940
941 ps_dec_state_multi_core =
942 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
943 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
944
945 ps_dec_state->u1_flushfrm = 0;
946 ps_dec_state->u2_decode_header = 1;
947
948 if (1 == ps_dec_state->u2_header_done)
949 {
950 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
951 }
952
953 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
954
955 return (IV_SUCCESS);
956
957 }
958
959 /*****************************************************************************/
960 /* */
961 /* Function Name : impeg2d_api_reset */
962 /* */
963 /* Description : */
964 /* */
965 /* Inputs : */
966 /* Globals : <Does it use any global variables?> */
967 /* Outputs : */
968 /* Returns : void */
969 /* */
970 /* Issues : none */
971 /* */
972 /* Revision History: */
973 /* */
974 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
975 /* 08 06 2009 100356 RAVI */
976 /* */
977 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)978 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
979 void *pv_api_ip,
980 void *pv_api_op)
981 {
982 dec_state_t *ps_dec_state;
983 dec_state_multi_core_t *ps_dec_state_multi_core;
984 UNUSED(pv_api_ip);
985 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
986
987 WORD32 i4_num_threads;
988
989 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
990 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
991
992 if(ps_dec_state_multi_core != NULL)
993 {
994 if(ps_dec_state->aps_ref_pics[1] != NULL)
995 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
996 if(ps_dec_state->aps_ref_pics[0] != NULL)
997 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
998 while(1)
999 {
1000 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
1001 if(NULL == ps_disp_pic)
1002 break;
1003 if(0 == ps_dec_state->u4_share_disp_buf)
1004 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
1005
1006 }
1007
1008 if((ps_dec_state->u4_deinterlace) && (NULL != ps_dec_state->ps_deint_pic))
1009 {
1010 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
1011 ps_dec_state->ps_deint_pic->i4_buf_id,
1012 MPEG2_BUF_MGR_DEINT);
1013 }
1014
1015 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1016 {
1017 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1018
1019
1020 /* --------------------------------------------------------------------- */
1021 /* Initializations */
1022
1023 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1024 ps_dec_state->u4_frm_buf_stride = 0;
1025 ps_dec_state->u2_is_mpeg2 = 0;
1026 ps_dec_state->aps_ref_pics[0] = NULL;
1027 ps_dec_state->aps_ref_pics[1] = NULL;
1028 ps_dec_state->ps_deint_pic = NULL;
1029 }
1030 }
1031 else
1032 {
1033 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1034 IMPEG2D_INIT_NOT_DONE;
1035 }
1036
1037 return(IV_SUCCESS);
1038 }
1039
1040 /*****************************************************************************/
1041 /* */
1042 /* Function Name : impeg2d_api_set_params */
1043 /* */
1044 /* Description : */
1045 /* */
1046 /* Inputs : */
1047 /* Globals : <Does it use any global variables?> */
1048 /* Outputs : */
1049 /* Returns : void */
1050 /* */
1051 /* Issues : none */
1052 /* */
1053 /* Revision History: */
1054 /* */
1055 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1056 /* 08 06 2009 100356 RAVI */
1057 /* */
1058 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1059 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1060 {
1061 dec_state_t *ps_dec_state;
1062 dec_state_multi_core_t *ps_dec_state_multi_core;
1063 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1064 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1065
1066 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1067 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1068
1069 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1070 {
1071 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1072 return(IV_FAIL);
1073 }
1074
1075 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1076 {
1077 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1078 return(IV_FAIL);
1079 }
1080
1081 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1082 {
1083 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1084 return(IV_FAIL);
1085 }
1086
1087 if(ps_dec_state->u2_header_done == 1)
1088 {
1089 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1090 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1091 {
1092 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1093 return(IV_FAIL);
1094 }
1095
1096 }
1097
1098
1099 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1100
1101 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1102 {
1103 if(ps_dec_state->u2_header_done == 1)
1104 {
1105 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width)
1106 {
1107 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1108 }
1109 }
1110 else
1111 {
1112 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1113 }
1114
1115 }
1116 else
1117 {
1118
1119 if(ps_dec_state->u2_header_done == 1)
1120 {
1121 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1122 }
1123 else
1124 {
1125 ps_dec_state->u4_frm_buf_stride = 0;
1126 }
1127 }
1128
1129
1130 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1131 {
1132 ps_dec_state->u1_flushfrm = 0;
1133 }
1134
1135
1136 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1137 return(IV_SUCCESS);
1138
1139 }
1140
1141 /*****************************************************************************/
1142 /* */
1143 /* Function Name : impeg2d_api_get_status */
1144 /* */
1145 /* Description : */
1146 /* */
1147 /* Inputs : */
1148 /* Globals : <Does it use any global variables?> */
1149 /* Outputs : */
1150 /* Returns : void */
1151 /* */
1152 /* Issues : none */
1153 /* */
1154 /* Revision History: */
1155 /* */
1156 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1157 /* 08 06 2009 100356 RAVI */
1158 /* */
1159 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1160 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1161 void *pv_api_ip,
1162 void *pv_api_op)
1163 {
1164 dec_state_t *ps_dec_state;
1165 dec_state_multi_core_t *ps_dec_state_multi_core;
1166 UWORD32 u4_i,u4_stride,u4_height;
1167 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1168 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1169 UNUSED(ps_ctl_dec_ip);
1170
1171 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1172 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1173
1174 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1175 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1176 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1177 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1178 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1179
1180
1181 if(ps_dec_state->u2_progressive_sequence == 1)
1182 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1183 else
1184 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1185
1186
1187 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1188 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1189 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1190
1191
1192 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1193 {
1194 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1195 }
1196 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1197 {
1198 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1199 }
1200 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1201 {
1202 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1203 }
1204 else
1205 {
1206 //Invalid chroma format; Error code may be updated, verify in testing if needed
1207 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1208 return IV_FAIL;
1209 }
1210
1211 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1212 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1213
1214 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1215 {
1216 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1217 }
1218
1219 u4_stride = ps_dec_state->u4_frm_buf_stride;
1220 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1221
1222 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1223 {
1224 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1225 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1226 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1227 }
1228 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1229 {
1230 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1231 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1232 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1233 }
1234 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1235 {
1236 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1237 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1238 }
1239
1240 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1241
1242 return(IV_SUCCESS);
1243
1244 }
1245
1246 /**
1247 *******************************************************************************
1248 *
1249 * @brief
1250 * Gets frame dimensions/offsets
1251 *
1252 * @par Description:
1253 * Gets frame buffer chararacteristics such a x & y offsets display and
1254 * buffer dimensions
1255 *
1256 * @param[in] ps_codec_obj
1257 * Pointer to codec object at API level
1258 *
1259 * @param[in] pv_api_ip
1260 * Pointer to input argument structure
1261 *
1262 * @param[out] pv_api_op
1263 * Pointer to output argument structure
1264 *
1265 * @returns Status
1266 *
1267 * @remarks
1268 *
1269 *
1270 *******************************************************************************
1271 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1272 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1273 void *pv_api_ip,
1274 void *pv_api_op)
1275 {
1276 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1277 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1278 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1279 dec_state_t *ps_codec;
1280 dec_state_multi_core_t *ps_dec_state_multi_core;
1281
1282 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1283 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1284
1285
1286 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1287 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1288 UNUSED(ps_ip);
1289 if(ps_codec->u2_header_done)
1290 {
1291 disp_wd = ps_codec->u2_horizontal_size;
1292 disp_ht = ps_codec->u2_vertical_size;
1293
1294 if(0 == ps_codec->u4_share_disp_buf)
1295 {
1296 buffer_wd = disp_wd;
1297 buffer_ht = disp_ht;
1298 }
1299 else
1300 {
1301 buffer_wd = ps_codec->u2_frame_width;
1302 buffer_ht = ps_codec->u2_frame_height;
1303 }
1304 }
1305 else
1306 {
1307
1308 disp_wd = ps_codec->u2_create_max_width;
1309 disp_ht = ps_codec->u2_create_max_height;
1310
1311 if(0 == ps_codec->u4_share_disp_buf)
1312 {
1313 buffer_wd = disp_wd;
1314 buffer_ht = disp_ht;
1315 }
1316 else
1317 {
1318 buffer_wd = ALIGN16(disp_wd);
1319 buffer_ht = ALIGN16(disp_ht);
1320
1321 }
1322 }
1323 if(ps_codec->u2_frame_width > buffer_wd)
1324 buffer_wd = ps_codec->u2_frame_width;
1325
1326 x_offset = 0;
1327 y_offset = 0;
1328
1329
1330 ps_op->u4_disp_wd[0] = disp_wd;
1331 ps_op->u4_disp_ht[0] = disp_ht;
1332 ps_op->u4_buffer_wd[0] = buffer_wd;
1333 ps_op->u4_buffer_ht[0] = buffer_ht;
1334 ps_op->u4_x_offset[0] = x_offset;
1335 ps_op->u4_y_offset[0] = y_offset;
1336
1337 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1338 >> 1);
1339 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1340 >> 1);
1341 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1342 >> 1);
1343 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1344 >> 1);
1345 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1346 >> 1);
1347 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1348 >> 1);
1349
1350 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1351 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1352 {
1353 ps_op->u4_disp_wd[2] = 0;
1354 ps_op->u4_disp_ht[2] = 0;
1355 ps_op->u4_buffer_wd[2] = 0;
1356 ps_op->u4_buffer_ht[2] = 0;
1357 ps_op->u4_x_offset[2] = 0;
1358 ps_op->u4_y_offset[2] = 0;
1359
1360 ps_op->u4_disp_wd[1] <<= 1;
1361 ps_op->u4_buffer_wd[1] <<= 1;
1362 ps_op->u4_x_offset[1] <<= 1;
1363 }
1364
1365 return IV_SUCCESS;
1366
1367 }
1368
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1369 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1370 {
1371 WORD32 i4_cmd;
1372 IV_API_CALL_STATUS_T u4_error_code;
1373 UWORD32 *pu4_api_ip;
1374
1375 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1376 if(IV_SUCCESS != u4_error_code)
1377 {
1378 return u4_error_code;
1379 }
1380
1381
1382 pu4_api_ip = (UWORD32 *)pv_api_ip;
1383 i4_cmd = *(pu4_api_ip + 1);
1384
1385 switch(i4_cmd)
1386 {
1387
1388 case IV_CMD_GET_NUM_MEM_REC:
1389 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1390 break;
1391
1392 case IV_CMD_FILL_NUM_MEM_REC:
1393 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1394 break;
1395
1396 case IV_CMD_INIT:
1397 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1398 break;
1399
1400 case IVD_CMD_SET_DISPLAY_FRAME:
1401 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1402 break;
1403
1404 case IVD_CMD_REL_DISPLAY_FRAME:
1405 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1406 break;
1407
1408 case IVD_CMD_VIDEO_DECODE:
1409 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1410 break;
1411
1412 case IV_CMD_RETRIEVE_MEMREC:
1413 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1414 break;
1415
1416 case IVD_CMD_VIDEO_CTL:
1417 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1418 break;
1419
1420 default:
1421 break;
1422 }
1423
1424 return(u4_error_code);
1425
1426 }
1427
1428 /*****************************************************************************/
1429 /* */
1430 /* Function Name : impeg2d_api_num_mem_rec */
1431 /* */
1432 /* Description : The function get the number mem records library needs */
1433 /* Inputs : Error message */
1434 /* Globals : None */
1435 /* Processing : Just prints error message to console */
1436 /* Outputs : Error mesage to the console */
1437 /* Returns : None */
1438 /* */
1439 /* Issues : <List any issues or problems with this function> */
1440 /* */
1441 /* Revision History: */
1442 /* */
1443 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1444 /* 23 09 2010 Hamsalekha Creation */
1445 /* */
1446 /*****************************************************************************/
1447
1448
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1449 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1450 {
1451 /* To Query No of Memory Records */
1452 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1453 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1454
1455 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1456 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1457
1458 UNUSED(ps_query_mem_rec_ip);
1459 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1460
1461 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1462
1463 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1464
1465
1466 return(IV_SUCCESS);
1467
1468 }
1469
1470
1471 /*****************************************************************************/
1472 /* */
1473 /* Function Name : impeg2d_api_fill_mem_rec */
1474 /* */
1475 /* Description : Thsi functions fills details of each mem record lib needs*/
1476 /* Inputs : Error message */
1477 /* Globals : None */
1478 /* Processing : Just prints error message to console */
1479 /* Outputs : Error mesage to the console */
1480 /* Returns : None */
1481 /* */
1482 /* Issues : <List any issues or problems with this function> */
1483 /* */
1484 /* Revision History: */
1485 /* */
1486 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1487 /* 23 09 2010 Hamsalekha Creation */
1488 /* */
1489 /*****************************************************************************/
1490
1491
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1492 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1493 {
1494
1495 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1496 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1497
1498
1499 ps_mem_q_ip = pv_api_ip;
1500 ps_mem_q_op = pv_api_op;
1501
1502
1503 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1504 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1505
1506
1507 return(IV_SUCCESS);
1508
1509 }
1510
1511
1512
1513 /*****************************************************************************/
1514 /* */
1515 /* Function Name : impeg2d_api_init */
1516 /* */
1517 /* Description : */
1518 /* Inputs : */
1519 /* Globals : */
1520 /* Processing : */
1521 /* Outputs : */
1522 /* Returns : */
1523 /* */
1524 /* Issues : */
1525 /* */
1526 /* Revision History: */
1527 /* */
1528 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1529 /* 17 09 2007 Rajendra C Y Draft */
1530 /* */
1531 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1532 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1533 void *ps_ip,
1534 void *ps_op)
1535 {
1536 UWORD32 i;
1537
1538 void *pv;
1539 UWORD32 u4_size;
1540
1541 dec_state_t *ps_dec_state;
1542 dec_state_multi_core_t *ps_dec_state_multi_core;
1543 UWORD32 u4_num_mem_rec;
1544 iv_mem_rec_t *ps_mem_rec ;
1545 iv_mem_rec_t *ps_frm_buf;
1546 iv_obj_t *ps_dec_handle;
1547 WORD32 i4_max_wd, i4_max_ht;
1548
1549 impeg2d_init_ip_t *ps_dec_init_ip;
1550 impeg2d_init_op_t *ps_dec_init_op;
1551 WORD32 i4_num_threads;
1552 UWORD32 u4_share_disp_buf, u4_chroma_format;
1553 UWORD32 u4_deinterlace;
1554
1555 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1556 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1557
1558 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1559 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1560
1561 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1562 {
1563 #ifndef LOGO_EN
1564 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1565 #else
1566 u4_share_disp_buf = 0;
1567 #endif
1568 }
1569 else
1570 {
1571 u4_share_disp_buf = 0;
1572 }
1573
1574 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1575
1576 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1577 {
1578 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1579 }
1580 else
1581 {
1582 u4_deinterlace = 0;
1583 }
1584
1585 if( (u4_chroma_format != IV_YUV_420P) &&
1586 (u4_chroma_format != IV_YUV_420SP_UV) &&
1587 (u4_chroma_format != IV_YUV_420SP_VU))
1588 {
1589 u4_share_disp_buf = 0;
1590 }
1591
1592 /* Disable deinterlacer in shared mode */
1593 if(u4_share_disp_buf)
1594 {
1595 u4_deinterlace = 0;
1596 }
1597
1598 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1599 ps_mem_rec ++;
1600
1601
1602 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1603
1604
1605 /* Except memTab[0], all other memTabs are initialized to zero */
1606 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1607 {
1608 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1609 ps_mem_rec++;
1610 }
1611
1612 /* Reinitializing memTab[0] memory base address */
1613 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1614
1615
1616 /* memTab[0] is for codec Handle,redundant currently not being used */
1617 ps_dec_handle = ps_mem_rec->pv_base;
1618 u4_num_mem_rec = 1;
1619 ps_mem_rec++;
1620
1621
1622
1623
1624
1625 /* decoder handle */
1626 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1627 u4_num_mem_rec++;
1628 ps_mem_rec++;
1629
1630
1631 {
1632 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1633
1634 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1635 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1636 }
1637
1638
1639 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1640 {
1641 /*************************************************************************/
1642 /* For MPEG2 Decoder Context */
1643 /*************************************************************************/
1644 ps_dec_state = ps_mem_rec->pv_base;
1645
1646 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1647
1648 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1649
1650 ps_dec_state->i4_num_cores = 1;
1651 /* @ */ /* Used for storing MemRecords */
1652 u4_num_mem_rec++;
1653 ps_mem_rec++;
1654
1655 /* Thread handle */
1656 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1657 u4_num_mem_rec++;
1658 ps_mem_rec++;
1659
1660 /*************************************************************************/
1661 /* For Motion Compensation Buffers */
1662 /*************************************************************************/
1663 pv = ps_mem_rec->pv_base;
1664
1665 /* for mc_fw_buf.pu1_y */
1666
1667 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1668 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1669
1670 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1671 /* for mc_fw_buf.pu1_u */
1672
1673 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1674 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1675
1676 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1677
1678 /* for mc_fw_buf.pu1_v */
1679
1680 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1681 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1682
1683 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1684
1685 /* for mc_bk_buf.pu1_y */
1686
1687 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1688 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1689
1690 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1691
1692 /* for mc_bk_buf.pu1_u */
1693
1694 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1695 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1696
1697 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1698
1699 /* for mc_bk_buf.pu1_v */
1700
1701 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1702 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1703
1704 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1705
1706 /* for mc_buf.pu1_y */
1707
1708 ps_dec_state->s_mc_buf.pu1_y = pv;
1709 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1710
1711 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1712
1713 /* for mc_buf.pu1_u */
1714
1715 ps_dec_state->s_mc_buf.pu1_u = pv;
1716 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1717
1718 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1719
1720 /* for mc_buf.pu1_v */
1721
1722 ps_dec_state->s_mc_buf.pu1_v = pv;
1723
1724 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1725
1726 u4_num_mem_rec++;
1727 ps_mem_rec++;
1728
1729
1730
1731 ps_dec_state->pv_pic_buf_mg = 0;
1732
1733 /*************************************************************************/
1734 /* For saving stack context to support global error handling */
1735 /*************************************************************************/
1736 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1737 u4_num_mem_rec++;
1738 ps_mem_rec++;
1739
1740 }
1741
1742
1743
1744
1745
1746 /*************************************************************************/
1747 /* For Picture Buffer Manager */
1748 /*************************************************************************/
1749 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1750
1751 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1752 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1753
1754 u4_num_mem_rec++;
1755 ps_mem_rec++;
1756
1757
1758
1759 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1760 {
1761
1762 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1763
1764
1765 /* --------------------------------------------------------------------- */
1766 /* Initializations */
1767
1768 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1769
1770
1771 {
1772 UWORD32 u4_max_frm_width,u4_max_frm_height;
1773
1774 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1775 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1776
1777 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1778 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1779
1780 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1781 ps_dec_state->u4_frm_buf_stride = 0 ;
1782 ps_dec_state->u2_frame_width = u4_max_frm_width;
1783 ps_dec_state->u2_picture_width = u4_max_frm_width;
1784 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1785
1786 ps_dec_state->u2_frame_height = u4_max_frm_height;
1787 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1788 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1789 ps_dec_state->u4_deinterlace = u4_deinterlace;
1790 ps_dec_state->ps_deint_pic = NULL;
1791 }
1792 }
1793
1794
1795 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1796
1797 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1798 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1799 {
1800 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1801 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1802 return(IV_FAIL);
1803
1804
1805 }
1806
1807 /* --------------------------------------------------------------------- */
1808
1809
1810 /* ! */
1811 // picture buffer manager initialization will be done only for first thread
1812 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1813 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1814
1815 /*************************************************************************/
1816 /* Internal Frame Buffers */
1817 /*************************************************************************/
1818
1819
1820 /* Set first frame to grey */
1821 {
1822 ps_frm_buf = ps_mem_rec;
1823 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1824 ps_frm_buf++;
1825 }
1826
1827 if(0 == ps_dec_state->u4_share_disp_buf)
1828 {
1829 pic_buf_t *ps_pic_buf;
1830 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1831 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1832 {
1833 UWORD8 *pu1_buf;
1834 pu1_buf = ps_mem_rec->pv_base;
1835
1836 ps_pic_buf->pu1_y = pu1_buf;
1837 pu1_buf += i4_max_ht * i4_max_wd;
1838
1839 ps_pic_buf->pu1_u = pu1_buf;
1840 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1841
1842 ps_pic_buf->pu1_v = pu1_buf;
1843 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1844
1845 ps_pic_buf->i4_buf_id = i;
1846
1847 ps_pic_buf->u1_used_as_ref = 0;
1848
1849 ps_pic_buf->u4_ts = 0;
1850
1851 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1852 ps_mem_rec++;
1853 ps_pic_buf++;
1854 }
1855 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1856 }
1857 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1858 {
1859 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1860 {
1861 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1862 ps_mem_rec++;
1863 }
1864
1865 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1866 }
1867 else
1868 {
1869 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1870 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1871 }
1872
1873
1874 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1875
1876
1877 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1878 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1879 ps_mem_rec++;
1880
1881 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1882 {
1883 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1884 return(IV_FAIL);
1885
1886 }
1887
1888 ps_dec_state->u1_flushfrm = 0;
1889 ps_dec_state->u1_flushcnt = 0;
1890 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1891
1892
1893 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
1894 ps_mem_rec++;
1895
1896 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
1897 ps_mem_rec++;
1898
1899
1900 /*************************************************************************/
1901 /* Last MemTab is used for storing TabRecords */
1902 /*************************************************************************/
1903 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1904 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1905 /* Updating in Decoder Context with memRecords */
1906 u4_num_mem_rec++;
1907 ps_mem_rec++;
1908 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1909
1910
1911 ps_dec_state->u4_num_frames_decoded = 0;
1912 ps_dec_state->aps_ref_pics[0] = NULL;
1913 ps_dec_state->aps_ref_pics[1] = NULL;
1914
1915 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1916
1917 impeg2d_init_arch(ps_dec_state);
1918
1919 impeg2d_init_function_ptr(ps_dec_state);
1920
1921 return(IV_SUCCESS);
1922 }
1923
1924 /*****************************************************************************/
1925 /* */
1926 /* Function Name : impeg2d_api_retrieve_mem_rec */
1927 /* */
1928 /* Description : */
1929 /* */
1930 /* Inputs : */
1931 /* Globals : <Does it use any global variables?> */
1932 /* Outputs : */
1933 /* Returns : void */
1934 /* */
1935 /* Issues : none */
1936 /* */
1937 /* Revision History: */
1938 /* */
1939 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1940 /* 22 10 2008 100356 Draft */
1941 /* */
1942 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1943 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
1944 void *pv_api_ip,
1945 void *pv_api_op)
1946 {
1947 UWORD32 u4_i;
1948 dec_state_t *ps_dec_state;
1949 dec_state_multi_core_t *ps_dec_state_multi_core;
1950 iv_mem_rec_t *ps_mem_rec;
1951 iv_mem_rec_t *ps_temp_rec;
1952
1953
1954
1955 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
1956 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
1957
1958 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
1959 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
1960
1961 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
1962 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1963 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1964 ps_temp_rec = ps_dec_state->pv_memTab;
1965
1966 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
1967 {
1968 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
1969 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
1970 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
1971 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
1972 }
1973
1974 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1975 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
1976
1977 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
1978 IMPEG2D_PRINT_STATISTICS();
1979
1980
1981 return(IV_SUCCESS);
1982
1983 }
1984
1985 /*****************************************************************************/
1986 /* */
1987 /* Function Name : impeg2d_api_ctl */
1988 /* */
1989 /* Description : */
1990 /* */
1991 /* Inputs : */
1992 /* Globals : <Does it use any global variables?> */
1993 /* Outputs : */
1994 /* Returns : void */
1995 /* */
1996 /* Issues : none */
1997 /* */
1998 /* Revision History: */
1999 /* */
2000 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2001 /* 22 10 2008 100356 Draft */
2002 /* */
2003 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2004 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2005 void *pv_api_ip,
2006 void *pv_api_op)
2007 {
2008 WORD32 i4_sub_cmd;
2009 UWORD32 *pu4_api_ip;
2010 IV_API_CALL_STATUS_T u4_error_code;
2011
2012 pu4_api_ip = (UWORD32 *)pv_api_ip;
2013 i4_sub_cmd = *(pu4_api_ip + 2);
2014
2015 switch(i4_sub_cmd)
2016 {
2017 case IVD_CMD_CTL_GETPARAMS:
2018 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2019 (void *)pv_api_op);
2020 break;
2021
2022 case IVD_CMD_CTL_SETPARAMS:
2023 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2024 (void *)pv_api_op);
2025 break;
2026
2027 case IVD_CMD_CTL_RESET:
2028 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2029 (void *)pv_api_op);
2030 break;
2031
2032 case IVD_CMD_CTL_SETDEFAULT:
2033 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2034 (void *)pv_api_ip,
2035 (void *)pv_api_op);
2036 break;
2037
2038 case IVD_CMD_CTL_FLUSH:
2039 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2040 (void *)pv_api_ip,
2041 (void *)pv_api_op);
2042 break;
2043
2044 case IVD_CMD_CTL_GETBUFINFO:
2045 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2046 (void *)pv_api_ip,
2047 (void *)pv_api_op);
2048 break;
2049
2050 case IVD_CMD_CTL_GETVERSION:
2051 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2052 (void *)pv_api_op);
2053 break;
2054
2055 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2056 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2057 (void *)pv_api_ip,
2058 (void *)pv_api_op);
2059 break;
2060
2061 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2062 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2063 (void *)pv_api_ip,
2064 (void *)pv_api_op);
2065 break;
2066
2067 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2068 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2069 (void *)pv_api_ip,
2070 (void *)pv_api_op);
2071 break;
2072
2073 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2074 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2075 (void *)pv_api_op);
2076 break;
2077
2078 default:
2079 u4_error_code = IV_FAIL;
2080 break;
2081 }
2082
2083 return (u4_error_code);
2084
2085 }
2086
2087 /*****************************************************************************/
2088 /* */
2089 /* Function Name : impeg2d_api_check_struct_sanity */
2090 /* */
2091 /* Description : */
2092 /* */
2093 /* Inputs : */
2094 /* Globals : <Does it use any global variables?> */
2095 /* Outputs : */
2096 /* Returns : void */
2097 /* */
2098 /* Issues : none */
2099 /* */
2100 /* Revision History: */
2101 /* */
2102 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2103 /* 22 10 2008 100356 Draft */
2104 /* */
2105 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2106 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2107 void *pv_api_ip,
2108 void *pv_api_op)
2109 {
2110 WORD32 i4_cmd;
2111 UWORD32 *pu4_api_ip;
2112 UWORD32 *pu4_api_op;
2113 WORD32 i,j;
2114
2115 if(NULL == pv_api_op)
2116 return(IV_FAIL);
2117
2118 if(NULL == pv_api_ip)
2119 return(IV_FAIL);
2120
2121 pu4_api_ip = (UWORD32 *)pv_api_ip;
2122 pu4_api_op = (UWORD32 *)pv_api_op;
2123 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2124
2125 /* error checks on handle */
2126 switch(i4_cmd)
2127 {
2128 case IV_CMD_GET_NUM_MEM_REC:
2129 case IV_CMD_FILL_NUM_MEM_REC:
2130 break;
2131 case IV_CMD_INIT:
2132 if(ps_handle == NULL)
2133 {
2134 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2135 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2136 return IV_FAIL;
2137 }
2138
2139 if(ps_handle->u4_size != sizeof(iv_obj_t))
2140 {
2141 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2142 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2143 return IV_FAIL;
2144 }
2145 break;
2146 case IVD_CMD_GET_DISPLAY_FRAME:
2147 case IVD_CMD_VIDEO_DECODE:
2148 case IV_CMD_RETRIEVE_MEMREC:
2149 case IVD_CMD_SET_DISPLAY_FRAME:
2150 case IVD_CMD_REL_DISPLAY_FRAME:
2151 case IVD_CMD_VIDEO_CTL:
2152 {
2153 if(ps_handle == NULL)
2154 {
2155 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2156 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2157 return IV_FAIL;
2158 }
2159
2160 if(ps_handle->u4_size != sizeof(iv_obj_t))
2161 {
2162 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2163 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2164 return IV_FAIL;
2165 }
2166 if(ps_handle->pv_fxns != impeg2d_api_function)
2167 {
2168 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2169 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2170 return IV_FAIL;
2171 }
2172
2173 if(ps_handle->pv_codec_handle == NULL)
2174 {
2175 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2176 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2177 return IV_FAIL;
2178 }
2179 }
2180 break;
2181 default:
2182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2183 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2184 return IV_FAIL;
2185 }
2186
2187 switch(i4_cmd)
2188 {
2189 case IV_CMD_GET_NUM_MEM_REC:
2190 {
2191 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2192 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2193 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2194
2195 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2196 {
2197 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2198 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2199 return(IV_FAIL);
2200 }
2201
2202 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2203 {
2204 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2205 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2206 return(IV_FAIL);
2207 }
2208 }
2209 break;
2210 case IV_CMD_FILL_NUM_MEM_REC:
2211 {
2212 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2213 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2214 iv_mem_rec_t *ps_mem_rec;
2215
2216 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2217
2218 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2219 {
2220 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2221 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2222 return(IV_FAIL);
2223 }
2224
2225 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2226 {
2227 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2228 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2229 return(IV_FAIL);
2230 }
2231
2232 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2233 {
2234 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2235 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2236 return(IV_FAIL);
2237 }
2238
2239 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2240 {
2241 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2242 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2243 return(IV_FAIL);
2244 }
2245
2246 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2247 {
2248 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2249 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2250 return(IV_FAIL);
2251 }
2252
2253 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2254 {
2255 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2256 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2257 return(IV_FAIL);
2258 }
2259
2260 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2261 {
2262 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2263 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2264 return(IV_FAIL);
2265 }
2266
2267 /* check memrecords sizes are correct */
2268 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2269 for(i=0;i<NUM_MEM_RECORDS;i++)
2270 {
2271 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2272 {
2273 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2274 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2275 return IV_FAIL;
2276 }
2277 }
2278 }
2279 break;
2280
2281 case IV_CMD_INIT:
2282 {
2283 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2284 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2285 iv_mem_rec_t *ps_mem_rec;
2286 UWORD32 u4_tot_num_mem_recs;
2287
2288 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2289
2290 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2291 {
2292 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2293 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2294 return(IV_FAIL);
2295 }
2296
2297 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2298 {
2299 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2300 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2301 return(IV_FAIL);
2302 }
2303
2304 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2305
2306
2307
2308
2309 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2310 {
2311 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2312 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2313 return(IV_FAIL);
2314 }
2315
2316 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2317 {
2318 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2319 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2320 return(IV_FAIL);
2321 }
2322
2323 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2324 {
2325 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2326 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2327 return(IV_FAIL);
2328 }
2329
2330 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2331 {
2332 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2333 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2334 return(IV_FAIL);
2335 }
2336
2337 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2338 {
2339 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2340 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2341 return(IV_FAIL);
2342 }
2343
2344 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2345 {
2346 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2347 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2348 return(IV_FAIL);
2349 }
2350
2351 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2352 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2353 {
2354 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2355 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2356 return(IV_FAIL);
2357 }
2358
2359 /* verify number of mem records */
2360 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2361 {
2362 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2363 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2364 return IV_FAIL;
2365 }
2366
2367 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2368 /* verify wether first memrecord is handle or not */
2369 /*
2370 if(ps_mem_rec->pv_base != ps_handle)
2371 {
2372 // indicate the incorrect handle error
2373 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2374 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2375 return IV_FAIL;
2376 }
2377 */
2378 /* check memrecords sizes are correct */
2379 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2380 {
2381 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2382 {
2383 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2384 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2385 return IV_FAIL;
2386 }
2387 }
2388
2389 /* verify memtabs for overlapping regions */
2390 {
2391 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2392 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2393
2394
2395 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2396 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2397 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2398 {
2399 /* This array is populated to check memtab overlapp */
2400 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2401 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2402
2403 for(j = 0; j < i; j++)
2404 {
2405 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2406 {
2407 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2408 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2409 return IV_FAIL;
2410 }
2411
2412 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2413 {
2414 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2415 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2416 return IV_FAIL;
2417 }
2418
2419 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2420 {
2421 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2422 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2423 return IV_FAIL;
2424 }
2425 }
2426 }
2427 }
2428
2429
2430
2431
2432 {
2433 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2434
2435 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2436 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2437 IV_API_CALL_STATUS_T e_status;
2438 WORD32 i4_num_memrec;
2439 {
2440
2441 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2442 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2443
2444
2445 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2446 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2447
2448 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2449 impeg2d_api_function(NULL,
2450 (void *)&s_no_of_mem_rec_query_ip,
2451 (void *)&s_no_of_mem_rec_query_op);
2452
2453 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2454
2455
2456
2457 }
2458
2459
2460 /* initialize mem records array with sizes */
2461 for(i = 0; i < i4_num_memrec; i++)
2462 {
2463 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2464 }
2465
2466 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2467 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2468 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2469 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2470 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2471 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2472 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2473 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2474
2475
2476 e_status = impeg2d_api_function(NULL,
2477 (void *)&s_fill_mem_rec_ip,
2478 (void *)&s_fill_mem_rec_op);
2479 if(IV_FAIL == e_status)
2480 {
2481 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2482 return(IV_FAIL);
2483 }
2484
2485
2486
2487 for(i = 0; i < i4_num_memrec; i ++)
2488 {
2489 if(ps_mem_rec[i].pv_base == NULL)
2490 {
2491 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2492 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2493 return IV_FAIL;
2494 }
2495 #ifdef CHECK_ALIGN
2496
2497 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2498 {
2499 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2500 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2501 return IV_FAIL;
2502 }
2503 #endif //CHECK_ALIGN
2504 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2505 {
2506 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2507 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2508 return IV_FAIL;
2509 }
2510
2511 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2512 {
2513 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2514 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2515 return IV_FAIL;
2516 }
2517
2518 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2519 {
2520 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2521 {
2522 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2523 {
2524 continue;
2525 }
2526 }
2527 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2528 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2529 return IV_FAIL;
2530 }
2531 }
2532 }
2533
2534
2535 }
2536 break;
2537
2538 case IVD_CMD_GET_DISPLAY_FRAME:
2539 {
2540 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2541 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2542
2543 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2544
2545 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2546 {
2547 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2548 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2549 return(IV_FAIL);
2550 }
2551
2552 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2553 {
2554 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2555 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2556 return(IV_FAIL);
2557 }
2558
2559 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2560 {
2561 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2562 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2563 return IV_FAIL;
2564 }
2565
2566 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2567 {
2568 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2569 {
2570 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2571 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2572 return IV_FAIL;
2573 }
2574
2575 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2576 {
2577 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2578 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2579 return IV_FAIL;
2580 }
2581 /*
2582 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2583 {
2584 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2585 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2586 return IV_FAIL;
2587 }
2588 */
2589 }
2590 }
2591 break;
2592 case IVD_CMD_REL_DISPLAY_FRAME:
2593 {
2594 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2595 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2596
2597 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2598
2599 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2600 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2601 {
2602 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2603 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2604 return(IV_FAIL);
2605 }
2606
2607 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2608 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2609 {
2610 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2611 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2612 return(IV_FAIL);
2613 }
2614
2615 }
2616 break;
2617
2618
2619 case IVD_CMD_SET_DISPLAY_FRAME:
2620 {
2621 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2622 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2623 UWORD32 j, i;
2624
2625 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2626
2627 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2628 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2629 {
2630 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2631 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2632 return(IV_FAIL);
2633 }
2634
2635 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2636 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2637 {
2638 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2639 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2640 return(IV_FAIL);
2641 }
2642
2643 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2644 {
2645 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2646 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2647 return IV_FAIL;
2648 }
2649
2650 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2651 {
2652 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2653 {
2654 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2655 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2656 return IV_FAIL;
2657 }
2658
2659 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2660 {
2661 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2662 {
2663 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2664 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2665 return IV_FAIL;
2666 }
2667
2668 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2669 {
2670 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2671 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2672 return IV_FAIL;
2673 }
2674 }
2675 }
2676 }
2677 break;
2678
2679 case IVD_CMD_VIDEO_DECODE:
2680 {
2681 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2682 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2683
2684 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2685
2686 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2687 {
2688 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2689 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2690 return(IV_FAIL);
2691 }
2692
2693 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2694 {
2695 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2696 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2697 return(IV_FAIL);
2698 }
2699
2700 }
2701 break;
2702
2703 case IV_CMD_RETRIEVE_MEMREC:
2704 {
2705 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2706 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2707 iv_mem_rec_t *ps_mem_rec;
2708
2709 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2710
2711 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2712 {
2713 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2714 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2715 return(IV_FAIL);
2716 }
2717
2718 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2719 {
2720 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2721 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2722 return(IV_FAIL);
2723 }
2724
2725 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2726 /* check memrecords sizes are correct */
2727 for(i=0;i < NUM_MEM_RECORDS ; i++)
2728 {
2729 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2730 {
2731 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2732 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2733 return IV_FAIL;
2734 }
2735 }
2736 }
2737 break;
2738
2739 case IVD_CMD_VIDEO_CTL:
2740 {
2741 UWORD32 *pu4_ptr_cmd;
2742 UWORD32 u4_sub_command;
2743
2744 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2745 pu4_ptr_cmd += 2;
2746 u4_sub_command = *pu4_ptr_cmd;
2747
2748 switch(u4_sub_command)
2749 {
2750 case IVD_CMD_CTL_SETPARAMS:
2751 {
2752 impeg2d_ctl_set_config_ip_t *ps_ip;
2753 impeg2d_ctl_set_config_op_t *ps_op;
2754 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2755 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2756
2757 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2758
2759 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2760 {
2761 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2762 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2763 return IV_FAIL;
2764 }
2765 }
2766 case IVD_CMD_CTL_SETDEFAULT:
2767 {
2768 impeg2d_ctl_set_config_op_t *ps_op;
2769 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2770 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2771
2772 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2773 {
2774 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2775 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2776 return IV_FAIL;
2777 }
2778 }
2779 break;
2780
2781 case IVD_CMD_CTL_GETPARAMS:
2782 {
2783 impeg2d_ctl_getstatus_ip_t *ps_ip;
2784 impeg2d_ctl_getstatus_op_t *ps_op;
2785
2786 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2787 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2788
2789 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2790
2791 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2792 {
2793 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2794 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2795 return IV_FAIL;
2796 }
2797 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2798 {
2799 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2800 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2801 return IV_FAIL;
2802 }
2803 }
2804 break;
2805
2806 case IVD_CMD_CTL_GETBUFINFO:
2807 {
2808 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2809 impeg2d_ctl_getbufinfo_op_t *ps_op;
2810 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2811 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2812
2813 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2814
2815 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2816 {
2817 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2818 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2819 return IV_FAIL;
2820 }
2821 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2822 {
2823 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2824 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2825 return IV_FAIL;
2826 }
2827 }
2828 break;
2829
2830 case IVD_CMD_CTL_GETVERSION:
2831 {
2832 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2833 impeg2d_ctl_getversioninfo_op_t *ps_op;
2834 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2835 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2836
2837 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2838
2839 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2840 {
2841 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2842 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2843 return IV_FAIL;
2844 }
2845 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2846 {
2847 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2848 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2849 return IV_FAIL;
2850 }
2851 }
2852 break;
2853
2854 case IVD_CMD_CTL_FLUSH:
2855 {
2856 impeg2d_ctl_flush_ip_t *ps_ip;
2857 impeg2d_ctl_flush_op_t *ps_op;
2858 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2859 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2860
2861 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2862
2863 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2864 {
2865 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2866 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2867 return IV_FAIL;
2868 }
2869 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2870 {
2871 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2872 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2873 return IV_FAIL;
2874 }
2875 }
2876 break;
2877
2878 case IVD_CMD_CTL_RESET:
2879 {
2880 impeg2d_ctl_reset_ip_t *ps_ip;
2881 impeg2d_ctl_reset_op_t *ps_op;
2882 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2883 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2884
2885 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2886
2887 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2888 {
2889 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2890 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2891 return IV_FAIL;
2892 }
2893 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2894 {
2895 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2896 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2897 return IV_FAIL;
2898 }
2899 }
2900 break;
2901
2902 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2903 {
2904 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2905 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2906
2907 ps_ip =
2908 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2909 ps_op =
2910 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2911
2912 if(ps_ip->u4_size
2913 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2914 {
2915 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2916 ps_op->u4_error_code |=
2917 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2918 return IV_FAIL;
2919 }
2920
2921 if(ps_op->u4_size
2922 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2923 {
2924 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2925 ps_op->u4_error_code |=
2926 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2927 return IV_FAIL;
2928 }
2929
2930 break;
2931 }
2932 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2933 {
2934 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
2935 impeg2d_ctl_get_seq_info_op_t *ps_op;
2936
2937 ps_ip =
2938 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
2939 ps_op =
2940 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
2941
2942 if(ps_ip->u4_size
2943 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
2944 {
2945 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2946 ps_op->u4_error_code |=
2947 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2948 return IV_FAIL;
2949 }
2950
2951 if(ps_op->u4_size
2952 != sizeof(impeg2d_ctl_get_seq_info_op_t))
2953 {
2954 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2955 ps_op->u4_error_code |=
2956 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2957 return IV_FAIL;
2958 }
2959
2960 break;
2961 }
2962 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2963 {
2964 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
2965 impeg2d_ctl_set_num_cores_op_t *ps_op;
2966
2967 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
2968 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
2969
2970 if(ps_ip->u4_size
2971 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
2972 {
2973 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2974 ps_op->u4_error_code |=
2975 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2976 return IV_FAIL;
2977 }
2978
2979 if(ps_op->u4_size
2980 != sizeof(impeg2d_ctl_set_num_cores_op_t))
2981 {
2982 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2983 ps_op->u4_error_code |=
2984 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2985 return IV_FAIL;
2986 }
2987
2988 #ifdef MULTICORE
2989 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
2990 #else
2991 if(ps_ip->u4_num_cores != 1)
2992 #endif
2993 {
2994 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2995 return IV_FAIL;
2996 }
2997 break;
2998 }
2999 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3000 {
3001 impeg2d_ctl_set_processor_ip_t *ps_ip;
3002 impeg2d_ctl_set_processor_op_t *ps_op;
3003
3004 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3005 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3006
3007 if(ps_ip->u4_size
3008 != sizeof(impeg2d_ctl_set_processor_ip_t))
3009 {
3010 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3011 ps_op->u4_error_code |=
3012 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3013 return IV_FAIL;
3014 }
3015
3016 if(ps_op->u4_size
3017 != sizeof(impeg2d_ctl_set_processor_op_t))
3018 {
3019 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3020 ps_op->u4_error_code |=
3021 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3022 return IV_FAIL;
3023 }
3024
3025 break;
3026 }
3027 default:
3028 break;
3029
3030 }
3031 }
3032 break;
3033
3034 default:
3035 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3036 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3037 return IV_FAIL;
3038 }
3039
3040
3041 }
3042
3043 return IV_SUCCESS;
3044 }
3045
3046 /*****************************************************************************/
3047 /* */
3048 /* Function Name : impeg2d_api_entity */
3049 /* */
3050 /* Description : */
3051 /* */
3052 /* Inputs : */
3053 /* Globals : <Does it use any global variables?> */
3054 /* Outputs : */
3055 /* Returns : void */
3056 /* */
3057 /* Issues : none */
3058 /* */
3059 /* Revision History: */
3060 /* */
3061 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3062 /* 22 10 2008 100356 Draft */
3063 /* */
3064 /*****************************************************************************/
3065
3066
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3067 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3068 void *pv_api_ip,
3069 void *pv_api_op)
3070 {
3071 iv_obj_t *ps_dec_handle;
3072 dec_state_t *ps_dec_state;
3073 dec_state_multi_core_t *ps_dec_state_multi_core;
3074
3075 impeg2d_video_decode_ip_t *ps_dec_ip;
3076
3077 impeg2d_video_decode_op_t *ps_dec_op;
3078 WORD32 bytes_remaining;
3079 pic_buf_t *ps_disp_pic;
3080
3081
3082
3083 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3084 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3085
3086 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3087
3088 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3089 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3090 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3091
3092 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3093
3094 if(ps_dechdl == NULL)
3095 {
3096 return(IV_FAIL);
3097 }
3098
3099
3100
3101 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3102 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3103
3104 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3105 if(0 == ps_dec_state->u4_share_disp_buf)
3106 {
3107 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3108 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3109 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3110 }
3111
3112 ps_dec_state->ps_disp_pic = NULL;
3113 ps_dec_state->i4_frame_decoded = 0;
3114 /*rest bytes consumed */
3115 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3116
3117 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3118
3119 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3120 {
3121 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3122 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3123 return IV_FAIL;
3124 }
3125
3126
3127 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3128 {
3129 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3130 return(IV_FAIL);
3131 }
3132
3133 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3134 {
3135 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3136 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3137 }
3138
3139 if((1 != ps_dec_state->u2_decode_header) &&
3140 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3141 {
3142 if(ps_dec_state->u1_flushfrm)
3143 {
3144 if(ps_dec_state->aps_ref_pics[1] != NULL)
3145 {
3146 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3147 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3148 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3149
3150 ps_dec_state->aps_ref_pics[1] = NULL;
3151 ps_dec_state->aps_ref_pics[0] = NULL;
3152
3153 }
3154 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3155 {
3156 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3157 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3158
3159 ps_dec_state->aps_ref_pics[0] = NULL;
3160 }
3161 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3162 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3163
3164 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3165
3166 ps_dec_state->ps_disp_pic = ps_disp_pic;
3167 if(ps_disp_pic == NULL)
3168 {
3169 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3170 }
3171 else
3172 {
3173 WORD32 fmt_conv;
3174 if(0 == ps_dec_state->u4_share_disp_buf)
3175 {
3176 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3177 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3178 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3179 fmt_conv = 1;
3180 }
3181 else
3182 {
3183 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3184 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3185 {
3186 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3187 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3188 fmt_conv = 0;
3189 }
3190 else
3191 {
3192 UWORD8 *pu1_buf;
3193
3194 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3195 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3196
3197 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3198 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3199 fmt_conv = 1;
3200 }
3201 }
3202
3203 if(fmt_conv == 1)
3204 {
3205 iv_yuv_buf_t *ps_dst;
3206
3207
3208 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3209 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3210 {
3211 impeg2d_deinterlace(ps_dec_state,
3212 ps_disp_pic,
3213 ps_dst,
3214 0,
3215 ps_dec_state->u2_vertical_size);
3216
3217 }
3218 else
3219 {
3220 impeg2d_format_convert(ps_dec_state,
3221 ps_disp_pic,
3222 ps_dst,
3223 0,
3224 ps_dec_state->u2_vertical_size);
3225 }
3226 }
3227
3228 if(ps_dec_state->u4_deinterlace)
3229 {
3230 if(ps_dec_state->ps_deint_pic)
3231 {
3232 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3233 ps_dec_state->ps_deint_pic->i4_buf_id,
3234 MPEG2_BUF_MGR_DEINT);
3235 }
3236 ps_dec_state->ps_deint_pic = ps_disp_pic;
3237 }
3238 if(0 == ps_dec_state->u4_share_disp_buf)
3239 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3240
3241 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3242 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3243 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3244
3245 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3246 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3247
3248 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3249
3250 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3251
3252 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3253
3254 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3255 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3256 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3257
3258 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3259 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3260 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3261
3262 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3263 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3264 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3265 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3266
3267 switch(ps_dec_state->i4_chromaFormat)
3268 {
3269 case IV_YUV_420SP_UV:
3270 case IV_YUV_420SP_VU:
3271 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3272 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3273 break;
3274 case IV_YUV_422ILE:
3275 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3276 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3277 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3278 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3279 break;
3280 default:
3281 break;
3282 }
3283
3284
3285 }
3286 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3287 {
3288 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3289 {
3290 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3291 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3292 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3293 ps_dec_state->u4_frm_buf_stride,
3294 ps_dec_state->u2_horizontal_size,
3295 ps_dec_state->u2_vertical_size,
3296 ps_dec_state->i4_chromaFormat,
3297 ps_dec_state->u2_horizontal_size,
3298 ps_dec_state->u2_vertical_size);
3299 }
3300 return(IV_SUCCESS);
3301 }
3302 else
3303 {
3304 ps_dec_state->u1_flushfrm = 0;
3305
3306 return(IV_FAIL);
3307 }
3308
3309 }
3310 else if(ps_dec_state->u1_flushfrm==0)
3311 {
3312 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3313 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3314 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3315 {
3316 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3317 return(IV_FAIL);
3318 }
3319
3320 if(1 == ps_dec_state->u4_share_disp_buf)
3321 {
3322 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3323 {
3324 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3325 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3326 return IV_FAIL;
3327 }
3328 }
3329
3330
3331 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3332
3333 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3334
3335 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3336
3337 if (0 == ps_dec_state->u4_frm_buf_stride)
3338 {
3339 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3340 }
3341
3342 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3343 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3344 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3345
3346 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3347 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3348 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3349
3350 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3351 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3352 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3353 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3354
3355 switch(ps_dec_state->i4_chromaFormat)
3356 {
3357 case IV_YUV_420SP_UV:
3358 case IV_YUV_420SP_VU:
3359 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3360 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3361 break;
3362 case IV_YUV_422ILE:
3363 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3364 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3365 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3366 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3367 break;
3368 default:
3369 break;
3370 }
3371
3372 if( ps_dec_state->u1_flushfrm == 0)
3373 {
3374 ps_dec_state->u1_flushcnt = 0;
3375
3376 /*************************************************************************/
3377 /* Frame Decode */
3378 /*************************************************************************/
3379
3380 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3381
3382 if (IVD_ERROR_NONE ==
3383 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3384 {
3385 if(ps_dec_state->u1_first_frame_done == 0)
3386 {
3387 ps_dec_state->u1_first_frame_done = 1;
3388 }
3389
3390 if(ps_dec_state->ps_disp_pic)
3391 {
3392 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3393 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3394 {
3395 case I_PIC :
3396 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3397 break;
3398
3399 case P_PIC:
3400 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3401 break;
3402
3403 case B_PIC:
3404 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3405 break;
3406
3407 case D_PIC:
3408 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3409 break;
3410
3411 default :
3412 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3413 break;
3414 }
3415 }
3416 else
3417 {
3418 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3419 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3420 }
3421
3422 ps_dec_state->u4_num_frames_decoded++;
3423 }
3424 }
3425 else
3426 {
3427 ps_dec_state->u1_flushcnt++;
3428 }
3429 }
3430 if(ps_dec_state->ps_disp_pic)
3431 {
3432 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3433 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3434
3435 if(0 == ps_dec_state->u4_share_disp_buf)
3436 {
3437 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3438 }
3439 }
3440
3441 if(ps_dec_state->u4_deinterlace)
3442 {
3443 if(ps_dec_state->ps_deint_pic)
3444 {
3445 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3446 ps_dec_state->ps_deint_pic->i4_buf_id,
3447 MPEG2_BUF_MGR_DEINT);
3448 }
3449 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3450 }
3451
3452 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3453 {
3454 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3455 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3456 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3457 ps_dec_state->u4_frm_buf_stride,
3458 ps_dec_state->u2_horizontal_size,
3459 ps_dec_state->u2_vertical_size,
3460 ps_dec_state->i4_chromaFormat,
3461 ps_dec_state->u2_horizontal_size,
3462 ps_dec_state->u2_vertical_size);
3463 }
3464
3465 }
3466
3467 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3468 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3469
3470
3471 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3472 return IV_FAIL;
3473 else
3474 return IV_SUCCESS;
3475 }
3476