| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 359 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
406 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
481 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
600 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
612 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
701 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); in CopyParameter() local
725 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); in CopyParameter() local
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 427 X86ManagedRegister out_reg = mout_reg.AsX86(); in CreateHandleScopeEntry() local
468 X86ManagedRegister out_reg = mout_reg.AsX86(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm.cc | 476 ArmManagedRegister out_reg = mout_reg.AsArm(); in CreateHandleScopeEntry() local
523 ArmManagedRegister out_reg = mout_reg.AsArm(); in LoadReferenceFromHandleScope() local
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| D | jni_macro_assembler_arm_vixl.cc | 438 ArmManagedRegister out_reg = mout_reg.AsArm(); in CreateHandleScopeEntry() local
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 478 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in CreateHandleScopeEntry() local
525 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 562 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in CreateHandleScopeEntry() local
609 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in LoadReferenceFromHandleScope() local
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| /art/compiler/optimizing/ |
| D | intrinsics_arm64.cc | 486 FPRegister out_reg = is64bit ? DRegisterFrom(out) : SRegisterFrom(out); in MathAbsFP() local
522 Register out_reg = is64bit ? XRegisterFrom(output) : WRegisterFrom(output); in GenAbsInteger() local
554 FPRegister out_reg = is_double ? DRegisterFrom(out) : SRegisterFrom(out); in GenMinMaxFP() local
614 Register out_reg = is_long ? XRegisterFrom(out) : WRegisterFrom(out); in GenMinMax() local
718 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); in GenMathRound() local
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| D | code_generator_arm_vixl.cc | 4344 vixl32::Register out_reg = OutputRegister(rem); in VisitRem() local
4627 vixl32::Register out_reg = OutputRegister(op); in HandleShift() local
7669 vixl32::Register out_reg = RegisterFrom(out); in VisitBitwiseNegatedRight() local
7867 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
7901 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
7938 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadOneRegister() local
7972 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_arm.cc | 4645 Register out_reg = out.AsRegister<Register>(); in HandleShift() local
5452 DRegister out_reg = FromLowSToD(out.AsFpuRegisterPairLow<SRegister>()); in HandleFieldGet() local
7597 Register out_reg = out.AsRegister<Register>(); in VisitBitwiseNegatedRight() local
7792 Register out_reg = out.AsRegister<Register>(); in HandleBitwiseOperation() local
7826 Register out_reg = out.AsRegister<Register>(); in HandleBitwiseOperation() local
7863 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
7897 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
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| D | intrinsics_arm_vixl.cc | 497 vixl32::Register out_reg = RegisterFrom(output); in GenAbsInteger() local
820 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat() local
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| D | code_generator_arm64.cc | 5846 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadOneRegister() local
5886 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_x86_64.cc | 6461 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadOneRegister() local
6494 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_mips64.cc | 4205 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadOneRegister() local
4243 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_x86.cc | 7096 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
7129 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
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| D | intrinsics_arm.cc | 439 Register out_reg = output.AsRegister<Register>(); in GenAbsInteger() local
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| D | code_generator_mips.cc | 6104 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
6142 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 3651 MipsManagedRegister out_reg = mout_reg.AsMips(); in CreateHandleScopeEntry() local
3700 MipsManagedRegister out_reg = mout_reg.AsMips(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3112 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); in CreateHandleScopeEntry() local
3162 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); in LoadReferenceFromHandleScope() local
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| /art/oatdump/ |
| D | oatdump.cc | 1422 for (size_t out_reg = 0; out_reg < num_outs; out_reg++) { in DumpVregLocations() local
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