| /art/runtime/interpreter/mterp/mips/ |
| D | header.S | 157 #define SEB(rd, rt) \ argument
159 #define SEH(rd, rt) \ argument
164 #define SEB(rd, rt) \ argument
167 #define SEH(rd, rt) \ argument
187 #define LSA(rd, rs, rt, sa) \ argument
196 #define LSA(rd, rs, rt, sa) \ argument
280 #define FETCH_ADVANCE_INST_RB(rd) \ argument
290 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) argument
291 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) argument
298 #define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) argument
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 111 void Rrx(vixl32::Register rd, vixl32::Register rn) { in Rrx()
116 void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) { in Mul()
123 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
140 void Vmov(vixl32::DRegister rd, double imm) { in Vmov()
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| D | assembler_thumb2.cc | 383 inline int32_t Thumb2Assembler::MovwEncoding32(Register rd, int32_t value) { in MovwEncoding32()
393 inline int32_t Thumb2Assembler::MovtEncoding32(Register rd, int32_t value) { in MovtEncoding32()
399 inline int32_t Thumb2Assembler::MovModImmEncoding32(Register rd, int32_t value) { in MovModImmEncoding32()
478 inline int16_t Thumb2Assembler::AdrEncoding16(Register rd, int32_t offset) { in AdrEncoding16()
485 inline int32_t Thumb2Assembler::AdrEncoding32(Register rd, int32_t offset) { in AdrEncoding32()
542 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_()
548 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor()
554 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub()
560 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb()
566 void Thumb2Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add()
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| D | assembler_arm_vixl.cc | 80 void ArmVIXLAssembler::LoadImmediate(vixl32::Register rd, int32_t value) { in LoadImmediate()
404 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, int32_t value) { in AddConstant()
409 void ArmVIXLAssembler::AddConstant(vixl32::Register rd, in AddConstant()
424 void ArmVIXLAssembler::AddConstantInIt(vixl32::Register rd, in AddConstantInIt()
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| D | assembler_arm.h | 838 bool ShifterOperandCanHold(Register rd, in ShifterOperandCanHold()
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_mips.S | 164 #define SEB(rd, rt) \ argument
166 #define SEH(rd, rt) \ argument
171 #define SEB(rd, rt) \ argument
174 #define SEH(rd, rt) \ argument
194 #define LSA(rd, rs, rt, sa) \ argument
203 #define LSA(rd, rs, rt, sa) \ argument
287 #define FETCH_ADVANCE_INST_RB(rd) \ argument
297 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) argument
298 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) argument
305 #define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) argument
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd()
126 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
323 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
327 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
331 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
335 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
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| D | assembler_mips64.h | 64 void TemplateLoadConst32(Asm* a, GpuRegister rd, int32_t value) { in TemplateLoadConst32()
95 void TemplateLoadConst64(Asm* a, Rtype rd, Vtype value) { in TemplateLoadConst64()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 334 Register rd, in EmitR()
407 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu()
415 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu()
439 void MipsAssembler::MulR2(Register rd, Register rs, Register rt) { in MulR2()
444 void MipsAssembler::DivR2(Register rd, Register rs, Register rt) { in DivR2()
450 void MipsAssembler::ModR2(Register rd, Register rs, Register rt) { in ModR2()
456 void MipsAssembler::DivuR2(Register rd, Register rs, Register rt) { in DivuR2()
462 void MipsAssembler::ModuR2(Register rd, Register rs, Register rt) { in ModuR2()
468 void MipsAssembler::MulR6(Register rd, Register rs, Register rt) { in MulR6()
473 void MipsAssembler::MuhR6(Register rd, Register rs, Register rt) { in MuhR6()
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| /art/disassembler/ |
| D | disassembler_mips.cc | 466 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. in Dump() local
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 73 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, int32_t value, Condition cond) { in AddConstant()
77 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, in AddConstant()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64_test.cc | 57 std::random_device rd; in TEST() local
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