Searched defs:rev16 (Results 1 – 7 of 7) sorted by relevance
/external/vixl/test/aarch64/ |
D | test-trace-aarch64.cc | 274 __ rev16(w20, w21); in GenerateTestSequenceBase() local 275 __ rev16(x22, x23); in GenerateTestSequenceBase() local 1326 __ rev16(v31.V16B(), v27.V16B()); in GenerateTestSequenceNEON() local 1327 __ rev16(v12.V8B(), v26.V8B()); in GenerateTestSequenceNEON() local
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/external/vixl/src/aarch64/ |
D | assembler-aarch64.cc | 920 void Assembler::rev16(const Register& rd, const Register& rn) { in rev16() function in vixl::aarch64::Assembler 3376 void Assembler::rev16(const VRegister& vd, const VRegister& vn) { in rev16() function in vixl::aarch64::Assembler
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D | logic-aarch64.cc | 2320 LogicVRegister Simulator::rev16(VectorFormat vform, in rev16() function in vixl::aarch64::Simulator
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/external/v8/src/arm64/ |
D | assembler-arm64.cc | 1541 void Assembler::rev16(const Register& rd, in rev16() function in v8::internal::Assembler
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 2785 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } in rev16() function 2786 void rev16(Condition cond, Register rd, Register rm) { in rev16() function 2789 void rev16(EncodingSize size, Register rd, Register rm) { in rev16() function
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D | assembler-aarch32.cc | 8098 void Assembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Assembler
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D | disasm-aarch32.cc | 2257 void Disassembler::rev16(Condition cond, in rev16() function in vixl::aarch32::Disassembler
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