Searched defs:rs (Results 1 – 6 of 6) sorted by relevance
99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd()139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI()149 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) { in EmitI21()239 GpuRegister rs, in EmitMsaMI10()303 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu()311 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu()319 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()[all …]
332 Register rs, in EmitR()350 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI()361 uint32_t MipsAssembler::EmitI21(int opcode, Register rs, uint32_t imm21) { in EmitI21()407 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu()411 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { in Addiu()415 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu()419 void MipsAssembler::MultR2(Register rs, Register rt) { in MultR2()424 void MipsAssembler::MultuR2(Register rs, Register rt) { in MultuR2()429 void MipsAssembler::DivR2(Register rs, Register rt) { in DivR2()434 void MipsAssembler::DivuR2(Register rs, Register rt) { in DivuR2()[all …]
464 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. in Dump() local
187 #define LSA(rd, rs, rt, sa) \ argument196 #define LSA(rd, rs, rt, sa) \ argument
148 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), in ShifterOperand()
194 #define LSA(rd, rs, rt, sa) \ argument203 #define LSA(rd, rs, rt, sa) \ argument