1 /****************************************************************************** 2 * arch-arm.h 3 * 4 * Guest OS interface to ARM Xen. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Copyright 2011 (C) Citrix Systems 25 */ 26 27 #ifndef __XEN_PUBLIC_ARCH_ARM_H__ 28 #define __XEN_PUBLIC_ARCH_ARM_H__ 29 30 /* 31 * `incontents 50 arm_abi Hypercall Calling Convention 32 * 33 * A hypercall is issued using the ARM HVC instruction. 34 * 35 * A hypercall can take up to 5 arguments. These are passed in 36 * registers, the first argument in x0/r0 (for arm64/arm32 guests 37 * respectively irrespective of whether the underlying hypervisor is 38 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2, 39 * the forth in x3/r3 and the fifth in x4/r4. 40 * 41 * The hypercall number is passed in r12 (arm) or x16 (arm64). In both 42 * cases the relevant ARM procedure calling convention specifies this 43 * is an inter-procedure-call scratch register (e.g. for use in linker 44 * stubs). This use does not conflict with use during a hypercall. 45 * 46 * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG. 47 * 48 * The return value is in x0/r0. 49 * 50 * The hypercall will clobber x16/r12 and the argument registers used 51 * by that hypercall (except r0 which is the return value) i.e. in 52 * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a 53 * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3. 54 * 55 * Parameter structs passed to hypercalls are laid out according to 56 * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA 57 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture 58 * (AAPCS64). Where there is a conflict the 64-bit standard should be 59 * used regardless of guest type. Structures which are passed as 60 * hypercall arguments are always little endian. 61 * 62 * All memory which is shared with other entities in the system 63 * (including the hypervisor and other guests) must reside in memory 64 * which is mapped as Normal Inner-cacheable. This applies to: 65 * - hypercall arguments passed via a pointer to guest memory. 66 * - memory shared via the grant table mechanism (including PV I/O 67 * rings etc). 68 * - memory shared with the hypervisor (struct shared_info, struct 69 * vcpu_info, the grant table, etc). 70 * 71 * Any Inner cache allocation strategy (Write-Back, Write-Through etc) 72 * is acceptable. There is no restriction on the Outer-cacheability. 73 */ 74 75 /* 76 * `incontents 55 arm_hcall Supported Hypercalls 77 * 78 * Xen on ARM makes extensive use of hardware facilities and therefore 79 * only a subset of the potential hypercalls are required. 80 * 81 * Since ARM uses second stage paging any machine/physical addresses 82 * passed to hypercalls are Guest Physical Addresses (Intermediate 83 * Physical Addresses) unless otherwise noted. 84 * 85 * The following hypercalls (and sub operations) are supported on the 86 * ARM platform. Other hypercalls should be considered 87 * unavailable/unsupported. 88 * 89 * HYPERVISOR_memory_op 90 * All generic sub-operations. 91 * 92 * In addition the following arch specific sub-ops: 93 * * XENMEM_add_to_physmap 94 * * XENMEM_add_to_physmap_batch 95 * 96 * HYPERVISOR_domctl 97 * All generic sub-operations, with the exception of: 98 * * XEN_DOMCTL_iomem_permission (not yet implemented) 99 * * XEN_DOMCTL_irq_permission (not yet implemented) 100 * 101 * HYPERVISOR_sched_op 102 * All generic sub-operations, with the exception of: 103 * * SCHEDOP_block -- prefer wfi hardware instruction 104 * 105 * HYPERVISOR_console_io 106 * All generic sub-operations 107 * 108 * HYPERVISOR_xen_version 109 * All generic sub-operations 110 * 111 * HYPERVISOR_event_channel_op 112 * All generic sub-operations 113 * 114 * HYPERVISOR_physdev_op 115 * No sub-operations are currenty supported 116 * 117 * HYPERVISOR_sysctl 118 * All generic sub-operations, with the exception of: 119 * * XEN_SYSCTL_page_offline_op 120 * * XEN_SYSCTL_get_pmstat 121 * * XEN_SYSCTL_pm_op 122 * 123 * HYPERVISOR_hvm_op 124 * Exactly these sub-operations are supported: 125 * * HVMOP_set_param 126 * * HVMOP_get_param 127 * 128 * HYPERVISOR_grant_table_op 129 * All generic sub-operations 130 * 131 * HYPERVISOR_vcpu_op 132 * Exactly these sub-operations are supported: 133 * * VCPUOP_register_vcpu_info 134 * * VCPUOP_register_runstate_memory_area 135 * 136 * 137 * Other notes on the ARM ABI: 138 * 139 * - struct start_info is not exported to ARM guests. 140 * 141 * - struct shared_info is mapped by ARM guests using the 142 * HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing 143 * XENMAPSPACE_shared_info as space parameter. 144 * 145 * - All the per-cpu struct vcpu_info are mapped by ARM guests using the 146 * HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0 147 * struct vcpu_info. 148 * 149 * - The grant table is mapped using the HYPERVISOR_memory_op sub-op 150 * XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space 151 * parameter. The memory range specified under the Xen compatible 152 * hypervisor node on device tree can be used as target gpfn for the 153 * mapping. 154 * 155 * - Xenstore is initialized by using the two hvm_params 156 * HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read 157 * with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 158 * 159 * - The paravirtualized console is initialized by using the two 160 * hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They 161 * can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 162 * 163 * - Event channel notifications are delivered using the percpu GIC 164 * interrupt specified under the Xen compatible hypervisor node on 165 * device tree. 166 * 167 * - The device tree Xen compatible node is fully described under Linux 168 * at Documentation/devicetree/bindings/arm/xen.txt. 169 */ 170 171 #define XEN_HYPERCALL_TAG 0xEA1 172 173 #define uint64_aligned_t UINT64 __attribute__((aligned(8))) 174 175 #ifndef __ASSEMBLY__ 176 #define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ 177 typedef union { type *p; unsigned long q; } \ 178 __guest_handle_ ## name; \ 179 typedef union { type *p; uint64_aligned_t q; } \ 180 __guest_handle_64_ ## name; 181 182 /* 183 * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field 184 * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes 185 * aligned. 186 * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an 187 * hypercall argument. It is 4 bytes on aarch and 8 bytes on aarch64. 188 */ 189 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \ 190 ___DEFINE_XEN_GUEST_HANDLE(name, type); \ 191 ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) 192 #define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) 193 #define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name 194 #define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) 195 /* this is going to be changed on 64 bit */ 196 #define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name 197 #define set_xen_guest_handle_raw(hnd, val) \ 198 do { \ 199 typeof(&(hnd)) _sxghr_tmp = &(hnd); \ 200 _sxghr_tmp->q = 0; \ 201 _sxghr_tmp->p = val; \ 202 } while ( 0 ) 203 #ifdef __XEN_TOOLS__ 204 #define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0) 205 #endif 206 #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) 207 208 #if defined(__GNUC__) && !defined(__STRICT_ANSI__) 209 /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ 210 # define __DECL_REG(n64, n32) union { \ 211 UINT64 n64; \ 212 UINT32 n32; \ 213 } 214 #else 215 /* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */ 216 #define __DECL_REG(n64, n32) UINT64 n64 217 #endif 218 219 struct vcpu_guest_core_regs 220 { 221 /* Aarch64 Aarch32 */ 222 __DECL_REG(x0, r0_usr); 223 __DECL_REG(x1, r1_usr); 224 __DECL_REG(x2, r2_usr); 225 __DECL_REG(x3, r3_usr); 226 __DECL_REG(x4, r4_usr); 227 __DECL_REG(x5, r5_usr); 228 __DECL_REG(x6, r6_usr); 229 __DECL_REG(x7, r7_usr); 230 __DECL_REG(x8, r8_usr); 231 __DECL_REG(x9, r9_usr); 232 __DECL_REG(x10, r10_usr); 233 __DECL_REG(x11, r11_usr); 234 __DECL_REG(x12, r12_usr); 235 236 __DECL_REG(x13, sp_usr); 237 __DECL_REG(x14, lr_usr); 238 239 __DECL_REG(x15, __unused_sp_hyp); 240 241 __DECL_REG(x16, lr_irq); 242 __DECL_REG(x17, sp_irq); 243 244 __DECL_REG(x18, lr_svc); 245 __DECL_REG(x19, sp_svc); 246 247 __DECL_REG(x20, lr_abt); 248 __DECL_REG(x21, sp_abt); 249 250 __DECL_REG(x22, lr_und); 251 __DECL_REG(x23, sp_und); 252 253 __DECL_REG(x24, r8_fiq); 254 __DECL_REG(x25, r9_fiq); 255 __DECL_REG(x26, r10_fiq); 256 __DECL_REG(x27, r11_fiq); 257 __DECL_REG(x28, r12_fiq); 258 259 __DECL_REG(x29, sp_fiq); 260 __DECL_REG(x30, lr_fiq); 261 262 /* Return address and mode */ 263 __DECL_REG(pc64, pc32); /* ELR_EL2 */ 264 UINT32 cpsr; /* SPSR_EL2 */ 265 266 union { 267 UINT32 spsr_el1; /* AArch64 */ 268 UINT32 spsr_svc; /* AArch32 */ 269 }; 270 271 /* AArch32 guests only */ 272 UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt; 273 274 /* AArch64 guests only */ 275 UINT64 sp_el0; 276 UINT64 sp_el1, elr_el1; 277 }; 278 typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t; 279 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t); 280 281 #undef __DECL_REG 282 283 typedef UINT64 xen_pfn_t; 284 #define PRI_xen_pfn PRIx64 285 286 /* Maximum number of virtual CPUs in legacy multi-processor guests. */ 287 /* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ 288 #define XEN_LEGACY_MAX_VCPUS 1 289 290 typedef UINT64 xen_ulong_t; 291 #define PRI_xen_ulong PRIx64 292 293 #if defined(__XEN__) || defined(__XEN_TOOLS__) 294 struct vcpu_guest_context { 295 #define _VGCF_online 0 296 #define VGCF_online (1<<_VGCF_online) 297 UINT32 flags; /* VGCF_* */ 298 299 struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ 300 301 UINT32 sctlr; 302 UINT64 ttbcr, ttbr0, ttbr1; 303 }; 304 typedef struct vcpu_guest_context vcpu_guest_context_t; 305 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); 306 #endif 307 308 struct arch_vcpu_info { 309 }; 310 typedef struct arch_vcpu_info arch_vcpu_info_t; 311 312 struct arch_shared_info { 313 }; 314 typedef struct arch_shared_info arch_shared_info_t; 315 typedef UINT64 xen_callback_t; 316 317 #endif 318 319 #if defined(__XEN__) || defined(__XEN_TOOLS__) 320 321 /* PSR bits (CPSR, SPSR)*/ 322 323 #define PSR_THUMB (1<<5) /* Thumb Mode enable */ 324 #define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */ 325 #define PSR_IRQ_MASK (1<<7) /* Interrupt mask */ 326 #define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */ 327 #define PSR_BIG_ENDIAN (1<<9) /* arm32: Big Endian Mode */ 328 #define PSR_DBG_MASK (1<<9) /* arm64: Debug Exception mask */ 329 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ 330 #define PSR_JAZELLE (1<<24) /* Jazelle Mode */ 331 332 /* 32 bit modes */ 333 #define PSR_MODE_USR 0x10 334 #define PSR_MODE_FIQ 0x11 335 #define PSR_MODE_IRQ 0x12 336 #define PSR_MODE_SVC 0x13 337 #define PSR_MODE_MON 0x16 338 #define PSR_MODE_ABT 0x17 339 #define PSR_MODE_HYP 0x1a 340 #define PSR_MODE_UND 0x1b 341 #define PSR_MODE_SYS 0x1f 342 343 /* 64 bit modes */ 344 #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ 345 #define PSR_MODE_EL3h 0x0d 346 #define PSR_MODE_EL3t 0x0c 347 #define PSR_MODE_EL2h 0x09 348 #define PSR_MODE_EL2t 0x08 349 #define PSR_MODE_EL1h 0x05 350 #define PSR_MODE_EL1t 0x04 351 #define PSR_MODE_EL0t 0x00 352 353 #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) 354 #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) 355 356 #define SCTLR_GUEST_INIT 0x00c50078 357 358 /* 359 * Virtual machine platform (memory layout, interrupts) 360 * 361 * These are defined for consistency between the tools and the 362 * hypervisor. Guests must not rely on these hardcoded values but 363 * should instead use the FDT. 364 */ 365 366 /* Physical Address Space */ 367 368 /* vGIC mappings: Only one set of mapping is used by the guest. 369 * Therefore they can overlap. 370 */ 371 372 /* vGIC v2 mappings */ 373 #define GUEST_GICD_BASE 0x03001000ULL 374 #define GUEST_GICD_SIZE 0x00001000ULL 375 #define GUEST_GICC_BASE 0x03002000ULL 376 #define GUEST_GICC_SIZE 0x00000100ULL 377 378 /* vGIC v3 mappings */ 379 #define GUEST_GICV3_GICD_BASE 0x03001000ULL 380 #define GUEST_GICV3_GICD_SIZE 0x00010000ULL 381 382 #define GUEST_GICV3_RDIST_STRIDE 0x20000ULL 383 #define GUEST_GICV3_RDIST_REGIONS 1 384 385 #define GUEST_GICV3_GICR0_BASE 0x03020000ULL /* vCPU0 - vCPU7 */ 386 #define GUEST_GICV3_GICR0_SIZE 0x00100000ULL 387 388 /* 16MB == 4096 pages reserved for guest to use as a region to map its 389 * grant table in. 390 */ 391 #define GUEST_GNTTAB_BASE 0x38000000ULL 392 #define GUEST_GNTTAB_SIZE 0x01000000ULL 393 394 #define GUEST_MAGIC_BASE 0x39000000ULL 395 #define GUEST_MAGIC_SIZE 0x01000000ULL 396 397 #define GUEST_RAM_BANKS 2 398 399 #define GUEST_RAM0_BASE 0x40000000ULL /* 3GB of low RAM @ 1GB */ 400 #define GUEST_RAM0_SIZE 0xc0000000ULL 401 402 #define GUEST_RAM1_BASE 0x0200000000ULL /* 1016GB of RAM @ 8GB */ 403 #define GUEST_RAM1_SIZE 0xfe00000000ULL 404 405 #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ 406 /* Largest amount of actual RAM, not including holes */ 407 #define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE) 408 /* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */ 409 #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } 410 #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } 411 412 /* Interrupts */ 413 #define GUEST_TIMER_VIRT_PPI 27 414 #define GUEST_TIMER_PHYS_S_PPI 29 415 #define GUEST_TIMER_PHYS_NS_PPI 30 416 #define GUEST_EVTCHN_PPI 31 417 418 /* PSCI functions */ 419 #define PSCI_cpu_suspend 0 420 #define PSCI_cpu_off 1 421 #define PSCI_cpu_on 2 422 #define PSCI_migrate 3 423 424 #endif 425 426 #endif /* __XEN_PUBLIC_ARCH_ARM_H__ */ 427 428 /* 429 * Local variables: 430 * mode: C 431 * c-file-style: "BSD" 432 * c-basic-offset: 4 433 * tab-width: 4 434 * indent-tabs-mode: nil 435 * End: 436 */ 437