1 /*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <arch_helpers.h>
32 #include <assert.h>
33 #include <bl_common.h>
34 #include <context_mgmt.h>
35 #include <debug.h>
36 #include <platform.h>
37 #include <tsp.h>
38 #include "tspd_private.h"
39
40 /*******************************************************************************
41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions
42 * needed. Nothing at the moment.
43 ******************************************************************************/
tspd_cpu_on_handler(uint64_t target_cpu)44 static void tspd_cpu_on_handler(uint64_t target_cpu)
45 {
46 }
47
48 /*******************************************************************************
49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions
50 * needed
51 ******************************************************************************/
tspd_cpu_off_handler(uint64_t unused)52 static int32_t tspd_cpu_off_handler(uint64_t unused)
53 {
54 int32_t rc = 0;
55 uint64_t mpidr = read_mpidr();
56 uint32_t linear_id = platform_get_core_pos(mpidr);
57 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
58
59 assert(tsp_vectors);
60 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
61
62 /* Program the entry point and enter the TSP */
63 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry);
64 rc = tspd_synchronous_sp_entry(tsp_ctx);
65
66 /*
67 * Read the response from the TSP. A non-zero return means that
68 * something went wrong while communicating with the TSP.
69 */
70 if (rc != 0)
71 panic();
72
73 /*
74 * Reset TSP's context for a fresh start when this cpu is turned on
75 * subsequently.
76 */
77 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
78
79 return 0;
80 }
81
82 /*******************************************************************************
83 * This cpu is being suspended. S-EL1 state must have been saved in the
84 * resident cpu (mpidr format) if it is a UP/UP migratable TSP.
85 ******************************************************************************/
tspd_cpu_suspend_handler(uint64_t unused)86 static void tspd_cpu_suspend_handler(uint64_t unused)
87 {
88 int32_t rc = 0;
89 uint64_t mpidr = read_mpidr();
90 uint32_t linear_id = platform_get_core_pos(mpidr);
91 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
92
93 assert(tsp_vectors);
94 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
95
96 /* Program the entry point and enter the TSP */
97 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
98 rc = tspd_synchronous_sp_entry(tsp_ctx);
99
100 /*
101 * Read the response from the TSP. A non-zero return means that
102 * something went wrong while communicating with the TSP.
103 */
104 if (rc != 0)
105 panic();
106
107 /* Update its context to reflect the state the TSP is in */
108 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND);
109 }
110
111 /*******************************************************************************
112 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits
113 * before passing control back to the Secure Monitor. Entry in S-El1 is done
114 * after initialising minimal architectural state that guarantees safe
115 * execution.
116 ******************************************************************************/
tspd_cpu_on_finish_handler(uint64_t unused)117 static void tspd_cpu_on_finish_handler(uint64_t unused)
118 {
119 int32_t rc = 0;
120 uint64_t mpidr = read_mpidr();
121 uint32_t linear_id = platform_get_core_pos(mpidr);
122 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
123 entry_point_info_t tsp_on_entrypoint;
124
125 assert(tsp_vectors);
126 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF);
127
128 tspd_init_tsp_ep_state(&tsp_on_entrypoint,
129 TSP_AARCH64,
130 (uint64_t) &tsp_vectors->cpu_on_entry,
131 tsp_ctx);
132
133 /* Initialise this cpu's secure context */
134 cm_init_context(mpidr, &tsp_on_entrypoint);
135
136 #if TSPD_ROUTE_IRQ_TO_EL3
137 /*
138 * Disable the NS interrupt locally since it will be enabled globally
139 * within cm_init_context.
140 */
141 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
142 #endif
143
144 /* Enter the TSP */
145 rc = tspd_synchronous_sp_entry(tsp_ctx);
146
147 /*
148 * Read the response from the TSP. A non-zero return means that
149 * something went wrong while communicating with the SP.
150 */
151 if (rc != 0)
152 panic();
153
154 /* Update its context to reflect the state the SP is in */
155 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
156 }
157
158 /*******************************************************************************
159 * This cpu has resumed from suspend. The SPD saved the TSP context when it
160 * completed the preceding suspend call. Use that context to program an entry
161 * into the TSP to allow it to do any remaining book keeping
162 ******************************************************************************/
tspd_cpu_suspend_finish_handler(uint64_t suspend_level)163 static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
164 {
165 int32_t rc = 0;
166 uint64_t mpidr = read_mpidr();
167 uint32_t linear_id = platform_get_core_pos(mpidr);
168 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
169
170 assert(tsp_vectors);
171 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND);
172
173 /* Program the entry point, suspend_level and enter the SP */
174 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
175 CTX_GPREG_X0,
176 suspend_level);
177 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
178 rc = tspd_synchronous_sp_entry(tsp_ctx);
179
180 /*
181 * Read the response from the TSP. A non-zero return means that
182 * something went wrong while communicating with the TSP.
183 */
184 if (rc != 0)
185 panic();
186
187 /* Update its context to reflect the state the SP is in */
188 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
189 }
190
191 /*******************************************************************************
192 * Return the type of TSP the TSPD is dealing with. Report the current resident
193 * cpu (mpidr format) if it is a UP/UP migratable TSP.
194 ******************************************************************************/
tspd_cpu_migrate_info(uint64_t * resident_cpu)195 static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu)
196 {
197 return TSP_MIGRATE_INFO;
198 }
199
200 /*******************************************************************************
201 * System is about to be switched off. Allow the TSPD/TSP to perform
202 * any actions needed.
203 ******************************************************************************/
tspd_system_off(void)204 static void tspd_system_off(void)
205 {
206 uint64_t mpidr = read_mpidr();
207 uint32_t linear_id = platform_get_core_pos(mpidr);
208 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
209
210 assert(tsp_vectors);
211 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
212
213 /* Program the entry point */
214 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry);
215
216 /* Enter the TSP. We do not care about the return value because we
217 * must continue the shutdown anyway */
218 tspd_synchronous_sp_entry(tsp_ctx);
219 }
220
221 /*******************************************************************************
222 * System is about to be reset. Allow the TSPD/TSP to perform
223 * any actions needed.
224 ******************************************************************************/
tspd_system_reset(void)225 static void tspd_system_reset(void)
226 {
227 uint64_t mpidr = read_mpidr();
228 uint32_t linear_id = platform_get_core_pos(mpidr);
229 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
230
231 assert(tsp_vectors);
232 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
233
234 /* Program the entry point */
235 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry);
236
237 /* Enter the TSP. We do not care about the return value because we
238 * must continue the reset anyway */
239 tspd_synchronous_sp_entry(tsp_ctx);
240 }
241
242 /*******************************************************************************
243 * Structure populated by the TSP Dispatcher to be given a chance to perform any
244 * TSP bookkeeping before PSCI executes a power mgmt. operation.
245 ******************************************************************************/
246 const spd_pm_ops_t tspd_pm = {
247 .svc_on = tspd_cpu_on_handler,
248 .svc_off = tspd_cpu_off_handler,
249 .svc_suspend = tspd_cpu_suspend_handler,
250 .svc_on_finish = tspd_cpu_on_finish_handler,
251 .svc_suspend_finish = tspd_cpu_suspend_finish_handler,
252 .svc_migrate = NULL,
253 .svc_migrate_info = tspd_cpu_migrate_info,
254 .svc_system_off = tspd_system_off,
255 .svc_system_reset = tspd_system_reset
256 };
257