1//
2//  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
3//
4//  This program and the accompanying materials
5//  are licensed and made available under the terms and conditions of the BSD License
6//  which accompanies this distribution.  The full text of the license may be found at
7//  http://opensource.org/licenses/bsd-license.php
8//
9//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11//
12//
13
14#include <AsmMacroIoLibV8.h>
15#include <Base.h>
16#include <Library/PcdLib.h>
17#include <AutoGen.h>
18
19.text
20.align 3
21
22GCC_ASM_IMPORT(CEntryPoint)
23GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
24GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
25GCC_ASM_IMPORT(ArmReadMpidr)
26GCC_ASM_IMPORT(ArmPlatformPeiBootAction)
27GCC_ASM_EXPORT(_ModuleEntryPoint)
28
29StartupAddr: .8byte CEntryPoint
30
31ASM_PFX(_ModuleEntryPoint):
32  // Do early platform specific actions
33  bl    ASM_PFX(ArmPlatformPeiBootAction)
34
35// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
36//       and configure the system accordingly. EL2 is default if possible.
37// If we started in EL3 we need to switch and run at EL2.
38// If we are running at EL2 stay in EL2
39// If we are starting at EL1 stay in EL1.
40
41// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
42// If started at EL1 or EL2 Sec jumps directly to PEI without making any
43// changes.
44
45// Which EL are we running at? Every EL needs some level of setup...
46// We should not run this code in EL3
47  EL1_OR_EL2(x0)
481:bl    ASM_PFX(SetupExceptionLevel1)
49  b     ASM_PFX(MainEntryPoint)
502:bl    ASM_PFX(SetupExceptionLevel2)
51  b     ASM_PFX(MainEntryPoint)
52
53ASM_PFX(MainEntryPoint):
54  // Identify CPU ID
55  bl    ASM_PFX(ArmReadMpidr)
56  // Keep a copy of the MpId register value
57  mov   x5, x0
58
59  // Is it the Primary Core ?
60  bl    ASM_PFX(ArmPlatformIsPrimaryCore)
61
62  // Get the top of the primary stacks (and the base of the secondary stacks)
63  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), x1)
64  LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2)
65  add   x1, x1, x2
66
67  // x0 is equal to 1 if I am the primary core
68  cmp   x0, #1
69  b.eq   _SetupPrimaryCoreStack
70
71_SetupSecondaryCoreStack:
72  // x1 contains the base of the secondary stacks
73
74  // Get the Core Position
75  mov   x6, x1      // Save base of the secondary stacks
76  mov   x0, x5
77  bl    ASM_PFX(ArmPlatformGetCorePosition)
78  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
79  add   x0, x0, #1
80
81  // StackOffset = CorePos * StackSize
82  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x2)
83  mul   x0, x0, x2
84  // SP = StackBase + StackOffset
85  add   sp, x6, x0
86
87_PrepareArguments:
88  // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
89  LoadConstantToReg (FixedPcdGet64(PcdFvBaseAddress), x2)
90  add   x2, x2, #8
91  ldr   x1, [x2]
92
93  // Move sec startup address into a data register
94  // Ensure we're jumping to FV version of the code (not boot remapped alias)
95  ldr   x3, StartupAddr
96
97  // Jump to PrePeiCore C code
98  //    x0 = mp_id
99  //    x1 = pei_core_address
100  mov   x0, x5
101  blr   x3
102
103_SetupPrimaryCoreStack:
104  mov   sp, x1
105  b     _PrepareArguments
106