1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
19 #include "llvm/CodeGen/MachineCombinerPattern.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
30 class AArch64InstrInfo : public AArch64GenInstrInfo {
31   const AArch64RegisterInfo RI;
32   const AArch64Subtarget &Subtarget;
33 
34 public:
35   explicit AArch64InstrInfo(const AArch64Subtarget &STI);
36 
37   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
38   /// such, whenever a client has an instance of instruction info, it should
39   /// always be able to get register info as well (through this method).
getRegisterInfo()40   const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
41 
42   unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
43 
44   bool isAsCheapAsAMove(const MachineInstr &MI) const override;
45 
46   bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
47                              unsigned &DstReg, unsigned &SubIdx) const override;
48 
49   bool
50   areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
51                                   AliasAnalysis *AA = nullptr) const override;
52 
53   unsigned isLoadFromStackSlot(const MachineInstr &MI,
54                                int &FrameIndex) const override;
55   unsigned isStoreToStackSlot(const MachineInstr &MI,
56                               int &FrameIndex) const override;
57 
58   /// Returns true if there is a shiftable register and that the shift value
59   /// is non-zero.
60   bool hasShiftedReg(const MachineInstr &MI) const;
61 
62   /// Returns true if there is an extendable register and that the extending
63   /// value is non-zero.
64   bool hasExtendedReg(const MachineInstr &MI) const;
65 
66   /// \brief Does this instruction set its full destination register to zero?
67   bool isGPRZero(const MachineInstr &MI) const;
68 
69   /// \brief Does this instruction rename a GPR without modifying bits?
70   bool isGPRCopy(const MachineInstr &MI) const;
71 
72   /// \brief Does this instruction rename an FPR without modifying bits?
73   bool isFPRCopy(const MachineInstr &MI) const;
74 
75   /// Return true if this is load/store scales or extends its register offset.
76   /// This refers to scaling a dynamic index as opposed to scaled immediates.
77   /// MI should be a memory op that allows scaled addressing.
78   bool isScaledAddr(const MachineInstr &MI) const;
79 
80   /// Return true if pairing the given load or store is hinted to be
81   /// unprofitable.
82   bool isLdStPairSuppressed(const MachineInstr &MI) const;
83 
84   /// Return true if this is an unscaled load/store.
85   bool isUnscaledLdSt(unsigned Opc) const;
86 
87   /// Return true if this is an unscaled load/store.
88   bool isUnscaledLdSt(MachineInstr &MI) const;
89 
90   /// Return true if this is a load/store that can be potentially paired/merged.
91   bool isCandidateToMergeOrPair(MachineInstr &MI) const;
92 
93   /// Hint that pairing the given load or store is unprofitable.
94   void suppressLdStPair(MachineInstr &MI) const;
95 
96   bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
97                              int64_t &Offset,
98                              const TargetRegisterInfo *TRI) const override;
99 
100   bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
101                                   int64_t &Offset, unsigned &Width,
102                                   const TargetRegisterInfo *TRI) const;
103 
enableClusterLoads()104   bool enableClusterLoads() const override { return true; }
105 
enableClusterStores()106   bool enableClusterStores() const override { return true; }
107 
108   bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
109                            unsigned NumLoads) const override;
110 
111   bool shouldScheduleAdjacent(MachineInstr &First,
112                               MachineInstr &Second) const override;
113 
114   MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
115                                          uint64_t Offset, const MDNode *Var,
116                                          const MDNode *Expr,
117                                          const DebugLoc &DL) const;
118   void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
119                         const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
120                         bool KillSrc, unsigned Opcode,
121                         llvm::ArrayRef<unsigned> Indices) const;
122   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
123                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
124                    bool KillSrc) const override;
125 
126   void storeRegToStackSlot(MachineBasicBlock &MBB,
127                            MachineBasicBlock::iterator MBBI, unsigned SrcReg,
128                            bool isKill, int FrameIndex,
129                            const TargetRegisterClass *RC,
130                            const TargetRegisterInfo *TRI) const override;
131 
132   void loadRegFromStackSlot(MachineBasicBlock &MBB,
133                             MachineBasicBlock::iterator MBBI, unsigned DestReg,
134                             int FrameIndex, const TargetRegisterClass *RC,
135                             const TargetRegisterInfo *TRI) const override;
136 
137   using TargetInstrInfo::foldMemoryOperandImpl;
138   MachineInstr *
139   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
140                         ArrayRef<unsigned> Ops,
141                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
142                         LiveIntervals *LIS = nullptr) const override;
143 
144   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
145                      MachineBasicBlock *&FBB,
146                      SmallVectorImpl<MachineOperand> &Cond,
147                      bool AllowModify = false) const override;
148   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
149   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
150                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
151                         const DebugLoc &DL) const override;
152   bool
153   ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
154   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
155                        unsigned, unsigned, int &, int &, int &) const override;
156   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
157                     const DebugLoc &DL, unsigned DstReg,
158                     ArrayRef<MachineOperand> Cond, unsigned TrueReg,
159                     unsigned FalseReg) const override;
160   void getNoopForMachoTarget(MCInst &NopInst) const override;
161 
162   /// analyzeCompare - For a comparison instruction, return the source registers
163   /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
164   /// Return true if the comparison instruction can be analyzed.
165   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
166                       unsigned &SrcReg2, int &CmpMask,
167                       int &CmpValue) const override;
168   /// optimizeCompareInstr - Convert the instruction supplying the argument to
169   /// the comparison into one that sets the zero bit in the flags register.
170   bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
171                             unsigned SrcReg2, int CmpMask, int CmpValue,
172                             const MachineRegisterInfo *MRI) const override;
173   bool optimizeCondBranch(MachineInstr &MI) const override;
174 
175   /// Return true when a code sequence can improve throughput. It
176   /// should be called only for instructions in loops.
177   /// \param Pattern - combiner pattern
178   bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
179   /// Return true when there is potentially a faster code sequence
180   /// for an instruction chain ending in <Root>. All potential patterns are
181   /// listed in the <Patterns> array.
182   bool getMachineCombinerPatterns(MachineInstr &Root,
183                   SmallVectorImpl<MachineCombinerPattern> &Patterns)
184       const override;
185   /// Return true when Inst is associative and commutative so that it can be
186   /// reassociated.
187   bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
188   /// When getMachineCombinerPatterns() finds patterns, this function generates
189   /// the instructions that could replace the original code sequence
190   void genAlternativeCodeSequence(
191       MachineInstr &Root, MachineCombinerPattern Pattern,
192       SmallVectorImpl<MachineInstr *> &InsInstrs,
193       SmallVectorImpl<MachineInstr *> &DelInstrs,
194       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
195   /// AArch64 supports MachineCombiner.
196   bool useMachineCombiner() const override;
197 
198   bool expandPostRAPseudo(MachineInstr &MI) const override;
199 
200   std::pair<unsigned, unsigned>
201   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
202   ArrayRef<std::pair<unsigned, const char *>>
203   getSerializableDirectMachineOperandTargetFlags() const override;
204   ArrayRef<std::pair<unsigned, const char *>>
205   getSerializableBitmaskMachineOperandTargetFlags() const override;
206 
207 private:
208   void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
209                              MachineBasicBlock *TBB,
210                              ArrayRef<MachineOperand> Cond) const;
211   bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
212                            const MachineRegisterInfo *MRI) const;
213 };
214 
215 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
216 /// plus Offset.  This is intended to be used from within the prolog/epilog
217 /// insertion (PEI) pass, where a virtual scratch register may be allocated
218 /// if necessary, to be replaced by the scavenger at the end of PEI.
219 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
220                      const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
221                      int Offset, const TargetInstrInfo *TII,
222                      MachineInstr::MIFlag = MachineInstr::NoFlags,
223                      bool SetNZCV = false);
224 
225 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
226 /// FP. Return false if the offset could not be handled directly in MI, and
227 /// return the left-over portion by reference.
228 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
229                             unsigned FrameReg, int &Offset,
230                             const AArch64InstrInfo *TII);
231 
232 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
233 enum AArch64FrameOffsetStatus {
234   AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
235   AArch64FrameOffsetIsLegal = 0x1,      ///< Offset is legal.
236   AArch64FrameOffsetCanUpdate = 0x2     ///< Offset can apply, at least partly.
237 };
238 
239 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
240 /// The returned value reports the validity of the frame offset for @p MI.
241 /// It uses the values defined by AArch64FrameOffsetStatus for that.
242 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
243 /// use an offset.eq
244 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
245 /// rewriten in @p MI.
246 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
247 /// amount that is off the limit of the legal offset.
248 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
249 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
250 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
251 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
252 /// is a legal offset.
253 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
254                             bool *OutUseUnscaledOp = nullptr,
255                             unsigned *OutUnscaledOp = nullptr,
256                             int *EmittableOffset = nullptr);
257 
isUncondBranchOpcode(int Opc)258 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
259 
isCondBranchOpcode(int Opc)260 static inline bool isCondBranchOpcode(int Opc) {
261   switch (Opc) {
262   case AArch64::Bcc:
263   case AArch64::CBZW:
264   case AArch64::CBZX:
265   case AArch64::CBNZW:
266   case AArch64::CBNZX:
267   case AArch64::TBZW:
268   case AArch64::TBZX:
269   case AArch64::TBNZW:
270   case AArch64::TBNZX:
271     return true;
272   default:
273     return false;
274   }
275 }
276 
isIndirectBranchOpcode(int Opc)277 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
278 
279 } // end namespace llvm
280 
281 #endif
282