1#------------------------------------------------------------------------------ 2# 3# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4# Copyright (c) 2011-2013, ARM Limited. All rights reserved. 5# 6# This program and the accompanying materials 7# are licensed and made available under the terms and conditions of the BSD License 8# which accompanies this distribution. The full text of the license may be found at 9# http://opensource.org/licenses/bsd-license.php 10# 11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13# 14#------------------------------------------------------------------------------ 15 16#include <AsmMacroIoLib.h> 17 18.text 19.align 2 20 21GCC_ASM_EXPORT(ArmIsMpCore) 22GCC_ASM_EXPORT(ArmHasMpExtensions) 23GCC_ASM_EXPORT(ArmEnableAsynchronousAbort) 24GCC_ASM_EXPORT(ArmDisableAsynchronousAbort) 25GCC_ASM_EXPORT(ArmEnableIrq) 26GCC_ASM_EXPORT(ArmDisableIrq) 27GCC_ASM_EXPORT(ArmEnableFiq) 28GCC_ASM_EXPORT(ArmDisableFiq) 29GCC_ASM_EXPORT(ArmEnableInterrupts) 30GCC_ASM_EXPORT(ArmDisableInterrupts) 31GCC_ASM_EXPORT(ReadCCSIDR) 32GCC_ASM_EXPORT(ReadCLIDR) 33GCC_ASM_EXPORT(ArmReadNsacr) 34GCC_ASM_EXPORT(ArmWriteNsacr) 35 36#------------------------------------------------------------------------------ 37 38ASM_PFX(ArmIsMpCore): 39 mrc p15,0,R0,c0,c0,5 40 // Get Multiprocessing extension (bit31) & U bit (bit30) 41 and R0, R0, #0xC0000000 42 // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system 43 cmp R0, #0x80000000 44 moveq R0, #1 45 movne R0, #0 46 bx LR 47 48ASM_PFX(ArmHasMpExtensions): 49 mrc p15,0,R0,c0,c0,5 50 // Get Multiprocessing extension (bit31) 51 lsr R0, R0, #31 52 bx LR 53 54ASM_PFX(ArmEnableAsynchronousAbort): 55 cpsie a 56 isb 57 bx LR 58 59ASM_PFX(ArmDisableAsynchronousAbort): 60 cpsid a 61 isb 62 bx LR 63 64ASM_PFX(ArmEnableIrq): 65 cpsie i 66 isb 67 bx LR 68 69ASM_PFX(ArmDisableIrq): 70 cpsid i 71 isb 72 bx LR 73 74ASM_PFX(ArmEnableFiq): 75 cpsie f 76 isb 77 bx LR 78 79ASM_PFX(ArmDisableFiq): 80 cpsid f 81 isb 82 bx LR 83 84ASM_PFX(ArmEnableInterrupts): 85 cpsie if 86 isb 87 bx LR 88 89ASM_PFX(ArmDisableInterrupts): 90 cpsid if 91 isb 92 bx LR 93 94// UINT32 95// ReadCCSIDR ( 96// IN UINT32 CSSELR 97// ) 98ASM_PFX(ReadCCSIDR): 99 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR) 100 isb 101 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR) 102 bx lr 103 104// UINT32 105// ReadCLIDR ( 106// IN UINT32 CSSELR 107// ) 108ASM_PFX(ReadCLIDR): 109 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register 110 bx lr 111 112ASM_PFX(ArmReadNsacr): 113 mrc p15, 0, r0, c1, c1, 2 114 bx lr 115 116ASM_PFX(ArmWriteNsacr): 117 mcr p15, 0, r0, c1, c1, 2 118 bx lr 119 120ASM_FUNCTION_REMOVE_IF_UNREFERENCED 121