1//------------------------------------------------------------------------------
2//
3// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
5//
6// This program and the accompanying materials
7// are licensed and made available under the terms and conditions of the BSD License
8// which accompanies this distribution.  The full text of the license may be found at
9// http://opensource.org/licenses/bsd-license.php
10//
11// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13//
14//------------------------------------------------------------------------------
15
16
17
18    INCLUDE AsmMacroExport.inc
19
20
21//------------------------------------------------------------------------------
22
23 RVCT_ASM_EXPORT ArmIsMpCore
24  mrc     p15,0,R0,c0,c0,5
25  // Get Multiprocessing extension (bit31) & U bit (bit30)
26  and     R0, R0, #0xC0000000
27  // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
28  cmp     R0, #0x80000000
29  moveq   R0, #1
30  movne   R0, #0
31  bx      LR
32
33 RVCT_ASM_EXPORT ArmHasMpExtensions
34  mrc     p15,0,R0,c0,c0,5
35  // Get Multiprocessing extension (bit31)
36  lsr     R0, R0, #31
37  bx      LR
38
39 RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
40  cpsie   a
41  isb
42  bx      LR
43
44 RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
45  cpsid   a
46  isb
47  bx      LR
48
49 RVCT_ASM_EXPORT ArmEnableIrq
50  cpsie   i
51  isb
52  bx      LR
53
54 RVCT_ASM_EXPORT ArmDisableIrq
55  cpsid   i
56  isb
57  bx      LR
58
59 RVCT_ASM_EXPORT ArmEnableFiq
60  cpsie   f
61  isb
62  bx      LR
63
64 RVCT_ASM_EXPORT ArmDisableFiq
65  cpsid   f
66  isb
67  bx      LR
68
69 RVCT_ASM_EXPORT ArmEnableInterrupts
70  cpsie   if
71  isb
72  bx      LR
73
74 RVCT_ASM_EXPORT ArmDisableInterrupts
75  cpsid   if
76  isb
77  bx      LR
78
79// UINT32
80// ReadCCSIDR (
81//   IN UINT32 CSSELR
82//   )
83 RVCT_ASM_EXPORT ReadCCSIDR
84  mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
85  isb
86  mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
87  bx  lr
88
89// UINT32
90// ReadCLIDR (
91//   IN UINT32 CSSELR
92//   )
93 RVCT_ASM_EXPORT ReadCLIDR
94  mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
95  bx  lr
96
97 RVCT_ASM_EXPORT ArmReadNsacr
98  mrc     p15, 0, r0, c1, c1, 2
99  bx      lr
100
101 RVCT_ASM_EXPORT ArmWriteNsacr
102  mcr     p15, 0, r0, c1, c1, 2
103  bx      lr
104
105  END
106