1#------------------------------------------------------------------------------
2#
3# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5#
6# This program and the accompanying materials
7# are licensed and made available under the terms and conditions of the BSD License
8# which accompanies this distribution.  The full text of the license may be found at
9# http://opensource.org/licenses/bsd-license.php
10#
11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13#
14#------------------------------------------------------------------------------
15
16.text
17.align 2
18
19GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
20GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
21GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
22GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
23GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
24GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
25GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
26GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
27GCC_ASM_EXPORT (ArmEnableMmu)
28GCC_ASM_EXPORT (ArmDisableMmu)
29GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
30GCC_ASM_EXPORT (ArmMmuEnabled)
31GCC_ASM_EXPORT (ArmEnableDataCache)
32GCC_ASM_EXPORT (ArmDisableDataCache)
33GCC_ASM_EXPORT (ArmEnableInstructionCache)
34GCC_ASM_EXPORT (ArmDisableInstructionCache)
35GCC_ASM_EXPORT (ArmEnableSWPInstruction)
36GCC_ASM_EXPORT (ArmEnableBranchPrediction)
37GCC_ASM_EXPORT (ArmDisableBranchPrediction)
38GCC_ASM_EXPORT (ArmSetLowVectors)
39GCC_ASM_EXPORT (ArmSetHighVectors)
40GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
41GCC_ASM_EXPORT (ArmDataMemoryBarrier)
42GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
43GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
44GCC_ASM_EXPORT (ArmReadVBar)
45GCC_ASM_EXPORT (ArmWriteVBar)
46GCC_ASM_EXPORT (ArmEnableVFP)
47GCC_ASM_EXPORT (ArmCallWFI)
48GCC_ASM_EXPORT (ArmReadCbar)
49GCC_ASM_EXPORT (ArmReadMpidr)
50GCC_ASM_EXPORT (ArmReadTpidrurw)
51GCC_ASM_EXPORT (ArmWriteTpidrurw)
52GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
53GCC_ASM_EXPORT (ArmReadIdPfr1)
54GCC_ASM_EXPORT (ArmReadIdMmfr0)
55
56.set DC_ON, (0x1<<2)
57.set IC_ON, (0x1<<12)
58.set CTRL_M_BIT,  (1 << 0)
59.set CTRL_C_BIT,  (1 << 2)
60.set CTRL_B_BIT,  (1 << 7)
61.set CTRL_I_BIT,  (1 << 12)
62
63
64ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
65  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
66  bx      lr
67
68ASM_PFX(ArmCleanDataCacheEntryByMVA):
69  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
70  bx      lr
71
72
73ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
74  mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU
75  bx      lr
76
77
78ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
79  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
80  bx      lr
81
82
83ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
84  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
85  bx      lr
86
87
88ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
89  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
90  bx      lr
91
92
93ASM_PFX(ArmCleanDataCacheEntryBySetWay):
94  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
95  bx      lr
96
97ASM_PFX(ArmInvalidateInstructionCache):
98  mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
99  dsb
100  isb
101  bx      LR
102
103ASM_PFX(ArmEnableMmu):
104  mrc     p15,0,R0,c1,c0,0
105  orr     R0,R0,#1
106  mcr     p15,0,R0,c1,c0,0
107  dsb
108  isb
109  bx      LR
110
111
112ASM_PFX(ArmDisableMmu):
113  mrc     p15,0,R0,c1,c0,0
114  bic     R0,R0,#1
115  mcr     p15,0,R0,c1,c0,0      @Disable MMU
116
117  mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
118  mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
119  dsb
120  isb
121  bx      LR
122
123ASM_PFX(ArmDisableCachesAndMmu):
124  mrc   p15, 0, r0, c1, c0, 0           @ Get control register
125  bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
126  bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
127  bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
128  mcr   p15, 0, r0, c1, c0, 0           @ Write control register
129  dsb
130  isb
131  bx      LR
132
133ASM_PFX(ArmMmuEnabled):
134  mrc     p15,0,R0,c1,c0,0
135  and     R0,R0,#1
136  bx      LR
137
138ASM_PFX(ArmEnableDataCache):
139  ldr     R1,=DC_ON
140  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
141  orr     R0,R0,R1              @Set C bit
142  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
143  dsb
144  isb
145  bx      LR
146
147ASM_PFX(ArmDisableDataCache):
148  ldr     R1,=DC_ON
149  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
150  bic     R0,R0,R1              @Clear C bit
151  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
152  dsb
153  isb
154  bx      LR
155
156ASM_PFX(ArmEnableInstructionCache):
157  ldr     R1,=IC_ON
158  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
159  orr     R0,R0,R1              @Set I bit
160  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
161  dsb
162  isb
163  bx      LR
164
165ASM_PFX(ArmDisableInstructionCache):
166  ldr     R1,=IC_ON
167  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
168  bic     R0,R0,R1              @Clear I bit.
169  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
170  dsb
171  isb
172  bx      LR
173
174ASM_PFX(ArmEnableSWPInstruction):
175  mrc     p15, 0, r0, c1, c0, 0
176  orr     r0, r0, #0x00000400
177  mcr     p15, 0, r0, c1, c0, 0
178  isb
179  bx      LR
180
181ASM_PFX(ArmEnableBranchPrediction):
182  mrc     p15, 0, r0, c1, c0, 0
183  orr     r0, r0, #0x00000800
184  mcr     p15, 0, r0, c1, c0, 0
185  dsb
186  isb
187  bx      LR
188
189ASM_PFX(ArmDisableBranchPrediction):
190  mrc     p15, 0, r0, c1, c0, 0
191  bic     r0, r0, #0x00000800
192  mcr     p15, 0, r0, c1, c0, 0
193  dsb
194  isb
195  bx      LR
196
197ASM_PFX(ArmSetLowVectors):
198  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
199  bic     r0, r0, #0x00002000   @ clear V bit
200  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
201  isb
202  bx      LR
203
204ASM_PFX(ArmSetHighVectors):
205  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
206  orr     r0, r0, #0x00002000   @ Set V bit
207  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
208  isb
209  bx      LR
210
211ASM_PFX(ArmV7AllDataCachesOperation):
212  stmfd SP!,{r4-r12, LR}
213  mov   R1, R0                @ Save Function call in R1
214  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
215  ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
216  mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
217  beq   L_Finished
218  mov   R10, #0
219
220Loop1:
221  add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
222  mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
223  and   R12, R12, #7          @ get those 3 bits alone
224  cmp   R12, #2
225  blt   L_Skip                  @ no cache or only instruction cache at this level
226  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
227  isb                           @ isb to sync the change to the CacheSizeID reg
228  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
229  and   R2, R12, #0x7           @ extract the line length field
230  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
231@  ldr   R4, =0x3FF
232  mov   R4, #0x400
233  sub   R4, R4, #1
234  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
235  clz   R5, R4                  @ R5 is the bit position of the way size increment
236@  ldr   R7, =0x00007FFF
237  mov   R7, #0x00008000
238  sub   R7, R7, #1
239  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
240
241Loop2:
242  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
243
244Loop3:
245  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
246  orr   R0, R0, R7, LSL R2      @ factor in the index number
247
248  blx   R1
249
250  subs  R9, R9, #1              @ decrement the way number
251  bge   Loop3
252  subs  R7, R7, #1              @ decrement the index
253  bge   Loop2
254L_Skip:
255  add   R10, R10, #2            @ increment the cache number
256  cmp   R3, R10
257  bgt   Loop1
258
259L_Finished:
260  dsb
261  ldmfd SP!, {r4-r12, lr}
262  bx    LR
263
264ASM_PFX(ArmDataMemoryBarrier):
265  dmb
266  bx      LR
267
268ASM_PFX(ArmDataSynchronizationBarrier):
269  dsb
270  bx      LR
271
272ASM_PFX(ArmInstructionSynchronizationBarrier):
273  isb
274  bx      LR
275
276ASM_PFX(ArmReadVBar):
277  # Set the Address of the Vector Table in the VBAR register
278  mrc     p15, 0, r0, c12, c0, 0
279  bx      lr
280
281ASM_PFX(ArmWriteVBar):
282  # Set the Address of the Vector Table in the VBAR register
283  mcr     p15, 0, r0, c12, c0, 0
284  # Ensure the SCTLR.V bit is clear
285  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
286  bic     r0, r0, #0x00002000   @ clear V bit
287  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
288  isb
289  bx      lr
290
291ASM_PFX(ArmEnableVFP):
292  # Read CPACR (Coprocessor Access Control Register)
293  mrc     p15, 0, r0, c1, c0, 2
294  # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
295  orr     r0, r0, #0x00f00000
296  # Write back CPACR (Coprocessor Access Control Register)
297  mcr     p15, 0, r0, c1, c0, 2
298  isb
299  # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
300  mov     r0, #0x40000000
301#ifndef __clang__
302  mcr     p10,#0x7,r0,c8,c0,#0
303#else
304  vmsr    fpexc, r0
305#endif
306  bx      lr
307
308ASM_PFX(ArmCallWFI):
309  wfi
310  bx      lr
311
312#Note: Return 0 in Uniprocessor implementation
313ASM_PFX(ArmReadCbar):
314  mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
315  bx      lr
316
317ASM_PFX(ArmReadMpidr):
318  mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
319  bx      lr
320
321ASM_PFX(ArmReadTpidrurw):
322  mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
323  bx      lr
324
325ASM_PFX(ArmWriteTpidrurw):
326  mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
327  bx      lr
328
329ASM_PFX(ArmIsArchTimerImplemented):
330  mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
331  and    r0, r0, #0x000F0000
332  bx     lr
333
334ASM_PFX(ArmReadIdPfr1):
335  mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
336  bx     lr
337
338ASM_PFX(ArmReadIdMmfr0):
339  mrc    p15, 0, r0, c0, c1, 4     @ Read ID_MMFR0 Register
340  bx     lr
341
342ASM_FUNCTION_REMOVE_IF_UNREFERENCED
343