1 /*++ 2 3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 13 Module Name: 14 15 EdkIIGluePciCf8Lib.h 16 17 Abstract: 18 19 Public header file for Pci Cf8 Lib 20 21 --*/ 22 23 #ifndef __EDKII_GLUE_PCI_CF8_LIB_H__ 24 #define __EDKII_GLUE_PCI_CF8_LIB_H__ 25 26 27 /** 28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an 29 address that can be passed to the PCI Library functions. 30 31 Computes an address that is compatible with the PCI Library functions. The 32 unused upper bits of Bus, Device, Function and Register are stripped prior to 33 the generation of the address. 34 35 @param Bus PCI Bus number. Range 0..255. 36 @param Device PCI Device number. Range 0..31. 37 @param Function PCI Function number. Range 0..7. 38 @param Register PCI Register number. Range 0..255. 39 40 @return The encode PCI address. 41 42 **/ 43 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \ 44 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) 45 46 /** 47 Reads an 8-bit PCI configuration register. 48 49 Reads and returns the 8-bit PCI configuration register specified by Address. 50 This function must guarantee that all PCI read and write operations are 51 serialized. 52 53 If Address > 0x0FFFFFFF, then ASSERT(). 54 If the register specified by Address >= 0x100, then ASSERT(). 55 56 @param Address Address that encodes the PCI Bus, Device, Function and 57 Register. 58 59 @return The read value from the PCI configuration register. 60 61 **/ 62 UINT8 63 EFIAPI 64 PciCf8Read8 ( 65 IN UINTN Address 66 ); 67 68 /** 69 Writes an 8-bit PCI configuration register. 70 71 Writes the 8-bit PCI configuration register specified by Address with the 72 value specified by Value. Value is returned. This function must guarantee 73 that all PCI read and write operations are serialized. 74 75 If Address > 0x0FFFFFFF, then ASSERT(). 76 If the register specified by Address >= 0x100, then ASSERT(). 77 78 @param Address Address that encodes the PCI Bus, Device, Function and 79 Register. 80 @param Value The value to write. 81 82 @return The value written to the PCI configuration register. 83 84 **/ 85 UINT8 86 EFIAPI 87 PciCf8Write8 ( 88 IN UINTN Address, 89 IN UINT8 Data 90 ); 91 92 /** 93 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with 94 an 8-bit value. 95 96 Reads the 8-bit PCI configuration register specified by Address, performs a 97 bitwise inclusive OR between the read result and the value specified by 98 OrData, and writes the result to the 8-bit PCI configuration register 99 specified by Address. The value written to the PCI configuration register is 100 returned. This function must guarantee that all PCI read and write operations 101 are serialized. 102 103 If Address > 0x0FFFFFFF, then ASSERT(). 104 If the register specified by Address >= 0x100, then ASSERT(). 105 106 @param Address Address that encodes the PCI Bus, Device, Function and 107 Register. 108 @param OrData The value to OR with the PCI configuration register. 109 110 @return The value written back to the PCI configuration register. 111 112 **/ 113 UINT8 114 EFIAPI 115 PciCf8Or8 ( 116 IN UINTN Address, 117 IN UINT8 OrData 118 ); 119 120 /** 121 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 122 value. 123 124 Reads the 8-bit PCI configuration register specified by Address, performs a 125 bitwise AND between the read result and the value specified by AndData, and 126 writes the result to the 8-bit PCI configuration register specified by 127 Address. The value written to the PCI configuration register is returned. 128 This function must guarantee that all PCI read and write operations are 129 serialized. 130 131 If Address > 0x0FFFFFFF, then ASSERT(). 132 If the register specified by Address >= 0x100, then ASSERT(). 133 134 @param Address Address that encodes the PCI Bus, Device, Function and 135 Register. 136 @param AndData The value to AND with the PCI configuration register. 137 138 @return The value written back to the PCI configuration register. 139 140 **/ 141 UINT8 142 EFIAPI 143 PciCf8And8 ( 144 IN UINTN Address, 145 IN UINT8 AndData 146 ); 147 148 /** 149 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 150 value, followed a bitwise inclusive OR with another 8-bit value. 151 152 Reads the 8-bit PCI configuration register specified by Address, performs a 153 bitwise AND between the read result and the value specified by AndData, 154 performs a bitwise inclusive OR between the result of the AND operation and 155 the value specified by OrData, and writes the result to the 8-bit PCI 156 configuration register specified by Address. The value written to the PCI 157 configuration register is returned. This function must guarantee that all PCI 158 read and write operations are serialized. 159 160 If Address > 0x0FFFFFFF, then ASSERT(). 161 If the register specified by Address >= 0x100, then ASSERT(). 162 163 @param Address Address that encodes the PCI Bus, Device, Function and 164 Register. 165 @param AndData The value to AND with the PCI configuration register. 166 @param OrData The value to OR with the result of the AND operation. 167 168 @return The value written back to the PCI configuration register. 169 170 **/ 171 UINT8 172 EFIAPI 173 PciCf8AndThenOr8 ( 174 IN UINTN Address, 175 IN UINT8 AndData, 176 IN UINT8 OrData 177 ); 178 179 /** 180 Reads a bit field of a PCI configuration register. 181 182 Reads the bit field in an 8-bit PCI configuration register. The bit field is 183 specified by the StartBit and the EndBit. The value of the bit field is 184 returned. 185 186 If Address > 0x0FFFFFFF, then ASSERT(). 187 If the register specified by Address >= 0x100, then ASSERT(). 188 If StartBit is greater than 7, then ASSERT(). 189 If EndBit is greater than 7, then ASSERT(). 190 If EndBit is less than StartBit, then ASSERT(). 191 192 @param Address PCI configuration register to read. 193 @param StartBit The ordinal of the least significant bit in the bit field. 194 Range 0..7. 195 @param EndBit The ordinal of the most significant bit in the bit field. 196 Range 0..7. 197 198 @return The value of the bit field read from the PCI configuration register. 199 200 **/ 201 UINT8 202 EFIAPI 203 PciCf8BitFieldRead8 ( 204 IN UINTN Address, 205 IN UINTN StartBit, 206 IN UINTN EndBit 207 ); 208 209 /** 210 Writes a bit field to a PCI configuration register. 211 212 Writes Value to the bit field of the PCI configuration register. The bit 213 field is specified by the StartBit and the EndBit. All other bits in the 214 destination PCI configuration register are preserved. The new value of the 215 8-bit register is returned. 216 217 If Address > 0x0FFFFFFF, then ASSERT(). 218 If the register specified by Address >= 0x100, then ASSERT(). 219 If StartBit is greater than 7, then ASSERT(). 220 If EndBit is greater than 7, then ASSERT(). 221 If EndBit is less than StartBit, then ASSERT(). 222 223 @param Address PCI configuration register to write. 224 @param StartBit The ordinal of the least significant bit in the bit field. 225 Range 0..7. 226 @param EndBit The ordinal of the most significant bit in the bit field. 227 Range 0..7. 228 @param Value New value of the bit field. 229 230 @return The value written back to the PCI configuration register. 231 232 **/ 233 UINT8 234 EFIAPI 235 PciCf8BitFieldWrite8 ( 236 IN UINTN Address, 237 IN UINTN StartBit, 238 IN UINTN EndBit, 239 IN UINT8 Value 240 ); 241 242 /** 243 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 244 writes the result back to the bit field in the 8-bit port. 245 246 Reads the 8-bit PCI configuration register specified by Address, performs a 247 bitwise inclusive OR between the read result and the value specified by 248 OrData, and writes the result to the 8-bit PCI configuration register 249 specified by Address. The value written to the PCI configuration register is 250 returned. This function must guarantee that all PCI read and write operations 251 are serialized. Extra left bits in OrData are stripped. 252 253 If Address > 0x0FFFFFFF, then ASSERT(). 254 If the register specified by Address >= 0x100, then ASSERT(). 255 If StartBit is greater than 7, then ASSERT(). 256 If EndBit is greater than 7, then ASSERT(). 257 If EndBit is less than StartBit, then ASSERT(). 258 259 @param Address PCI configuration register to write. 260 @param StartBit The ordinal of the least significant bit in the bit field. 261 Range 0..7. 262 @param EndBit The ordinal of the most significant bit in the bit field. 263 Range 0..7. 264 @param OrData The value to OR with the PCI configuration register. 265 266 @return The value written back to the PCI configuration register. 267 268 **/ 269 UINT8 270 EFIAPI 271 PciCf8BitFieldOr8 ( 272 IN UINTN Address, 273 IN UINTN StartBit, 274 IN UINTN EndBit, 275 IN UINT8 OrData 276 ); 277 278 /** 279 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 280 AND, and writes the result back to the bit field in the 8-bit register. 281 282 Reads the 8-bit PCI configuration register specified by Address, performs a 283 bitwise AND between the read result and the value specified by AndData, and 284 writes the result to the 8-bit PCI configuration register specified by 285 Address. The value written to the PCI configuration register is returned. 286 This function must guarantee that all PCI read and write operations are 287 serialized. Extra left bits in AndData are stripped. 288 289 If Address > 0x0FFFFFFF, then ASSERT(). 290 If the register specified by Address >= 0x100, then ASSERT(). 291 If StartBit is greater than 7, then ASSERT(). 292 If EndBit is greater than 7, then ASSERT(). 293 If EndBit is less than StartBit, then ASSERT(). 294 295 @param Address PCI configuration register to write. 296 @param StartBit The ordinal of the least significant bit in the bit field. 297 Range 0..7. 298 @param EndBit The ordinal of the most significant bit in the bit field. 299 Range 0..7. 300 @param AndData The value to AND with the PCI configuration register. 301 302 @return The value written back to the PCI configuration register. 303 304 **/ 305 UINT8 306 EFIAPI 307 PciCf8BitFieldAnd8 ( 308 IN UINTN Address, 309 IN UINTN StartBit, 310 IN UINTN EndBit, 311 IN UINT8 AndData 312 ); 313 314 /** 315 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 316 bitwise inclusive OR, and writes the result back to the bit field in the 317 8-bit port. 318 319 Reads the 8-bit PCI configuration register specified by Address, performs a 320 bitwise AND followed by a bitwise inclusive OR between the read result and 321 the value specified by AndData, and writes the result to the 8-bit PCI 322 configuration register specified by Address. The value written to the PCI 323 configuration register is returned. This function must guarantee that all PCI 324 read and write operations are serialized. Extra left bits in both AndData and 325 OrData are stripped. 326 327 If Address > 0x0FFFFFFF, then ASSERT(). 328 If the register specified by Address >= 0x100, then ASSERT(). 329 If StartBit is greater than 7, then ASSERT(). 330 If EndBit is greater than 7, then ASSERT(). 331 If EndBit is less than StartBit, then ASSERT(). 332 333 @param Address PCI configuration register to write. 334 @param StartBit The ordinal of the least significant bit in the bit field. 335 Range 0..7. 336 @param EndBit The ordinal of the most significant bit in the bit field. 337 Range 0..7. 338 @param AndData The value to AND with the PCI configuration register. 339 @param OrData The value to OR with the result of the AND operation. 340 341 @return The value written back to the PCI configuration register. 342 343 **/ 344 UINT8 345 EFIAPI 346 PciCf8BitFieldAndThenOr8 ( 347 IN UINTN Address, 348 IN UINTN StartBit, 349 IN UINTN EndBit, 350 IN UINT8 AndData, 351 IN UINT8 OrData 352 ); 353 354 /** 355 Reads a 16-bit PCI configuration register. 356 357 Reads and returns the 16-bit PCI configuration register specified by Address. 358 This function must guarantee that all PCI read and write operations are 359 serialized. 360 361 If Address > 0x0FFFFFFF, then ASSERT(). 362 If Address is not aligned on a 16-bit boundary, then ASSERT(). 363 If the register specified by Address >= 0x100, then ASSERT(). 364 365 @param Address Address that encodes the PCI Bus, Device, Function and 366 Register. 367 368 @return The read value from the PCI configuration register. 369 370 **/ 371 UINT16 372 EFIAPI 373 PciCf8Read16 ( 374 IN UINTN Address 375 ); 376 377 /** 378 Writes a 16-bit PCI configuration register. 379 380 Writes the 16-bit PCI configuration register specified by Address with the 381 value specified by Value. Value is returned. This function must guarantee 382 that all PCI read and write operations are serialized. 383 384 If Address > 0x0FFFFFFF, then ASSERT(). 385 If Address is not aligned on a 16-bit boundary, then ASSERT(). 386 If the register specified by Address >= 0x100, then ASSERT(). 387 388 @param Address Address that encodes the PCI Bus, Device, Function and 389 Register. 390 @param Value The value to write. 391 392 @return The value written to the PCI configuration register. 393 394 **/ 395 UINT16 396 EFIAPI 397 PciCf8Write16 ( 398 IN UINTN Address, 399 IN UINT16 Data 400 ); 401 402 /** 403 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with 404 a 16-bit value. 405 406 Reads the 16-bit PCI configuration register specified by Address, performs a 407 bitwise inclusive OR between the read result and the value specified by 408 OrData, and writes the result to the 16-bit PCI configuration register 409 specified by Address. The value written to the PCI configuration register is 410 returned. This function must guarantee that all PCI read and write operations 411 are serialized. 412 413 If Address > 0x0FFFFFFF, then ASSERT(). 414 If Address is not aligned on a 16-bit boundary, then ASSERT(). 415 If the register specified by Address >= 0x100, then ASSERT(). 416 417 @param Address Address that encodes the PCI Bus, Device, Function and 418 Register. 419 @param OrData The value to OR with the PCI configuration register. 420 421 @return The value written back to the PCI configuration register. 422 423 **/ 424 UINT16 425 EFIAPI 426 PciCf8Or16 ( 427 IN UINTN Address, 428 IN UINT16 OrData 429 ); 430 431 /** 432 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 433 value. 434 435 Reads the 16-bit PCI configuration register specified by Address, performs a 436 bitwise AND between the read result and the value specified by AndData, and 437 writes the result to the 16-bit PCI configuration register specified by 438 Address. The value written to the PCI configuration register is returned. 439 This function must guarantee that all PCI read and write operations are 440 serialized. 441 442 If Address > 0x0FFFFFFF, then ASSERT(). 443 If Address is not aligned on a 16-bit boundary, then ASSERT(). 444 If the register specified by Address >= 0x100, then ASSERT(). 445 446 @param Address Address that encodes the PCI Bus, Device, Function and 447 Register. 448 @param AndData The value to AND with the PCI configuration register. 449 450 @return The value written back to the PCI configuration register. 451 452 **/ 453 UINT16 454 EFIAPI 455 PciCf8And16 ( 456 IN UINTN Address, 457 IN UINT16 AndData 458 ); 459 460 /** 461 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 462 value, followed a bitwise inclusive OR with another 16-bit value. 463 464 Reads the 16-bit PCI configuration register specified by Address, performs a 465 bitwise AND between the read result and the value specified by AndData, 466 performs a bitwise inclusive OR between the result of the AND operation and 467 the value specified by OrData, and writes the result to the 16-bit PCI 468 configuration register specified by Address. The value written to the PCI 469 configuration register is returned. This function must guarantee that all PCI 470 read and write operations are serialized. 471 472 If Address > 0x0FFFFFFF, then ASSERT(). 473 If Address is not aligned on a 16-bit boundary, then ASSERT(). 474 If the register specified by Address >= 0x100, then ASSERT(). 475 476 @param Address Address that encodes the PCI Bus, Device, Function and 477 Register. 478 @param AndData The value to AND with the PCI configuration register. 479 @param OrData The value to OR with the result of the AND operation. 480 481 @return The value written back to the PCI configuration register. 482 483 **/ 484 UINT16 485 EFIAPI 486 PciCf8AndThenOr16 ( 487 IN UINTN Address, 488 IN UINT16 AndData, 489 IN UINT16 OrData 490 ); 491 492 /** 493 Reads a bit field of a PCI configuration register. 494 495 Reads the bit field in a 16-bit PCI configuration register. The bit field is 496 specified by the StartBit and the EndBit. The value of the bit field is 497 returned. 498 499 If Address > 0x0FFFFFFF, then ASSERT(). 500 If Address is not aligned on a 16-bit boundary, then ASSERT(). 501 If the register specified by Address >= 0x100, then ASSERT(). 502 If StartBit is greater than 15, then ASSERT(). 503 If EndBit is greater than 15, then ASSERT(). 504 If EndBit is less than StartBit, then ASSERT(). 505 506 @param Address PCI configuration register to read. 507 @param StartBit The ordinal of the least significant bit in the bit field. 508 Range 0..15. 509 @param EndBit The ordinal of the most significant bit in the bit field. 510 Range 0..15. 511 512 @return The value of the bit field read from the PCI configuration register. 513 514 **/ 515 UINT16 516 EFIAPI 517 PciCf8BitFieldRead16 ( 518 IN UINTN Address, 519 IN UINTN StartBit, 520 IN UINTN EndBit 521 ); 522 523 /** 524 Writes a bit field to a PCI configuration register. 525 526 Writes Value to the bit field of the PCI configuration register. The bit 527 field is specified by the StartBit and the EndBit. All other bits in the 528 destination PCI configuration register are preserved. The new value of the 529 16-bit register is returned. 530 531 If Address > 0x0FFFFFFF, then ASSERT(). 532 If Address is not aligned on a 16-bit boundary, then ASSERT(). 533 If the register specified by Address >= 0x100, then ASSERT(). 534 If StartBit is greater than 15, then ASSERT(). 535 If EndBit is greater than 15, then ASSERT(). 536 If EndBit is less than StartBit, then ASSERT(). 537 538 @param Address PCI configuration register to write. 539 @param StartBit The ordinal of the least significant bit in the bit field. 540 Range 0..15. 541 @param EndBit The ordinal of the most significant bit in the bit field. 542 Range 0..15. 543 @param Value New value of the bit field. 544 545 @return The value written back to the PCI configuration register. 546 547 **/ 548 UINT16 549 EFIAPI 550 PciCf8BitFieldWrite16 ( 551 IN UINTN Address, 552 IN UINTN StartBit, 553 IN UINTN EndBit, 554 IN UINT16 Value 555 ); 556 557 /** 558 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 559 writes the result back to the bit field in the 16-bit port. 560 561 Reads the 16-bit PCI configuration register specified by Address, performs a 562 bitwise inclusive OR between the read result and the value specified by 563 OrData, and writes the result to the 16-bit PCI configuration register 564 specified by Address. The value written to the PCI configuration register is 565 returned. This function must guarantee that all PCI read and write operations 566 are serialized. Extra left bits in OrData are stripped. 567 568 If Address > 0x0FFFFFFF, then ASSERT(). 569 If Address is not aligned on a 16-bit boundary, then ASSERT(). 570 If the register specified by Address >= 0x100, then ASSERT(). 571 If StartBit is greater than 15, then ASSERT(). 572 If EndBit is greater than 15, then ASSERT(). 573 If EndBit is less than StartBit, then ASSERT(). 574 575 @param Address PCI configuration register to write. 576 @param StartBit The ordinal of the least significant bit in the bit field. 577 Range 0..15. 578 @param EndBit The ordinal of the most significant bit in the bit field. 579 Range 0..15. 580 @param OrData The value to OR with the PCI configuration register. 581 582 @return The value written back to the PCI configuration register. 583 584 **/ 585 UINT16 586 EFIAPI 587 PciCf8BitFieldOr16 ( 588 IN UINTN Address, 589 IN UINTN StartBit, 590 IN UINTN EndBit, 591 IN UINT16 OrData 592 ); 593 594 /** 595 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 596 AND, and writes the result back to the bit field in the 16-bit register. 597 598 Reads the 16-bit PCI configuration register specified by Address, performs a 599 bitwise AND between the read result and the value specified by AndData, and 600 writes the result to the 16-bit PCI configuration register specified by 601 Address. The value written to the PCI configuration register is returned. 602 This function must guarantee that all PCI read and write operations are 603 serialized. Extra left bits in AndData are stripped. 604 605 If Address > 0x0FFFFFFF, then ASSERT(). 606 If Address is not aligned on a 16-bit boundary, then ASSERT(). 607 If the register specified by Address >= 0x100, then ASSERT(). 608 If StartBit is greater than 15, then ASSERT(). 609 If EndBit is greater than 15, then ASSERT(). 610 If EndBit is less than StartBit, then ASSERT(). 611 612 @param Address PCI configuration register to write. 613 @param StartBit The ordinal of the least significant bit in the bit field. 614 Range 0..15. 615 @param EndBit The ordinal of the most significant bit in the bit field. 616 Range 0..15. 617 @param AndData The value to AND with the PCI configuration register. 618 619 @return The value written back to the PCI configuration register. 620 621 **/ 622 UINT16 623 EFIAPI 624 PciCf8BitFieldAnd16 ( 625 IN UINTN Address, 626 IN UINTN StartBit, 627 IN UINTN EndBit, 628 IN UINT16 AndData 629 ); 630 631 /** 632 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 633 bitwise inclusive OR, and writes the result back to the bit field in the 634 16-bit port. 635 636 Reads the 16-bit PCI configuration register specified by Address, performs a 637 bitwise AND followed by a bitwise inclusive OR between the read result and 638 the value specified by AndData, and writes the result to the 16-bit PCI 639 configuration register specified by Address. The value written to the PCI 640 configuration register is returned. This function must guarantee that all PCI 641 read and write operations are serialized. Extra left bits in both AndData and 642 OrData are stripped. 643 644 If Address > 0x0FFFFFFF, then ASSERT(). 645 If Address is not aligned on a 16-bit boundary, then ASSERT(). 646 If the register specified by Address >= 0x100, then ASSERT(). 647 If StartBit is greater than 15, then ASSERT(). 648 If EndBit is greater than 15, then ASSERT(). 649 If EndBit is less than StartBit, then ASSERT(). 650 651 @param Address PCI configuration register to write. 652 @param StartBit The ordinal of the least significant bit in the bit field. 653 Range 0..15. 654 @param EndBit The ordinal of the most significant bit in the bit field. 655 Range 0..15. 656 @param AndData The value to AND with the PCI configuration register. 657 @param OrData The value to OR with the result of the AND operation. 658 659 @return The value written back to the PCI configuration register. 660 661 **/ 662 UINT16 663 EFIAPI 664 PciCf8BitFieldAndThenOr16 ( 665 IN UINTN Address, 666 IN UINTN StartBit, 667 IN UINTN EndBit, 668 IN UINT16 AndData, 669 IN UINT16 OrData 670 ); 671 672 /** 673 Reads a 32-bit PCI configuration register. 674 675 Reads and returns the 32-bit PCI configuration register specified by Address. 676 This function must guarantee that all PCI read and write operations are 677 serialized. 678 679 If Address > 0x0FFFFFFF, then ASSERT(). 680 If Address is not aligned on a 32-bit boundary, then ASSERT(). 681 If the register specified by Address >= 0x100, then ASSERT(). 682 683 @param Address Address that encodes the PCI Bus, Device, Function and 684 Register. 685 686 @return The read value from the PCI configuration register. 687 688 **/ 689 UINT32 690 EFIAPI 691 PciCf8Read32 ( 692 IN UINTN Address 693 ); 694 695 /** 696 Writes a 32-bit PCI configuration register. 697 698 Writes the 32-bit PCI configuration register specified by Address with the 699 value specified by Value. Value is returned. This function must guarantee 700 that all PCI read and write operations are serialized. 701 702 If Address > 0x0FFFFFFF, then ASSERT(). 703 If Address is not aligned on a 32-bit boundary, then ASSERT(). 704 If the register specified by Address >= 0x100, then ASSERT(). 705 706 @param Address Address that encodes the PCI Bus, Device, Function and 707 Register. 708 @param Value The value to write. 709 710 @return The value written to the PCI configuration register. 711 712 **/ 713 UINT32 714 EFIAPI 715 PciCf8Write32 ( 716 IN UINTN Address, 717 IN UINT32 Data 718 ); 719 720 /** 721 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with 722 a 32-bit value. 723 724 Reads the 32-bit PCI configuration register specified by Address, performs a 725 bitwise inclusive OR between the read result and the value specified by 726 OrData, and writes the result to the 32-bit PCI configuration register 727 specified by Address. The value written to the PCI configuration register is 728 returned. This function must guarantee that all PCI read and write operations 729 are serialized. 730 731 If Address > 0x0FFFFFFF, then ASSERT(). 732 If Address is not aligned on a 32-bit boundary, then ASSERT(). 733 If the register specified by Address >= 0x100, then ASSERT(). 734 735 @param Address Address that encodes the PCI Bus, Device, Function and 736 Register. 737 @param OrData The value to OR with the PCI configuration register. 738 739 @return The value written back to the PCI configuration register. 740 741 **/ 742 UINT32 743 EFIAPI 744 PciCf8Or32 ( 745 IN UINTN Address, 746 IN UINT32 OrData 747 ); 748 749 /** 750 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 751 value. 752 753 Reads the 32-bit PCI configuration register specified by Address, performs a 754 bitwise AND between the read result and the value specified by AndData, and 755 writes the result to the 32-bit PCI configuration register specified by 756 Address. The value written to the PCI configuration register is returned. 757 This function must guarantee that all PCI read and write operations are 758 serialized. 759 760 If Address > 0x0FFFFFFF, then ASSERT(). 761 If Address is not aligned on a 32-bit boundary, then ASSERT(). 762 If the register specified by Address >= 0x100, then ASSERT(). 763 764 @param Address Address that encodes the PCI Bus, Device, Function and 765 Register. 766 @param AndData The value to AND with the PCI configuration register. 767 768 @return The value written back to the PCI configuration register. 769 770 **/ 771 UINT32 772 EFIAPI 773 PciCf8And32 ( 774 IN UINTN Address, 775 IN UINT32 AndData 776 ); 777 778 /** 779 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 780 value, followed a bitwise inclusive OR with another 32-bit value. 781 782 Reads the 32-bit PCI configuration register specified by Address, performs a 783 bitwise AND between the read result and the value specified by AndData, 784 performs a bitwise inclusive OR between the result of the AND operation and 785 the value specified by OrData, and writes the result to the 32-bit PCI 786 configuration register specified by Address. The value written to the PCI 787 configuration register is returned. This function must guarantee that all PCI 788 read and write operations are serialized. 789 790 If Address > 0x0FFFFFFF, then ASSERT(). 791 If Address is not aligned on a 32-bit boundary, then ASSERT(). 792 If the register specified by Address >= 0x100, then ASSERT(). 793 794 @param Address Address that encodes the PCI Bus, Device, Function and 795 Register. 796 @param AndData The value to AND with the PCI configuration register. 797 @param OrData The value to OR with the result of the AND operation. 798 799 @return The value written back to the PCI configuration register. 800 801 **/ 802 UINT32 803 EFIAPI 804 PciCf8AndThenOr32 ( 805 IN UINTN Address, 806 IN UINT32 AndData, 807 IN UINT32 OrData 808 ); 809 810 /** 811 Reads a bit field of a PCI configuration register. 812 813 Reads the bit field in a 32-bit PCI configuration register. The bit field is 814 specified by the StartBit and the EndBit. The value of the bit field is 815 returned. 816 817 If Address > 0x0FFFFFFF, then ASSERT(). 818 If Address is not aligned on a 32-bit boundary, then ASSERT(). 819 If the register specified by Address >= 0x100, then ASSERT(). 820 If StartBit is greater than 31, then ASSERT(). 821 If EndBit is greater than 31, then ASSERT(). 822 If EndBit is less than StartBit, then ASSERT(). 823 824 @param Address PCI configuration register to read. 825 @param StartBit The ordinal of the least significant bit in the bit field. 826 Range 0..31. 827 @param EndBit The ordinal of the most significant bit in the bit field. 828 Range 0..31. 829 830 @return The value of the bit field read from the PCI configuration register. 831 832 **/ 833 UINT32 834 EFIAPI 835 PciCf8BitFieldRead32 ( 836 IN UINTN Address, 837 IN UINTN StartBit, 838 IN UINTN EndBit 839 ); 840 841 /** 842 Writes a bit field to a PCI configuration register. 843 844 Writes Value to the bit field of the PCI configuration register. The bit 845 field is specified by the StartBit and the EndBit. All other bits in the 846 destination PCI configuration register are preserved. The new value of the 847 32-bit register is returned. 848 849 If Address > 0x0FFFFFFF, then ASSERT(). 850 If Address is not aligned on a 32-bit boundary, then ASSERT(). 851 If the register specified by Address >= 0x100, then ASSERT(). 852 If StartBit is greater than 31, then ASSERT(). 853 If EndBit is greater than 31, then ASSERT(). 854 If EndBit is less than StartBit, then ASSERT(). 855 856 @param Address PCI configuration register to write. 857 @param StartBit The ordinal of the least significant bit in the bit field. 858 Range 0..31. 859 @param EndBit The ordinal of the most significant bit in the bit field. 860 Range 0..31. 861 @param Value New value of the bit field. 862 863 @return The value written back to the PCI configuration register. 864 865 **/ 866 UINT32 867 EFIAPI 868 PciCf8BitFieldWrite32 ( 869 IN UINTN Address, 870 IN UINTN StartBit, 871 IN UINTN EndBit, 872 IN UINT32 Value 873 ); 874 875 /** 876 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 877 writes the result back to the bit field in the 32-bit port. 878 879 Reads the 32-bit PCI configuration register specified by Address, performs a 880 bitwise inclusive OR between the read result and the value specified by 881 OrData, and writes the result to the 32-bit PCI configuration register 882 specified by Address. The value written to the PCI configuration register is 883 returned. This function must guarantee that all PCI read and write operations 884 are serialized. Extra left bits in OrData are stripped. 885 886 If Address > 0x0FFFFFFF, then ASSERT(). 887 If Address is not aligned on a 32-bit boundary, then ASSERT(). 888 If the register specified by Address >= 0x100, then ASSERT(). 889 If StartBit is greater than 31, then ASSERT(). 890 If EndBit is greater than 31, then ASSERT(). 891 If EndBit is less than StartBit, then ASSERT(). 892 893 @param Address PCI configuration register to write. 894 @param StartBit The ordinal of the least significant bit in the bit field. 895 Range 0..31. 896 @param EndBit The ordinal of the most significant bit in the bit field. 897 Range 0..31. 898 @param OrData The value to OR with the PCI configuration register. 899 900 @return The value written back to the PCI configuration register. 901 902 **/ 903 UINT32 904 EFIAPI 905 PciCf8BitFieldOr32 ( 906 IN UINTN Address, 907 IN UINTN StartBit, 908 IN UINTN EndBit, 909 IN UINT32 OrData 910 ); 911 912 /** 913 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 914 AND, and writes the result back to the bit field in the 32-bit register. 915 916 Reads the 32-bit PCI configuration register specified by Address, performs a 917 bitwise AND between the read result and the value specified by AndData, and 918 writes the result to the 32-bit PCI configuration register specified by 919 Address. The value written to the PCI configuration register is returned. 920 This function must guarantee that all PCI read and write operations are 921 serialized. Extra left bits in AndData are stripped. 922 923 If Address > 0x0FFFFFFF, then ASSERT(). 924 If Address is not aligned on a 32-bit boundary, then ASSERT(). 925 If the register specified by Address >= 0x100, then ASSERT(). 926 If StartBit is greater than 31, then ASSERT(). 927 If EndBit is greater than 31, then ASSERT(). 928 If EndBit is less than StartBit, then ASSERT(). 929 930 @param Address PCI configuration register to write. 931 @param StartBit The ordinal of the least significant bit in the bit field. 932 Range 0..31. 933 @param EndBit The ordinal of the most significant bit in the bit field. 934 Range 0..31. 935 @param AndData The value to AND with the PCI configuration register. 936 937 @return The value written back to the PCI configuration register. 938 939 **/ 940 UINT32 941 EFIAPI 942 PciCf8BitFieldAnd32 ( 943 IN UINTN Address, 944 IN UINTN StartBit, 945 IN UINTN EndBit, 946 IN UINT32 AndData 947 ); 948 949 /** 950 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 951 bitwise inclusive OR, and writes the result back to the bit field in the 952 32-bit port. 953 954 Reads the 32-bit PCI configuration register specified by Address, performs a 955 bitwise AND followed by a bitwise inclusive OR between the read result and 956 the value specified by AndData, and writes the result to the 32-bit PCI 957 configuration register specified by Address. The value written to the PCI 958 configuration register is returned. This function must guarantee that all PCI 959 read and write operations are serialized. Extra left bits in both AndData and 960 OrData are stripped. 961 962 If Address > 0x0FFFFFFF, then ASSERT(). 963 If Address is not aligned on a 32-bit boundary, then ASSERT(). 964 If the register specified by Address >= 0x100, then ASSERT(). 965 If StartBit is greater than 31, then ASSERT(). 966 If EndBit is greater than 31, then ASSERT(). 967 If EndBit is less than StartBit, then ASSERT(). 968 969 @param Address PCI configuration register to write. 970 @param StartBit The ordinal of the least significant bit in the bit field. 971 Range 0..31. 972 @param EndBit The ordinal of the most significant bit in the bit field. 973 Range 0..31. 974 @param AndData The value to AND with the PCI configuration register. 975 @param OrData The value to OR with the result of the AND operation. 976 977 @return The value written back to the PCI configuration register. 978 979 **/ 980 UINT32 981 EFIAPI 982 PciCf8BitFieldAndThenOr32 ( 983 IN UINTN Address, 984 IN UINTN StartBit, 985 IN UINTN EndBit, 986 IN UINT32 AndData, 987 IN UINT32 OrData 988 ); 989 990 /** 991 Reads a range of PCI configuration registers into a caller supplied buffer. 992 993 Reads the range of PCI configuration registers specified by StartAddress and 994 Size into the buffer specified by Buffer. This function only allows the PCI 995 configuration registers from a single PCI function to be read. Size is 996 returned. When possible 32-bit PCI configuration read cycles are used to read 997 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 998 and 16-bit PCI configuration read cycles may be used at the beginning and the 999 end of the range. 1000 1001 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1002 If the register specified by StartAddress >= 0x100, then ASSERT(). 1003 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). 1004 If Size > 0 and Buffer is NULL, then ASSERT(). 1005 1006 @param StartAddress Starting address that encodes the PCI Bus, Device, 1007 Function and Register. 1008 @param Size Size in bytes of the transfer. 1009 @param Buffer Pointer to a buffer receiving the data read. 1010 1011 @return Size 1012 1013 **/ 1014 UINTN 1015 EFIAPI 1016 PciCf8ReadBuffer ( 1017 IN UINTN StartAddress, 1018 IN UINTN Size, 1019 OUT VOID *Buffer 1020 ); 1021 1022 /** 1023 Copies the data in a caller supplied buffer to a specified range of PCI 1024 configuration space. 1025 1026 Writes the range of PCI configuration registers specified by StartAddress and 1027 Size from the buffer specified by Buffer. This function only allows the PCI 1028 configuration registers from a single PCI function to be written. Size is 1029 returned. When possible 32-bit PCI configuration write cycles are used to 1030 write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1031 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1032 and the end of the range. 1033 1034 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1035 If the register specified by StartAddress >= 0x100, then ASSERT(). 1036 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT(). 1037 If Size > 0 and Buffer is NULL, then ASSERT(). 1038 1039 @param StartAddress Starting address that encodes the PCI Bus, Device, 1040 Function and Register. 1041 @param Size Size in bytes of the transfer. 1042 @param Buffer Pointer to a buffer containing the data to write. 1043 1044 @return Size 1045 1046 **/ 1047 UINTN 1048 EFIAPI 1049 PciCf8WriteBuffer ( 1050 IN UINTN StartAddress, 1051 IN UINTN Size, 1052 IN VOID *Buffer 1053 ); 1054 1055 #endif 1056