1 /** @file 2 Library functions for Setting QNC internal network port 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __QNC_ACCESS_LIB_H__ 17 #define __QNC_ACCESS_LIB_H__ 18 19 #include <IntelQNCRegs.h> 20 21 #define MESSAGE_READ_DW(Port, Reg) \ 22 (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 23 24 #define MESSAGE_WRITE_DW(Port, Reg) \ 25 (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 26 27 #define ALT_MESSAGE_READ_DW(Port, Reg) \ 28 (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 29 30 #define ALT_MESSAGE_WRITE_DW(Port, Reg) \ 31 (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 32 33 #define MESSAGE_IO_READ_DW(Port, Reg) \ 34 (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 35 36 #define MESSAGE_IO_WRITE_DW(Port, Reg) \ 37 (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 38 39 #define MESSAGE_SHADOW_DW(Port, Reg) \ 40 (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) 41 42 43 /** 44 Read required data from QNC internal message network 45 **/ 46 UINT32 47 EFIAPI 48 QNCPortRead( 49 UINT8 Port, 50 UINT32 RegAddress 51 ); 52 53 /** 54 Write prepared data into QNC internal message network. 55 56 **/ 57 VOID 58 EFIAPI 59 QNCPortWrite ( 60 UINT8 Port, 61 UINT32 RegAddress, 62 UINT32 WriteValue 63 ); 64 65 /** 66 Read required data from QNC internal message network 67 **/ 68 UINT32 69 EFIAPI 70 QNCAltPortRead( 71 UINT8 Port, 72 UINT32 RegAddress 73 ); 74 75 /** 76 Write prepared data into QNC internal message network. 77 78 **/ 79 VOID 80 EFIAPI 81 QNCAltPortWrite ( 82 UINT8 Port, 83 UINT32 RegAddress, 84 UINT32 WriteValue 85 ); 86 87 /** 88 Read required data from QNC internal message network 89 **/ 90 UINT32 91 EFIAPI 92 QNCPortIORead( 93 UINT8 Port, 94 UINT32 RegAddress 95 ); 96 97 /** 98 Write prepared data into QNC internal message network. 99 100 **/ 101 VOID 102 EFIAPI 103 QNCPortIOWrite ( 104 UINT8 Port, 105 UINT32 RegAddress, 106 UINT32 WriteValue 107 ); 108 109 /** 110 This is for the special consideration for QNC MMIO write, as required by FWG, 111 a reading must be performed after MMIO writing to ensure the expected write 112 is processed and data is flushed into chipset 113 114 **/ 115 RETURN_STATUS 116 EFIAPI 117 QNCMmIoWrite ( 118 UINT32 MmIoAddress, 119 QNC_MEM_IO_WIDTH Width, 120 UINT32 DataNumber, 121 VOID *pData 122 ); 123 124 UINT32 125 EFIAPI 126 QncHsmmcRead ( 127 VOID 128 ); 129 130 VOID 131 EFIAPI 132 QncHsmmcWrite ( 133 UINT32 WriteValue 134 ); 135 136 VOID 137 EFIAPI 138 QncImrWrite ( 139 UINT32 ImrBaseOffset, 140 UINT32 ImrLow, 141 UINT32 ImrHigh, 142 UINT32 ImrReadMask, 143 UINT32 ImrWriteMask 144 ); 145 146 VOID 147 EFIAPI 148 QncIClkAndThenOr ( 149 UINT32 RegAddress, 150 UINT32 AndValue, 151 UINT32 OrValue 152 ); 153 154 VOID 155 EFIAPI 156 QncIClkOr ( 157 UINT32 RegAddress, 158 UINT32 OrValue 159 ); 160 161 UINTN 162 EFIAPI 163 QncGetPciExpressBaseAddress ( 164 VOID 165 ); 166 167 #endif 168