1 /** @file
2 Do platform initialization for PCI bridge.
3
4 Copyright (c) 2013-2015 Intel Corporation.
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14
15 **/
16
17 #include "PciHostBridge.h"
18
19 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
20
21 EFI_STATUS
ChipsetPreprocessController(IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL * This,IN EFI_HANDLE RootBridgeHandle,IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase)22 ChipsetPreprocessController (
23 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
24 IN EFI_HANDLE RootBridgeHandle,
25 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
26 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
27 )
28 /*++
29
30 Routine Description:
31 This function is called for all the PCI controllers that the PCI
32 bus driver finds. Can be used to Preprogram the controller.
33
34 Arguments:
35 This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
36 RootBridgeHandle -- The PCI Root Bridge handle
37 PciBusAddress -- Address of the controller on the PCI bus
38 Phase -- The Phase during resource allocation
39
40 Returns:
41 EFI_SUCCESS
42
43 --*/
44
45 // GC_TODO: PciAddress - add argument and description to function comment
46 //
47 // GC_TODO: PciAddress - add argument and description to function comment
48 //
49 // GC_TODO: PciAddress - add argument and description to function comment
50 //
51 // GC_TODO: PciAddress - add argument and description to function comment
52 //
53 {
54
55 EFI_STATUS Status;
56 UINT8 Latency;
57 UINT8 CacheLineSize;
58
59 if (mPciRootBridgeIo == NULL) {
60 //
61 // Get root bridge in the system.
62 //
63 Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);
64 ASSERT_EFI_ERROR (Status);
65 }
66
67 if (Phase == EfiPciBeforeResourceCollection) {
68 //
69 // Program the latency register, CLS register
70 //
71 PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;
72 mPciRootBridgeIo->Pci.Read (
73 mPciRootBridgeIo,
74 EfiPciWidthUint8,
75 *((UINT64 *) &PciAddress),
76 1,
77 &Latency
78 );
79
80 //
81 // PCI-x cards come up with a default latency of 0x40. Don't touch them.
82 //
83 if (Latency == 0) {
84 Latency = DEFAULT_PCI_LATENCY;
85 mPciRootBridgeIo->Pci.Write (
86 mPciRootBridgeIo,
87 EfiPciWidthUint8,
88 *((UINT64 *) &PciAddress),
89 1,
90 &Latency
91 );
92 }
93 //
94 // Program Cache Line Size as 64bytes
95 // 16 of DWORDs = 64bytes (0x10)
96 //
97 PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;
98 CacheLineSize = 0x10;
99 mPciRootBridgeIo->Pci.Write (
100 mPciRootBridgeIo,
101 EfiPciWidthUint8,
102 *((UINT64 *) &PciAddress),
103 1,
104 &CacheLineSize
105 );
106
107 }
108
109 return EFI_SUCCESS;
110 }
111
112 UINT64
GetAllocAttributes(IN UINTN RootBridgeIndex)113 GetAllocAttributes (
114 IN UINTN RootBridgeIndex
115 )
116 /*++
117
118 Routine Description:
119
120 Returns the Allocation attributes for the BNB Root Bridge.
121
122 Arguments:
123
124 RootBridgeIndex - The root bridge number. 0 based.
125
126 Returns:
127
128 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE
129
130 --*/
131 {
132 //
133 // Cannot have more than one Root bridge
134 //
135 //ASSERT (RootBridgeIndex == 0);
136
137 //
138 // PCI Root Bridge does not support separate windows for Non-prefetchable
139 // and Prefetchable memory. A PCI bus driver needs to include requests for
140 // Prefetchable memory in the Non-prefetchable memory pool.
141 // Further TNB does not support 64 bit memory apertures for PCI. BNB
142 // can only have system memory above 4 GB,
143 //
144
145 return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
146 }
147