1#
2# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
6#
7# Redistributions of source code must retain the above copyright notice, this
8# list of conditions and the following disclaimer.
9#
10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
12# and/or other materials provided with the distribution.
13#
14# Neither the name of ARM nor the names of its contributors may be used
15# to endorse or promote products derived from this software without specific
16# prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
31BL31_SOURCES		+=	bl31/bl31_main.c				\
32				bl31/context_mgmt.c				\
33				bl31/cpu_data_array.c				\
34				bl31/runtime_svc.c				\
35				bl31/interrupt_mgmt.c				\
36				bl31/aarch64/bl31_arch_setup.c			\
37				bl31/aarch64/bl31_entrypoint.S			\
38				bl31/aarch64/context.S				\
39				bl31/aarch64/cpu_data.S				\
40				bl31/aarch64/runtime_exceptions.S		\
41				bl31/aarch64/crash_reporting.S			\
42				lib/cpus/aarch64/cpu_helpers.S			\
43				lib/locks/exclusive/spinlock.S			\
44				services/std_svc/std_svc_setup.c		\
45				services/std_svc/psci/psci_afflvl_off.c		\
46				services/std_svc/psci/psci_afflvl_on.c		\
47				services/std_svc/psci/psci_afflvl_suspend.c	\
48				services/std_svc/psci/psci_common.c		\
49				services/std_svc/psci/psci_entry.S		\
50				services/std_svc/psci/psci_helpers.S		\
51				services/std_svc/psci/psci_main.c		\
52				services/std_svc/psci/psci_setup.c		\
53				services/std_svc/psci/psci_system_off.c
54
55ifeq (${USE_COHERENT_MEM}, 1)
56BL31_SOURCES		+=	lib/locks/bakery/bakery_lock_coherent.c
57else
58BL31_SOURCES		+=	lib/locks/bakery/bakery_lock_normal.c
59endif
60
61BL31_LINKERFILE		:=	bl31/bl31.ld.S
62
63# Flag used by the generic interrupt management framework to  determine if
64# upon the assertion of an interrupt, it should pass the interrupt id or not
65IMF_READ_INTERRUPT_ID	:=	0
66
67$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID))
68$(eval $(call add_define,IMF_READ_INTERRUPT_ID))
69
70# Flag used to inidicate if Crash reporting via console should be included
71# in BL3-1. This defaults to being present in DEBUG builds only
72ifndef CRASH_REPORTING
73CRASH_REPORTING		:=	$(DEBUG)
74endif
75
76$(eval $(call assert_boolean,CRASH_REPORTING))
77$(eval $(call add_define,CRASH_REPORTING))
78