1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <tsp.h>
34#include <xlat_tables.h>
35#include "../tsp_private.h"
36
37
38	.globl	tsp_entrypoint
39	.globl  tsp_vector_table
40
41
42
43	/* ---------------------------------------------
44	 * Populate the params in x0-x7 from the pointer
45	 * to the smc args structure in x0.
46	 * ---------------------------------------------
47	 */
48	.macro restore_args_call_smc
49	ldp	x6, x7, [x0, #TSP_ARG6]
50	ldp	x4, x5, [x0, #TSP_ARG4]
51	ldp	x2, x3, [x0, #TSP_ARG2]
52	ldp	x0, x1, [x0, #TSP_ARG0]
53	smc	#0
54	.endm
55
56	.macro	save_eret_context reg1 reg2
57	mrs	\reg1, elr_el1
58	mrs	\reg2, spsr_el1
59	stp	\reg1, \reg2, [sp, #-0x10]!
60	stp	x30, x18, [sp, #-0x10]!
61	.endm
62
63	.macro restore_eret_context reg1 reg2
64	ldp	x30, x18, [sp], #0x10
65	ldp	\reg1, \reg2, [sp], #0x10
66	msr	elr_el1, \reg1
67	msr	spsr_el1, \reg2
68	.endm
69
70	.section	.text, "ax"
71	.align 3
72
73func tsp_entrypoint
74
75	/* ---------------------------------------------
76	 * Set the exception vector to something sane.
77	 * ---------------------------------------------
78	 */
79	adr	x0, tsp_exceptions
80	msr	vbar_el1, x0
81	isb
82
83	/* ---------------------------------------------
84	 * Enable the SError interrupt now that the
85	 * exception vectors have been setup.
86	 * ---------------------------------------------
87	 */
88	msr	daifclr, #DAIF_ABT_BIT
89
90	/* ---------------------------------------------
91	 * Enable the instruction cache, stack pointer
92	 * and data access alignment checks
93	 * ---------------------------------------------
94	 */
95	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
96	mrs	x0, sctlr_el1
97	orr	x0, x0, x1
98	msr	sctlr_el1, x0
99	isb
100
101	/* ---------------------------------------------
102	 * Zero out NOBITS sections. There are 2 of them:
103	 *   - the .bss section;
104	 *   - the coherent memory section.
105	 * ---------------------------------------------
106	 */
107	ldr	x0, =__BSS_START__
108	ldr	x1, =__BSS_SIZE__
109	bl	zeromem16
110
111#if USE_COHERENT_MEM
112	ldr	x0, =__COHERENT_RAM_START__
113	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
114	bl	zeromem16
115#endif
116
117	/* --------------------------------------------
118	 * Allocate a stack whose memory will be marked
119	 * as Normal-IS-WBWA when the MMU is enabled.
120	 * There is no risk of reading stale stack
121	 * memory after enabling the MMU as only the
122	 * primary cpu is running at the moment.
123	 * --------------------------------------------
124	 */
125	mrs	x0, mpidr_el1
126	bl	platform_set_stack
127
128	/* ---------------------------------------------
129	 * Perform early platform setup & platform
130	 * specific early arch. setup e.g. mmu setup
131	 * ---------------------------------------------
132	 */
133	bl	tsp_early_platform_setup
134	bl	tsp_plat_arch_setup
135
136	/* ---------------------------------------------
137	 * Jump to main function.
138	 * ---------------------------------------------
139	 */
140	bl	tsp_main
141
142	/* ---------------------------------------------
143	 * Tell TSPD that we are done initialising
144	 * ---------------------------------------------
145	 */
146	mov	x1, x0
147	mov	x0, #TSP_ENTRY_DONE
148	smc	#0
149
150tsp_entrypoint_panic:
151	b	tsp_entrypoint_panic
152
153
154	/* -------------------------------------------
155	 * Table of entrypoint vectors provided to the
156	 * TSPD for the various entrypoints
157	 * -------------------------------------------
158	 */
159func tsp_vector_table
160	b	tsp_std_smc_entry
161	b	tsp_fast_smc_entry
162	b	tsp_cpu_on_entry
163	b	tsp_cpu_off_entry
164	b	tsp_cpu_resume_entry
165	b	tsp_cpu_suspend_entry
166	b	tsp_fiq_entry
167	b	tsp_system_off_entry
168	b	tsp_system_reset_entry
169
170	/*---------------------------------------------
171	 * This entrypoint is used by the TSPD when this
172	 * cpu is to be turned off through a CPU_OFF
173	 * psci call to ask the TSP to perform any
174	 * bookeeping necessary. In the current
175	 * implementation, the TSPD expects the TSP to
176	 * re-initialise its state so nothing is done
177	 * here except for acknowledging the request.
178	 * ---------------------------------------------
179	 */
180func tsp_cpu_off_entry
181	bl	tsp_cpu_off_main
182	restore_args_call_smc
183
184	/*---------------------------------------------
185	 * This entrypoint is used by the TSPD when the
186	 * system is about to be switched off (through
187	 * a SYSTEM_OFF psci call) to ask the TSP to
188	 * perform any necessary bookkeeping.
189	 * ---------------------------------------------
190	 */
191func tsp_system_off_entry
192	bl	tsp_system_off_main
193	restore_args_call_smc
194
195	/*---------------------------------------------
196	 * This entrypoint is used by the TSPD when the
197	 * system is about to be reset (through a
198	 * SYSTEM_RESET psci call) to ask the TSP to
199	 * perform any necessary bookkeeping.
200	 * ---------------------------------------------
201	 */
202func tsp_system_reset_entry
203	bl	tsp_system_reset_main
204	restore_args_call_smc
205
206	/*---------------------------------------------
207	 * This entrypoint is used by the TSPD when this
208	 * cpu is turned on using a CPU_ON psci call to
209	 * ask the TSP to initialise itself i.e. setup
210	 * the mmu, stacks etc. Minimal architectural
211	 * state will be initialised by the TSPD when
212	 * this function is entered i.e. Caches and MMU
213	 * will be turned off, the execution state
214	 * will be aarch64 and exceptions masked.
215	 * ---------------------------------------------
216	 */
217func tsp_cpu_on_entry
218	/* ---------------------------------------------
219	 * Set the exception vector to something sane.
220	 * ---------------------------------------------
221	 */
222	adr	x0, tsp_exceptions
223	msr	vbar_el1, x0
224	isb
225
226	/* Enable the SError interrupt */
227	msr	daifclr, #DAIF_ABT_BIT
228
229	/* ---------------------------------------------
230	 * Enable the instruction cache, stack pointer
231	 * and data access alignment checks
232	 * ---------------------------------------------
233	 */
234	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
235	mrs	x0, sctlr_el1
236	orr	x0, x0, x1
237	msr	sctlr_el1, x0
238	isb
239
240	/* --------------------------------------------
241	 * Give ourselves a stack whose memory will be
242	 * marked as Normal-IS-WBWA when the MMU is
243	 * enabled.
244	 * --------------------------------------------
245	 */
246	mrs	x0, mpidr_el1
247	bl	platform_set_stack
248
249	/* --------------------------------------------
250	 * Enable the MMU with the DCache disabled. It
251	 * is safe to use stacks allocated in normal
252	 * memory as a result. All memory accesses are
253	 * marked nGnRnE when the MMU is disabled. So
254	 * all the stack writes will make it to memory.
255	 * All memory accesses are marked Non-cacheable
256	 * when the MMU is enabled but D$ is disabled.
257	 * So used stack memory is guaranteed to be
258	 * visible immediately after the MMU is enabled
259	 * Enabling the DCache at the same time as the
260	 * MMU can lead to speculatively fetched and
261	 * possibly stale stack memory being read from
262	 * other caches. This can lead to coherency
263	 * issues.
264	 * --------------------------------------------
265	 */
266	mov	x0, #DISABLE_DCACHE
267	bl	bl32_plat_enable_mmu
268
269	/* ---------------------------------------------
270	 * Enable the Data cache now that the MMU has
271	 * been enabled. The stack has been unwound. It
272	 * will be written first before being read. This
273	 * will invalidate any stale cache lines resi-
274	 * -dent in other caches. We assume that
275	 * interconnect coherency has been enabled for
276	 * this cluster by EL3 firmware.
277	 * ---------------------------------------------
278	 */
279	mrs	x0, sctlr_el1
280	orr	x0, x0, #SCTLR_C_BIT
281	msr	sctlr_el1, x0
282	isb
283
284	/* ---------------------------------------------
285	 * Enter C runtime to perform any remaining
286	 * book keeping
287	 * ---------------------------------------------
288	 */
289	bl	tsp_cpu_on_main
290	restore_args_call_smc
291
292	/* Should never reach here */
293tsp_cpu_on_entry_panic:
294	b	tsp_cpu_on_entry_panic
295
296	/*---------------------------------------------
297	 * This entrypoint is used by the TSPD when this
298	 * cpu is to be suspended through a CPU_SUSPEND
299	 * psci call to ask the TSP to perform any
300	 * bookeeping necessary. In the current
301	 * implementation, the TSPD saves and restores
302	 * the EL1 state.
303	 * ---------------------------------------------
304	 */
305func tsp_cpu_suspend_entry
306	bl	tsp_cpu_suspend_main
307	restore_args_call_smc
308
309	/*---------------------------------------------
310	 * This entrypoint is used by the TSPD to pass
311	 * control for handling a pending S-EL1 FIQ.
312	 * 'x0' contains a magic number which indicates
313	 * this. TSPD expects control to be handed back
314	 * at the end of FIQ processing. This is done
315	 * through an SMC. The handover agreement is:
316	 *
317	 * 1. PSTATE.DAIF are set upon entry. 'x1' has
318	 *    the ELR_EL3 from the non-secure state.
319	 * 2. TSP has to preserve the callee saved
320	 *    general purpose registers, SP_EL1/EL0 and
321	 *    LR.
322	 * 3. TSP has to preserve the system and vfp
323	 *    registers (if applicable).
324	 * 4. TSP can use 'x0-x18' to enable its C
325	 *    runtime.
326	 * 5. TSP returns to TSPD using an SMC with
327	 *    'x0' = TSP_HANDLED_S_EL1_FIQ
328	 * ---------------------------------------------
329	 */
330func	tsp_fiq_entry
331#if DEBUG
332	mov	x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff)
333	movk	x2, #(TSP_HANDLE_FIQ_AND_RETURN &  0xffff)
334	cmp	x0, x2
335	b.ne	tsp_fiq_entry_panic
336#endif
337	/*---------------------------------------------
338	 * Save any previous context needed to perform
339	 * an exception return from S-EL1 e.g. context
340	 * from a previous IRQ. Update statistics and
341	 * handle the FIQ before returning to the TSPD.
342	 * IRQ/FIQs are not enabled since that will
343	 * complicate the implementation. Execution
344	 * will be transferred back to the normal world
345	 * in any case. A non-zero return value from the
346	 * fiq handler is an error.
347	 * ---------------------------------------------
348	 */
349	save_eret_context x2 x3
350	bl	tsp_update_sync_fiq_stats
351	bl	tsp_fiq_handler
352	cbnz	x0, tsp_fiq_entry_panic
353	restore_eret_context x2 x3
354	mov	x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff)
355	movk	x0, #(TSP_HANDLED_S_EL1_FIQ &  0xffff)
356	smc	#0
357
358tsp_fiq_entry_panic:
359	b	tsp_fiq_entry_panic
360
361	/*---------------------------------------------
362	 * This entrypoint is used by the TSPD when this
363	 * cpu resumes execution after an earlier
364	 * CPU_SUSPEND psci call to ask the TSP to
365	 * restore its saved context. In the current
366	 * implementation, the TSPD saves and restores
367	 * EL1 state so nothing is done here apart from
368	 * acknowledging the request.
369	 * ---------------------------------------------
370	 */
371func tsp_cpu_resume_entry
372	bl	tsp_cpu_resume_main
373	restore_args_call_smc
374tsp_cpu_resume_panic:
375	b	tsp_cpu_resume_panic
376
377	/*---------------------------------------------
378	 * This entrypoint is used by the TSPD to ask
379	 * the TSP to service a fast smc request.
380	 * ---------------------------------------------
381	 */
382func tsp_fast_smc_entry
383	bl	tsp_smc_handler
384	restore_args_call_smc
385tsp_fast_smc_entry_panic:
386	b	tsp_fast_smc_entry_panic
387
388	/*---------------------------------------------
389	 * This entrypoint is used by the TSPD to ask
390	 * the TSP to service a std smc request.
391	 * We will enable preemption during execution
392	 * of tsp_smc_handler.
393	 * ---------------------------------------------
394	 */
395func tsp_std_smc_entry
396	msr	daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
397	bl	tsp_smc_handler
398	msr	daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT
399	restore_args_call_smc
400tsp_std_smc_entry_panic:
401	b	tsp_std_smc_entry_panic
402