1/*
2 * boot.S - simple register setup code for junping to a second stage bootloader
3 *
4 * Copyright (C) 2011-2013 ARM Limited.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *        notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of ARM nor the names of its contributors may be
18 *       used to endorse or promote products derived from this software
19 *       without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
22 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
27 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
28 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
29 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * This license can also be found in the LICENSE.TXT file.
34 */
35
36	.text
37
38	.globl	_start
39
40.set LED_ADDR, 0x1c010008
41
42_start:
43	/*
44	 * EL3 initialisation
45	 */
46
47	// Set LED to show progress.
48	ldr	x1, =LED_ADDR
49	mov	w0, #0x1
50	str	w0, [x1]
51        dsb	sy
52
53#if defined START_EL2
54
55	mrs	x0, CurrentEL
56	cmp	x0, #0xc			// EL3?
57	b.ne	start_ns			// skip EL3 initialisation
58
59	mov	x0, #0x30			// RES1
60	orr	x0, x0, #(1 << 0)		// Non-secure bit
61	orr	x0, x0, #(1 << 8)		// HVC enable
62	orr	x0, x0, #(1 << 10)		// 64-bit EL2
63	msr	scr_el3, x0
64
65	msr	cptr_el3, xzr			// Disable copro. traps to EL3
66
67	ldr	x0, =CNTFRQ
68	msr	cntfrq_el0, x0
69
70	/*
71	 * Check for the primary CPU to avoid a race on the distributor
72	 * registers.
73	 */
74	mrs	x0, mpidr_el1
75	tst	x0, #15
76	b.ne	1f				// secondary CPU
77
78	ldr	x1, =GIC_DIST_BASE		// GICD_CTLR
79	mov	w0, #3				// EnableGrp0 | EnableGrp1
80	str	w0, [x1]
81
821:	ldr	x1, =GIC_DIST_BASE + 0x80	// GICD_IGROUPR
83	mov	w0, #~0				// Grp1 interrupts
84	str	w0, [x1], #4
85	b.ne	2f				// Only local interrupts for secondary CPUs
86	str	w0, [x1], #4
87	str	w0, [x1], #4
88
892:	ldr	x1, =GIC_CPU_BASE		// GICC_CTLR
90	ldr	w0, [x1]
91	orr	w0, w0, #3			// EnableGrp0 | EnableGrp1
92	str	w0, [x1]
93
94	mov	w0, #1 << 7			// allow NS access to GICC_PMR
95	str	w0, [x1, #4]			// GICC_PMR
96
97	msr	sctlr_el2, xzr
98
99#if defined START_EL1
100
101	/* Now setup our EL1. Controlled by EL2 config on Model */
102	mrs	x0, hcr_el2			// Read EL2 Hypervisor configuration Register
103	orr	x0, x0, #(1 << 31)		// Set EL1 to be 64bit
104
105	// Send all interrupts to their respective Exception levels for EL2
106	bic	x0, x0, #(1 << 3)		// Disable virtual FIQ
107	bic	x0, x0, #(1 << 4)		// Disable virtual IRQ
108	bic	x0, x0, #(1 << 5)		// Disable virtual SError and Abort
109	msr	hcr_el2, x0			// Write back our settings
110
111	/*
112	 * Enable architected timer access
113	 */
114	mrs	x0, cnthctl_el2
115	orr	x0, x0, #3			// Enable EL1 access to timers
116	msr	cnthctl_el2, x0
117
118	mrs	x0, cntkctl_el1
119	orr	x0, x0, #3			// EL0 access to counters
120	msr	cntkctl_el1, x0
121
122	/* Set ID regs */
123	mrs	x0, midr_el1
124	mrs	x1, mpidr_el1
125	msr	vpidr_el2, x0
126	msr	vmpidr_el2, x1
127
128	/* Coprocessor traps. */
129	mov	x0, #0x33ff
130	msr	cptr_el2, x0			// Disable copro. traps to EL2
131
132	msr	hstr_el2, xzr			// Disable CP15 traps to EL2
133
134#endif // START_EL1
135
136        /* Configure UART. Primary CPU only */
137	mrs     x4, mpidr_el1
138	tst     x4, #15
139	b.ne    1f
140
141	/*
142	 * UART initialisation (38400 8N1)
143	 */
144	ldr     x4, =UART_BASE                  // UART base
145	mov     w5, #0x10                       // ibrd
146	str     w5, [x4, #0x24]
147	mov     w5, #0xc300
148	orr     w5, w5, #0x0001                 // cr
149	str     w5, [x4, #0x30]
150
151	/*
152	 * Prepare the switch to the EL2_SP2 mode from EL3
153	 */
1541:	ldr	x0, =start_ns			// Return after mode switch
155#if defined START_EL1
156	mov	x1, #0x3c5			// EL1_SP1 | D | A | I | F
157#else
158	mov	x1, #0x3c9			// EL2_SP2 | D | A | I | F
159#endif
160
161	msr	elr_el3, x0
162	msr	spsr_el3, x1
163	eret
164
165#endif // START_EL2
166
167
168start_ns:
169
170/*
171 * We do not have NOR flash on the Foundation model. So run UEFI from RAM.
172 * On the full model we use the NOR FLASH to store UEFI, so start there.
173 */
174#if defined FOUNDATION_MODEL
175	mov	x0, #0xa0000000
176#else
177	mov	x0, #0x0
178#endif
179	br	x0
180
181	.ltorg
182
183	.org	0x200
184