1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "brw_context.h"
34 #include "brw_wm.h"
35
36
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
39 * tests.
40 */
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
43
44 static void spill_value(struct brw_wm_compile *c,
45 struct brw_wm_value *value);
46
prealloc_reg(struct brw_wm_compile * c,struct brw_wm_value * value,GLuint reg)47 static void prealloc_reg(struct brw_wm_compile *c,
48 struct brw_wm_value *value,
49 GLuint reg)
50 {
51 if (value->lastuse) {
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
54 */
55 c->pass2_grf[reg].value = value;
56 c->pass2_grf[reg].nextuse = 0;
57
58 value->resident = &c->pass2_grf[reg];
59 value->hw_reg = brw_vec8_grf(reg*2, 0);
60
61 if (TEST_PAYLOAD_SPILLS)
62 spill_value(c, value);
63 }
64 }
65
66
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
69 */
init_registers(struct brw_wm_compile * c)70 static void init_registers( struct brw_wm_compile *c )
71 {
72 struct brw_context *brw = c->func.brw;
73 struct intel_context *intel = &brw->intel;
74 GLuint nr_interp_regs = 0;
75 GLuint i = 0;
76 GLuint j;
77
78 for (j = 0; j < c->grf_limit; j++)
79 c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
80
81 for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++)
82 prealloc_reg(c, &c->payload.depth[j], i++);
83
84 for (j = 0; j < c->nr_creg; j++)
85 prealloc_reg(c, &c->creg[j], i++);
86
87 if (intel->gen >= 6) {
88 for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) {
89 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(j)) {
90 nr_interp_regs++;
91 prealloc_reg(c, &c->payload.input_interp[j], i++);
92 }
93 }
94 } else {
95 for (j = 0; j < VERT_RESULT_MAX; j++) {
96 /* Point size is packed into the header, not as a general attribute */
97 if (j == VERT_RESULT_PSIZ)
98 continue;
99
100 if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
101 int fp_index = _mesa_vert_result_to_frag_attrib(j);
102
103 nr_interp_regs++;
104
105 /* The back color slot is skipped when the front color is
106 * also written to. In addition, some slots can be
107 * written in the vertex shader and not read in the
108 * fragment shader. So the register number must always be
109 * incremented, mapped or not.
110 */
111 if (fp_index >= 0)
112 prealloc_reg(c, &c->payload.input_interp[fp_index], i);
113 i++;
114 }
115 }
116 assert(nr_interp_regs >= 1);
117 }
118
119
120 c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2);
121 c->prog_data.urb_read_length = nr_interp_regs * 2;
122 c->prog_data.curb_read_length = c->nr_creg * 2;
123
124 c->max_wm_grf = i * 2;
125 }
126
127
128 /* Update the nextuse value for each register in our file.
129 */
update_register_usage(struct brw_wm_compile * c,GLuint thisinsn)130 static void update_register_usage(struct brw_wm_compile *c,
131 GLuint thisinsn)
132 {
133 GLuint i;
134
135 for (i = 1; i < c->grf_limit; i++) {
136 struct brw_wm_grf *grf = &c->pass2_grf[i];
137
138 /* Only search those which can change:
139 */
140 if (grf->nextuse < thisinsn) {
141 const struct brw_wm_ref *ref = grf->value->lastuse;
142
143 /* Has last use of value been passed?
144 */
145 if (ref->insn < thisinsn) {
146 grf->value->resident = 0;
147 grf->value = 0;
148 grf->nextuse = BRW_WM_MAX_INSN;
149 }
150 else {
151 /* Else loop through chain to update:
152 */
153 while (ref->prevuse && ref->prevuse->insn >= thisinsn)
154 ref = ref->prevuse;
155
156 grf->nextuse = ref->insn;
157 }
158 }
159 }
160 }
161
162
spill_value(struct brw_wm_compile * c,struct brw_wm_value * value)163 static void spill_value(struct brw_wm_compile *c,
164 struct brw_wm_value *value)
165 {
166 /* Allocate a spill slot. Note that allocations start from 0x40 -
167 * the first slot is reserved to mean "undef" in brw_wm_emit.c
168 */
169 if (!value->spill_slot) {
170 c->last_scratch += 0x40;
171 value->spill_slot = c->last_scratch;
172 }
173
174 /* The spill will be done in brw_wm_emit.c immediately after the
175 * value is calculated, so we can just take this reg without any
176 * further work.
177 */
178 value->resident->value = NULL;
179 value->resident->nextuse = BRW_WM_MAX_INSN;
180 value->resident = NULL;
181 }
182
183
184
185 /* Search for contiguous region with the most distant nearest
186 * member. Free regs count as very distant.
187 *
188 * TODO: implement spill-to-reg so that we can rearrange discontigous
189 * free regs and then spill the oldest non-free regs in sequence.
190 * This would mean inserting instructions in this pass.
191 */
search_contiguous_regs(struct brw_wm_compile * c,GLuint nr,GLuint thisinsn)192 static GLuint search_contiguous_regs(struct brw_wm_compile *c,
193 GLuint nr,
194 GLuint thisinsn)
195 {
196 struct brw_wm_grf *grf = c->pass2_grf;
197 GLuint furthest = 0;
198 GLuint reg = 0;
199 GLuint i, j;
200
201 /* Start search at 1: r0 is special and can't be used or spilled.
202 */
203 for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) {
204 GLuint group_nextuse = BRW_WM_MAX_INSN;
205
206 for (j = 0; j < nr; j++) {
207 if (grf[i+j].nextuse < group_nextuse)
208 group_nextuse = grf[i+j].nextuse;
209 }
210
211 if (group_nextuse > furthest) {
212 furthest = group_nextuse;
213 reg = i;
214 }
215 }
216
217 assert(furthest != thisinsn);
218
219 /* Any non-empty regs will need to be spilled:
220 */
221 for (j = 0; j < nr; j++)
222 if (grf[reg+j].value)
223 spill_value(c, grf[reg+j].value);
224
225 return reg;
226 }
227
228
alloc_contiguous_dest(struct brw_wm_compile * c,struct brw_wm_value * dst[],GLuint nr,GLuint thisinsn)229 static void alloc_contiguous_dest(struct brw_wm_compile *c,
230 struct brw_wm_value *dst[],
231 GLuint nr,
232 GLuint thisinsn)
233 {
234 GLuint reg = search_contiguous_regs(c, nr, thisinsn);
235 GLuint i;
236
237 for (i = 0; i < nr; i++) {
238 if (!dst[i]) {
239 /* Need to grab a dummy value in TEX case. Don't introduce
240 * it into the tracking scheme.
241 */
242 dst[i] = &c->vreg[c->nr_vreg++];
243 }
244 else {
245 assert(!dst[i]->resident);
246 assert(c->pass2_grf[reg+i].nextuse != thisinsn);
247
248 c->pass2_grf[reg+i].value = dst[i];
249 c->pass2_grf[reg+i].nextuse = thisinsn;
250
251 dst[i]->resident = &c->pass2_grf[reg+i];
252 }
253
254 dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0);
255 }
256
257 if ((reg+nr)*2 > c->max_wm_grf)
258 c->max_wm_grf = (reg+nr) * 2;
259 }
260
261
load_args(struct brw_wm_compile * c,struct brw_wm_instruction * inst)262 static void load_args(struct brw_wm_compile *c,
263 struct brw_wm_instruction *inst)
264 {
265 GLuint thisinsn = inst - c->instruction;
266 GLuint i,j;
267
268 for (i = 0; i < 3; i++) {
269 for (j = 0; j < 4; j++) {
270 struct brw_wm_ref *ref = inst->src[i][j];
271
272 if (ref) {
273 if (!ref->value->resident) {
274 /* Need to bring the value in from scratch space. The code for
275 * this will be done in brw_wm_emit.c, here we just do the
276 * register allocation and mark the ref as requiring a fill.
277 */
278 GLuint reg = search_contiguous_regs(c, 1, thisinsn);
279
280 c->pass2_grf[reg].value = ref->value;
281 c->pass2_grf[reg].nextuse = thisinsn;
282
283 ref->value->resident = &c->pass2_grf[reg];
284
285 /* Note that a fill is required:
286 */
287 ref->unspill_reg = reg*2;
288 }
289
290 /* Adjust the hw_reg to point at the value's current location:
291 */
292 assert(ref->value == ref->value->resident->value);
293 ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2;
294 }
295 }
296 }
297 }
298
299
300
301 /* Step 3: Work forwards once again. Perform register allocations,
302 * taking into account instructions like TEX which require contiguous
303 * result registers. Where necessary spill registers to scratch space
304 * and reload later.
305 */
brw_wm_pass2(struct brw_wm_compile * c)306 void brw_wm_pass2( struct brw_wm_compile *c )
307 {
308 GLuint insn;
309 GLuint i;
310
311 init_registers(c);
312
313 for (insn = 0; insn < c->nr_insns; insn++) {
314 struct brw_wm_instruction *inst = &c->instruction[insn];
315
316 /* Update registers' nextuse values:
317 */
318 update_register_usage(c, insn);
319
320 /* May need to unspill some args.
321 */
322 load_args(c, inst);
323
324 /* Allocate registers to hold results:
325 */
326 switch (inst->opcode) {
327 case OPCODE_TEX:
328 case OPCODE_TXB:
329 case OPCODE_TXP:
330 alloc_contiguous_dest(c, inst->dst, 4, insn);
331 break;
332
333 default:
334 for (i = 0; i < 4; i++) {
335 if (inst->writemask & (1<<i)) {
336 assert(inst->dst[i]);
337 alloc_contiguous_dest(c, &inst->dst[i], 1, insn);
338 }
339 }
340 break;
341 }
342
343 if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) {
344 for (i = 0; i < 4; i++)
345 if (inst->dst[i])
346 spill_value(c, inst->dst[i]);
347 }
348 }
349
350 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
351 brw_wm_print_program(c, "pass2");
352 }
353
354 c->state = PASS2_DONE;
355
356 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
357 brw_wm_print_program(c, "pass2/done");
358 }
359 }
360