1ARM CPU Specific Build Macros
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4Contents
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71.  [Introduction](#1--introduction)
82.  [CPU Errata Workarounds](#2--cpu-errata-workarounds)
93.  [CPU Specific optimizations](#3--cpu-specific-optimizations)
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121.  Introduction
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14
15This document describes the various build options present in the CPU specific
16operations framework to enable errata workarounds and to enable optimizations
17for a specific CPU on a platform.
18
192.  CPU Errata Workarounds
20--------------------------
21
22ARM Trusted Firmware exports a series of build flags which control the
23errata workarounds that are applied to each CPU by the reset handler. The
24errata details can be found in the CPU specific errata documents published
25by ARM. The errata workarounds are implemented for a particular revision
26or a set of processor revisions. This is checked by reset handler at runtime.
27Each errata workaround is identified by its `ID` as specified in the processor's
28errata notice document. The format of the define used to enable/disable the
29errata is `ERRATA_<Processor name>_<ID>` where the `Processor name`
30is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU.
31
32All workarounds are disabled by default. The platform is reponsible for
33enabling these workarounds according to its requirement by defining the
34errata workaround build flags in the platform specific makefile. In case
35these workarounds are enabled for the wrong CPU revision then the errata
36workaround is not applied. In the DEBUG build, this is indicated by
37printing a warning to the crash console.
38
39In the current implementation, a platform which has more than 1 variant
40with different revisions of a processor has no runtime mechanism available
41for it to specify which errata workarounds should be enabled or not.
42
43The value of the build flags are 0 by default, that is, disabled. Any other
44value will enable it.
45
46For Cortex-A57, following errata build flags are defined :
47
48*   `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57
49     CPU. This needs to be enabled only for revision r0p0 of the CPU.
50
51*   `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
52     CPU. This needs to be enabled only for revision r0p0 of the CPU.
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543.  CPU Specific optimizations
55------------------------------
56
57This section describes some of the optimizations allowed by the CPU micro
58architecture that can be enabled by the platform as desired.
59
60*    `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the
61     Cortex-A57 cluster power down sequence by not flushing the Level 1 data
62     cache. The L1 data cache and the L2 unified cache are inclusive. A flush
63     of the L2 by set/way flushes any dirty lines from the L1 as well. This
64     is a known safe deviation from the Cortex-A57 TRM defined power down
65     sequence. Each Cortex-A57 based platform must make its own decision on
66     whether to use the optimization.
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70_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._
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