1/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32
33#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
34				(MIDR_PN_MASK << MIDR_PN_SHIFT)
35
36	/*
37	 * Define the offsets to the fields in cpu_ops structure.
38	 */
39	.struct 0
40CPU_MIDR: /* cpu_ops midr */
41	.space  8
42/* Reset fn is needed in BL at reset vector */
43#if IMAGE_BL1 || IMAGE_BL31
44CPU_RESET_FUNC: /* cpu_ops reset_func */
45	.space  8
46#endif
47#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
48CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
49	.space  8
50CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
51	.space  8
52#endif
53#if (IMAGE_BL31 && CRASH_REPORTING)
54CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
55	.space  8
56#endif
57CPU_OPS_SIZE = .
58
59	/*
60	 * Convenience macro to declare cpu_ops structure.
61	 * Make sure the structure fields are as per the offsets
62	 * defined above.
63	 */
64	.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
65	.section cpu_ops, "a"; .align 3
66	.type cpu_ops_\_name, %object
67	.quad \_midr
68#if IMAGE_BL1 || IMAGE_BL31
69	.if \_noresetfunc
70	.quad 0
71	.else
72	.quad \_name\()_reset_func
73	.endif
74#endif
75#if IMAGE_BL31
76	.quad \_name\()_core_pwr_dwn
77	.quad \_name\()_cluster_pwr_dwn
78#endif
79#if (IMAGE_BL31 && CRASH_REPORTING)
80	.quad \_name\()_cpu_reg_dump
81#endif
82	.endm
83