1VIXL Change Log
2===============
3
4* 1.13
5    + Improve code formatting and add tests using clang-format.
6    + Fix bugs in disassembly of unallocated instruction encodings.
7    + Fix some execution trace bugs, and add tests.
8    + Other small bug fixes and improvements.
9
10* 1.12
11    + Bug fixes for toolchain compatibility.
12
13* 1.11
14    + Fix bug in simulation of add with carry.
15    + Fix use-after-free bug in Literal handling.
16    + Build system updates for Android.
17    + Add option to run test.py under Valgrind.
18    + Other small bug fixes and improvements.
19
20* 1.10
21    + Improved support for externally managed literals.
22    + Reworked build and test infrastructure.
23    + Other small bug fixes and improvements.
24
25* 1.9
26    + Improved compatibility with Android build system.
27    + Improved compatibility with Clang toolchain.
28    + Added support for `umulh` instruction.
29    + Added support for `fcmpe` and `fccmpe` instructions.
30    + Other small bug fixes and improvements.
31
32* 1.8
33    + Complete NEON instruction set support.
34    + Support long branches using veneers.
35    + Improved handling of literal pools.
36    + Support some `ic` and `dc` cache op instructions.
37    + Support CRC32 instructions.
38    + Support half-precision floating point instructions.
39    + MacroAssembler support for `bfm`, `ubfm` and `sbfm`.
40    + Other small bug fixes and improvements.
41
42* 1.7
43    + Added support for `prfm` prefetch instructions.
44    + Added support for all `frint` instruction variants.
45    + Add support for disassembling as an offset from a given address.
46    + Fixed the disassembly of `movz` and `movn`.
47    + Provide static helpers for immediate generation.
48    + Provide helpers to create CPURegList from list unions or intersections.
49    + Improved register value tracing.
50    + Multithreading test fixes.
51    + Other small bug fixes and build system improvements.
52
53* 1.6
54    + Make literal pool management the responsibility of the macro assembler.
55    + Move code buffer management out of the Assembler.
56    + Support `ldrsw` for literals.
57    + Support binding a label to a specific offset.
58    + Add macro assembler support for load/store pair with arbitrary offset.
59    + Support Peek and Poke for CPURegLists.
60    + Fix disassembly of branch targets.
61    + Fix Decoder visitor insertion order.
62    + Separate Decoder visitors into const and non-const variants.
63    + Fix simulator for branches to tagged addresses.
64    + Add a VIM YouCompleteMe configuration file.
65    + Other small bug fixes and build system improvements.
66
67* 1.5
68    + Tagged pointer support.
69    + Implement support for exclusive access instructions.
70    + Implement support for `adrp` instruction.
71    + Faster code for logical immediate identification.
72    + Generate better code for immediates passed to shift-capable instructions.
73    + Allow explicit use of unscaled-offset loads and stores.
74    + Build and test infrastructure improvements.
75    + Corrected computation of cache line size.
76    + Fix simulation of `extr` instruction.
77    + Fixed a bug when moving kWMinInt to a register.
78    + Other small bug fixes.
79
80* 1.4
81    + Added support for `frintm`.
82    + Fixed simulation of `frintn` and `frinta` for corner cases.
83    + Added more tests for floating point instruction simulation.
84    + Modified `CalleeSave()` and `CalleeRestore()` to push general purpose
85      registers before floating point registers on the stack.
86    + Fixed Printf for mixed argument types, and use on real hardware.
87    + Improved compatibility with some 32-bit compilers.
88
89* 1.3
90    + Address inaccuracies in the simulated floating point instructions.
91    + Implement Default-NaN floating point mode.
92    + Introduce `UseScratchRegisterScope` for controlling the use of temporary
93      registers.
94    + Enable building VIXL on 32-bit hosts.
95    + Other small bug fixes and improvements.
96
97* 1.2
98    + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,
99      `frinta`, `fcvtau` and `fcvtas`.
100    + Added support for assembling and disassembling `isb`, `dsb` and `dmb`.
101    + Added support for automatic inversion of compare instructions when using
102      negative immediates.
103    + Added support for using `movn` when generating immediates.
104    + Added explicit flag-setting 'S' instructions, and removed
105      `SetFlags` and `LeaveFlags` arguments.
106    + Added support for `Movk` in macro assembler.
107    + Added support for W register parameters to `Tbz` and `Tbnz`.
108    + Added support for using immediate operands with `Csel`.
109    + Added new debugger syntax for memory inspection.
110    + Fixed `smull`, `fmsub` and `sdiv` simulation.
111    + Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`.
112    + Prevented code generation for certain side-effect free operations,
113      such as `add r, r, #0`, in the macro assembler.
114    + Other small bug fixes.
115
116* 1.1
117    + Improved robustness of instruction decoder and disassembler.
118    + Added support for double-to-float conversions using `fcvt`.
119    + Added support for more fixed-point to floating-point conversions (`ucvtf`
120      and `scvtf`).
121    + Added instruction statistics collection class `instrument-a64.cc`.
122
123* 1.0
124    + Initial release.
125