1 // This file is part of Eigen, a lightweight C++ template library 2 // for linear algebra. 3 // 4 // Copyright (C) 2008-2009 Gael Guennebaud <gael.guennebaud@inria.fr> 5 // Copyright (C) 2010 Konstantinos Margaritis <markos@freevec.org> 6 // Heavily based on Gael's SSE version. 7 // 8 // This Source Code Form is subject to the terms of the Mozilla 9 // Public License v. 2.0. If a copy of the MPL was not distributed 10 // with this file, You can obtain one at http://mozilla.org/MPL/2.0/. 11 12 #ifndef EIGEN_PACKET_MATH_NEON_H 13 #define EIGEN_PACKET_MATH_NEON_H 14 15 namespace Eigen { 16 17 namespace internal { 18 19 #ifndef EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 20 #define EIGEN_CACHEFRIENDLY_PRODUCT_THRESHOLD 8 21 #endif 22 23 #ifndef EIGEN_HAS_SINGLE_INSTRUCTION_MADD 24 #define EIGEN_HAS_SINGLE_INSTRUCTION_MADD 25 #endif 26 27 #ifndef EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD 28 #define EIGEN_HAS_SINGLE_INSTRUCTION_CJMADD 29 #endif 30 31 #ifndef EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 32 #if EIGEN_ARCH_ARM64 33 #define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 32 34 #else 35 #define EIGEN_ARCH_DEFAULT_NUMBER_OF_REGISTERS 16 36 #endif 37 #endif 38 39 typedef float32x2_t Packet2f; 40 typedef float32x4_t Packet4f; 41 typedef int32x4_t Packet4i; 42 typedef int32x2_t Packet2i; 43 typedef uint32x4_t Packet4ui; 44 45 #define _EIGEN_DECLARE_CONST_Packet4f(NAME,X) \ 46 const Packet4f p4f_##NAME = pset1<Packet4f>(X) 47 48 #define _EIGEN_DECLARE_CONST_Packet4f_FROM_INT(NAME,X) \ 49 const Packet4f p4f_##NAME = vreinterpretq_f32_u32(pset1<int32_t>(X)) 50 51 #define _EIGEN_DECLARE_CONST_Packet4i(NAME,X) \ 52 const Packet4i p4i_##NAME = pset1<Packet4i>(X) 53 54 // arm64 does have the pld instruction. If available, let's trust the __builtin_prefetch built-in function 55 // which available on LLVM and GCC (at least) 56 #if EIGEN_HAS_BUILTIN(__builtin_prefetch) || EIGEN_COMP_GNUC 57 #define EIGEN_ARM_PREFETCH(ADDR) __builtin_prefetch(ADDR); 58 #elif defined __pld 59 #define EIGEN_ARM_PREFETCH(ADDR) __pld(ADDR) 60 #elif !EIGEN_ARCH_ARM64 61 #define EIGEN_ARM_PREFETCH(ADDR) __asm__ __volatile__ ( " pld [%[addr]]\n" :: [addr] "r" (ADDR) : "cc" ); 62 #else 63 // by default no explicit prefetching 64 #define EIGEN_ARM_PREFETCH(ADDR) 65 #endif 66 67 template<> struct packet_traits<float> : default_packet_traits 68 { 69 typedef Packet4f type; 70 typedef Packet4f half; // Packet2f intrinsics not implemented yet 71 enum { 72 Vectorizable = 1, 73 AlignedOnScalar = 1, 74 size = 4, 75 HasHalfPacket=0, // Packet2f intrinsics not implemented yet 76 77 HasDiv = 1, 78 // FIXME check the Has* 79 HasSin = 0, 80 HasCos = 0, 81 HasLog = 0, 82 HasExp = 1, 83 HasSqrt = 0 84 }; 85 }; 86 template<> struct packet_traits<int32_t> : default_packet_traits 87 { 88 typedef Packet4i type; 89 typedef Packet4i half; // Packet2i intrinsics not implemented yet 90 enum { 91 Vectorizable = 1, 92 AlignedOnScalar = 1, 93 size=4, 94 HasHalfPacket=0 // Packet2i intrinsics not implemented yet 95 // FIXME check the Has* 96 }; 97 }; 98 99 #if EIGEN_GNUC_AT_MOST(4,4) && !EIGEN_COMP_LLVM 100 // workaround gcc 4.2, 4.3 and 4.4 compilatin issue 101 EIGEN_STRONG_INLINE float32x4_t vld1q_f32(const float* x) { return ::vld1q_f32((const float32_t*)x); } 102 EIGEN_STRONG_INLINE float32x2_t vld1_f32 (const float* x) { return ::vld1_f32 ((const float32_t*)x); } 103 EIGEN_STRONG_INLINE float32x2_t vld1_dup_f32 (const float* x) { return ::vld1_dup_f32 ((const float32_t*)x); } 104 EIGEN_STRONG_INLINE void vst1q_f32(float* to, float32x4_t from) { ::vst1q_f32((float32_t*)to,from); } 105 EIGEN_STRONG_INLINE void vst1_f32 (float* to, float32x2_t from) { ::vst1_f32 ((float32_t*)to,from); } 106 #endif 107 108 template<> struct unpacket_traits<Packet4f> { typedef float type; enum {size=4, alignment=Aligned16}; typedef Packet4f half; }; 109 template<> struct unpacket_traits<Packet4i> { typedef int32_t type; enum {size=4, alignment=Aligned16}; typedef Packet4i half; }; 110 111 template<> EIGEN_STRONG_INLINE Packet4f pset1<Packet4f>(const float& from) { return vdupq_n_f32(from); } 112 template<> EIGEN_STRONG_INLINE Packet4i pset1<Packet4i>(const int32_t& from) { return vdupq_n_s32(from); } 113 114 template<> EIGEN_STRONG_INLINE Packet4f plset<Packet4f>(const float& a) 115 { 116 const float32_t f[] = {0, 1, 2, 3}; 117 Packet4f countdown = vld1q_f32(f); 118 return vaddq_f32(pset1<Packet4f>(a), countdown); 119 } 120 template<> EIGEN_STRONG_INLINE Packet4i plset<Packet4i>(const int32_t& a) 121 { 122 const int32_t i[] = {0, 1, 2, 3}; 123 Packet4i countdown = vld1q_s32(i); 124 return vaddq_s32(pset1<Packet4i>(a), countdown); 125 } 126 127 template<> EIGEN_STRONG_INLINE Packet4f padd<Packet4f>(const Packet4f& a, const Packet4f& b) { return vaddq_f32(a,b); } 128 template<> EIGEN_STRONG_INLINE Packet4i padd<Packet4i>(const Packet4i& a, const Packet4i& b) { return vaddq_s32(a,b); } 129 130 template<> EIGEN_STRONG_INLINE Packet4f psub<Packet4f>(const Packet4f& a, const Packet4f& b) { return vsubq_f32(a,b); } 131 template<> EIGEN_STRONG_INLINE Packet4i psub<Packet4i>(const Packet4i& a, const Packet4i& b) { return vsubq_s32(a,b); } 132 133 template<> EIGEN_STRONG_INLINE Packet4f pnegate(const Packet4f& a) { return vnegq_f32(a); } 134 template<> EIGEN_STRONG_INLINE Packet4i pnegate(const Packet4i& a) { return vnegq_s32(a); } 135 136 template<> EIGEN_STRONG_INLINE Packet4f pconj(const Packet4f& a) { return a; } 137 template<> EIGEN_STRONG_INLINE Packet4i pconj(const Packet4i& a) { return a; } 138 139 template<> EIGEN_STRONG_INLINE Packet4f pmul<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmulq_f32(a,b); } 140 template<> EIGEN_STRONG_INLINE Packet4i pmul<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmulq_s32(a,b); } 141 142 template<> EIGEN_STRONG_INLINE Packet4f pdiv<Packet4f>(const Packet4f& a, const Packet4f& b) 143 { 144 #if EIGEN_ARCH_ARM64 145 return vdivq_f32(a,b); 146 #else 147 Packet4f inv, restep, div; 148 149 // NEON does not offer a divide instruction, we have to do a reciprocal approximation 150 // However NEON in contrast to other SIMD engines (AltiVec/SSE), offers 151 // a reciprocal estimate AND a reciprocal step -which saves a few instructions 152 // vrecpeq_f32() returns an estimate to 1/b, which we will finetune with 153 // Newton-Raphson and vrecpsq_f32() 154 inv = vrecpeq_f32(b); 155 156 // This returns a differential, by which we will have to multiply inv to get a better 157 // approximation of 1/b. 158 restep = vrecpsq_f32(b, inv); 159 inv = vmulq_f32(restep, inv); 160 161 // Finally, multiply a by 1/b and get the wanted result of the division. 162 div = vmulq_f32(a, inv); 163 164 return div; 165 #endif 166 } 167 168 template<> EIGEN_STRONG_INLINE Packet4i pdiv<Packet4i>(const Packet4i& /*a*/, const Packet4i& /*b*/) 169 { eigen_assert(false && "packet integer division are not supported by NEON"); 170 return pset1<Packet4i>(0); 171 } 172 173 // Clang/ARM wrongly advertises __ARM_FEATURE_FMA even when it's not available, 174 // then implements a slow software scalar fallback calling fmaf()! 175 // Filed LLVM bug: 176 // https://llvm.org/bugs/show_bug.cgi?id=27216 177 #if (defined __ARM_FEATURE_FMA) && !(EIGEN_COMP_CLANG && EIGEN_ARCH_ARM) 178 // See bug 936. 179 // FMA is available on VFPv4 i.e. when compiling with -mfpu=neon-vfpv4. 180 // FMA is a true fused multiply-add i.e. only 1 rounding at the end, no intermediate rounding. 181 // MLA is not fused i.e. does 2 roundings. 182 // In addition to giving better accuracy, FMA also gives better performance here on a Krait (Nexus 4): 183 // MLA: 10 GFlop/s ; FMA: 12 GFlops/s. 184 template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { return vfmaq_f32(c,a,b); } 185 #else 186 template<> EIGEN_STRONG_INLINE Packet4f pmadd(const Packet4f& a, const Packet4f& b, const Packet4f& c) { 187 #if EIGEN_COMP_CLANG && EIGEN_ARCH_ARM 188 // Clang/ARM will replace VMLA by VMUL+VADD at least for some values of -mcpu, 189 // at least -mcpu=cortex-a8 and -mcpu=cortex-a7. Since the former is the default on 190 // -march=armv7-a, that is a very common case. 191 // See e.g. this thread: 192 // http://lists.llvm.org/pipermail/llvm-dev/2013-December/068806.html 193 // Filed LLVM bug: 194 // https://llvm.org/bugs/show_bug.cgi?id=27219 195 Packet4f r = c; 196 asm volatile( 197 "vmla.f32 %q[r], %q[a], %q[b]" 198 : [r] "+w" (r) 199 : [a] "w" (a), 200 [b] "w" (b) 201 : ); 202 return r; 203 #else 204 return vmlaq_f32(c,a,b); 205 #endif 206 } 207 #endif 208 209 // No FMA instruction for int, so use MLA unconditionally. 210 template<> EIGEN_STRONG_INLINE Packet4i pmadd(const Packet4i& a, const Packet4i& b, const Packet4i& c) { return vmlaq_s32(c,a,b); } 211 212 template<> EIGEN_STRONG_INLINE Packet4f pmin<Packet4f>(const Packet4f& a, const Packet4f& b) { return vminq_f32(a,b); } 213 template<> EIGEN_STRONG_INLINE Packet4i pmin<Packet4i>(const Packet4i& a, const Packet4i& b) { return vminq_s32(a,b); } 214 215 template<> EIGEN_STRONG_INLINE Packet4f pmax<Packet4f>(const Packet4f& a, const Packet4f& b) { return vmaxq_f32(a,b); } 216 template<> EIGEN_STRONG_INLINE Packet4i pmax<Packet4i>(const Packet4i& a, const Packet4i& b) { return vmaxq_s32(a,b); } 217 218 // Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics 219 template<> EIGEN_STRONG_INLINE Packet4f pand<Packet4f>(const Packet4f& a, const Packet4f& b) 220 { 221 return vreinterpretq_f32_u32(vandq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b))); 222 } 223 template<> EIGEN_STRONG_INLINE Packet4i pand<Packet4i>(const Packet4i& a, const Packet4i& b) { return vandq_s32(a,b); } 224 225 template<> EIGEN_STRONG_INLINE Packet4f por<Packet4f>(const Packet4f& a, const Packet4f& b) 226 { 227 return vreinterpretq_f32_u32(vorrq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b))); 228 } 229 template<> EIGEN_STRONG_INLINE Packet4i por<Packet4i>(const Packet4i& a, const Packet4i& b) { return vorrq_s32(a,b); } 230 231 template<> EIGEN_STRONG_INLINE Packet4f pxor<Packet4f>(const Packet4f& a, const Packet4f& b) 232 { 233 return vreinterpretq_f32_u32(veorq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b))); 234 } 235 template<> EIGEN_STRONG_INLINE Packet4i pxor<Packet4i>(const Packet4i& a, const Packet4i& b) { return veorq_s32(a,b); } 236 237 template<> EIGEN_STRONG_INLINE Packet4f pandnot<Packet4f>(const Packet4f& a, const Packet4f& b) 238 { 239 return vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(a),vreinterpretq_u32_f32(b))); 240 } 241 template<> EIGEN_STRONG_INLINE Packet4i pandnot<Packet4i>(const Packet4i& a, const Packet4i& b) { return vbicq_s32(a,b); } 242 243 template<> EIGEN_STRONG_INLINE Packet4f pload<Packet4f>(const float* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f32(from); } 244 template<> EIGEN_STRONG_INLINE Packet4i pload<Packet4i>(const int32_t* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_s32(from); } 245 246 template<> EIGEN_STRONG_INLINE Packet4f ploadu<Packet4f>(const float* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f32(from); } 247 template<> EIGEN_STRONG_INLINE Packet4i ploadu<Packet4i>(const int32_t* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_s32(from); } 248 249 template<> EIGEN_STRONG_INLINE Packet4f ploaddup<Packet4f>(const float* from) 250 { 251 float32x2_t lo, hi; 252 lo = vld1_dup_f32(from); 253 hi = vld1_dup_f32(from+1); 254 return vcombine_f32(lo, hi); 255 } 256 template<> EIGEN_STRONG_INLINE Packet4i ploaddup<Packet4i>(const int32_t* from) 257 { 258 int32x2_t lo, hi; 259 lo = vld1_dup_s32(from); 260 hi = vld1_dup_s32(from+1); 261 return vcombine_s32(lo, hi); 262 } 263 264 template<> EIGEN_STRONG_INLINE void pstore<float> (float* to, const Packet4f& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f32(to, from); } 265 template<> EIGEN_STRONG_INLINE void pstore<int32_t>(int32_t* to, const Packet4i& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_s32(to, from); } 266 267 template<> EIGEN_STRONG_INLINE void pstoreu<float> (float* to, const Packet4f& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f32(to, from); } 268 template<> EIGEN_STRONG_INLINE void pstoreu<int32_t>(int32_t* to, const Packet4i& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_s32(to, from); } 269 270 template<> EIGEN_DEVICE_FUNC inline Packet4f pgather<float, Packet4f>(const float* from, Index stride) 271 { 272 Packet4f res = pset1<Packet4f>(0.f); 273 res = vsetq_lane_f32(from[0*stride], res, 0); 274 res = vsetq_lane_f32(from[1*stride], res, 1); 275 res = vsetq_lane_f32(from[2*stride], res, 2); 276 res = vsetq_lane_f32(from[3*stride], res, 3); 277 return res; 278 } 279 template<> EIGEN_DEVICE_FUNC inline Packet4i pgather<int32_t, Packet4i>(const int32_t* from, Index stride) 280 { 281 Packet4i res = pset1<Packet4i>(0); 282 res = vsetq_lane_s32(from[0*stride], res, 0); 283 res = vsetq_lane_s32(from[1*stride], res, 1); 284 res = vsetq_lane_s32(from[2*stride], res, 2); 285 res = vsetq_lane_s32(from[3*stride], res, 3); 286 return res; 287 } 288 289 template<> EIGEN_DEVICE_FUNC inline void pscatter<float, Packet4f>(float* to, const Packet4f& from, Index stride) 290 { 291 to[stride*0] = vgetq_lane_f32(from, 0); 292 to[stride*1] = vgetq_lane_f32(from, 1); 293 to[stride*2] = vgetq_lane_f32(from, 2); 294 to[stride*3] = vgetq_lane_f32(from, 3); 295 } 296 template<> EIGEN_DEVICE_FUNC inline void pscatter<int32_t, Packet4i>(int32_t* to, const Packet4i& from, Index stride) 297 { 298 to[stride*0] = vgetq_lane_s32(from, 0); 299 to[stride*1] = vgetq_lane_s32(from, 1); 300 to[stride*2] = vgetq_lane_s32(from, 2); 301 to[stride*3] = vgetq_lane_s32(from, 3); 302 } 303 304 template<> EIGEN_STRONG_INLINE void prefetch<float> (const float* addr) { EIGEN_ARM_PREFETCH(addr); } 305 template<> EIGEN_STRONG_INLINE void prefetch<int32_t>(const int32_t* addr) { EIGEN_ARM_PREFETCH(addr); } 306 307 // FIXME only store the 2 first elements ? 308 template<> EIGEN_STRONG_INLINE float pfirst<Packet4f>(const Packet4f& a) { float EIGEN_ALIGN16 x[4]; vst1q_f32(x, a); return x[0]; } 309 template<> EIGEN_STRONG_INLINE int32_t pfirst<Packet4i>(const Packet4i& a) { int32_t EIGEN_ALIGN16 x[4]; vst1q_s32(x, a); return x[0]; } 310 311 template<> EIGEN_STRONG_INLINE Packet4f preverse(const Packet4f& a) { 312 float32x2_t a_lo, a_hi; 313 Packet4f a_r64; 314 315 a_r64 = vrev64q_f32(a); 316 a_lo = vget_low_f32(a_r64); 317 a_hi = vget_high_f32(a_r64); 318 return vcombine_f32(a_hi, a_lo); 319 } 320 template<> EIGEN_STRONG_INLINE Packet4i preverse(const Packet4i& a) { 321 int32x2_t a_lo, a_hi; 322 Packet4i a_r64; 323 324 a_r64 = vrev64q_s32(a); 325 a_lo = vget_low_s32(a_r64); 326 a_hi = vget_high_s32(a_r64); 327 return vcombine_s32(a_hi, a_lo); 328 } 329 330 template<> EIGEN_STRONG_INLINE Packet4f pabs(const Packet4f& a) { return vabsq_f32(a); } 331 template<> EIGEN_STRONG_INLINE Packet4i pabs(const Packet4i& a) { return vabsq_s32(a); } 332 333 template<> EIGEN_STRONG_INLINE float predux<Packet4f>(const Packet4f& a) 334 { 335 float32x2_t a_lo, a_hi, sum; 336 337 a_lo = vget_low_f32(a); 338 a_hi = vget_high_f32(a); 339 sum = vpadd_f32(a_lo, a_hi); 340 sum = vpadd_f32(sum, sum); 341 return vget_lane_f32(sum, 0); 342 } 343 344 template<> EIGEN_STRONG_INLINE Packet4f preduxp<Packet4f>(const Packet4f* vecs) 345 { 346 float32x4x2_t vtrn1, vtrn2, res1, res2; 347 Packet4f sum1, sum2, sum; 348 349 // NEON zip performs interleaving of the supplied vectors. 350 // We perform two interleaves in a row to acquire the transposed vector 351 vtrn1 = vzipq_f32(vecs[0], vecs[2]); 352 vtrn2 = vzipq_f32(vecs[1], vecs[3]); 353 res1 = vzipq_f32(vtrn1.val[0], vtrn2.val[0]); 354 res2 = vzipq_f32(vtrn1.val[1], vtrn2.val[1]); 355 356 // Do the addition of the resulting vectors 357 sum1 = vaddq_f32(res1.val[0], res1.val[1]); 358 sum2 = vaddq_f32(res2.val[0], res2.val[1]); 359 sum = vaddq_f32(sum1, sum2); 360 361 return sum; 362 } 363 364 template<> EIGEN_STRONG_INLINE int32_t predux<Packet4i>(const Packet4i& a) 365 { 366 int32x2_t a_lo, a_hi, sum; 367 368 a_lo = vget_low_s32(a); 369 a_hi = vget_high_s32(a); 370 sum = vpadd_s32(a_lo, a_hi); 371 sum = vpadd_s32(sum, sum); 372 return vget_lane_s32(sum, 0); 373 } 374 375 template<> EIGEN_STRONG_INLINE Packet4i preduxp<Packet4i>(const Packet4i* vecs) 376 { 377 int32x4x2_t vtrn1, vtrn2, res1, res2; 378 Packet4i sum1, sum2, sum; 379 380 // NEON zip performs interleaving of the supplied vectors. 381 // We perform two interleaves in a row to acquire the transposed vector 382 vtrn1 = vzipq_s32(vecs[0], vecs[2]); 383 vtrn2 = vzipq_s32(vecs[1], vecs[3]); 384 res1 = vzipq_s32(vtrn1.val[0], vtrn2.val[0]); 385 res2 = vzipq_s32(vtrn1.val[1], vtrn2.val[1]); 386 387 // Do the addition of the resulting vectors 388 sum1 = vaddq_s32(res1.val[0], res1.val[1]); 389 sum2 = vaddq_s32(res2.val[0], res2.val[1]); 390 sum = vaddq_s32(sum1, sum2); 391 392 return sum; 393 } 394 395 // Other reduction functions: 396 // mul 397 template<> EIGEN_STRONG_INLINE float predux_mul<Packet4f>(const Packet4f& a) 398 { 399 float32x2_t a_lo, a_hi, prod; 400 401 // Get a_lo = |a1|a2| and a_hi = |a3|a4| 402 a_lo = vget_low_f32(a); 403 a_hi = vget_high_f32(a); 404 // Get the product of a_lo * a_hi -> |a1*a3|a2*a4| 405 prod = vmul_f32(a_lo, a_hi); 406 // Multiply prod with its swapped value |a2*a4|a1*a3| 407 prod = vmul_f32(prod, vrev64_f32(prod)); 408 409 return vget_lane_f32(prod, 0); 410 } 411 template<> EIGEN_STRONG_INLINE int32_t predux_mul<Packet4i>(const Packet4i& a) 412 { 413 int32x2_t a_lo, a_hi, prod; 414 415 // Get a_lo = |a1|a2| and a_hi = |a3|a4| 416 a_lo = vget_low_s32(a); 417 a_hi = vget_high_s32(a); 418 // Get the product of a_lo * a_hi -> |a1*a3|a2*a4| 419 prod = vmul_s32(a_lo, a_hi); 420 // Multiply prod with its swapped value |a2*a4|a1*a3| 421 prod = vmul_s32(prod, vrev64_s32(prod)); 422 423 return vget_lane_s32(prod, 0); 424 } 425 426 // min 427 template<> EIGEN_STRONG_INLINE float predux_min<Packet4f>(const Packet4f& a) 428 { 429 float32x2_t a_lo, a_hi, min; 430 431 a_lo = vget_low_f32(a); 432 a_hi = vget_high_f32(a); 433 min = vpmin_f32(a_lo, a_hi); 434 min = vpmin_f32(min, min); 435 436 return vget_lane_f32(min, 0); 437 } 438 439 template<> EIGEN_STRONG_INLINE int32_t predux_min<Packet4i>(const Packet4i& a) 440 { 441 int32x2_t a_lo, a_hi, min; 442 443 a_lo = vget_low_s32(a); 444 a_hi = vget_high_s32(a); 445 min = vpmin_s32(a_lo, a_hi); 446 min = vpmin_s32(min, min); 447 448 return vget_lane_s32(min, 0); 449 } 450 451 // max 452 template<> EIGEN_STRONG_INLINE float predux_max<Packet4f>(const Packet4f& a) 453 { 454 float32x2_t a_lo, a_hi, max; 455 456 a_lo = vget_low_f32(a); 457 a_hi = vget_high_f32(a); 458 max = vpmax_f32(a_lo, a_hi); 459 max = vpmax_f32(max, max); 460 461 return vget_lane_f32(max, 0); 462 } 463 464 template<> EIGEN_STRONG_INLINE int32_t predux_max<Packet4i>(const Packet4i& a) 465 { 466 int32x2_t a_lo, a_hi, max; 467 468 a_lo = vget_low_s32(a); 469 a_hi = vget_high_s32(a); 470 max = vpmax_s32(a_lo, a_hi); 471 max = vpmax_s32(max, max); 472 473 return vget_lane_s32(max, 0); 474 } 475 476 // this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors, 477 // see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074 478 #define PALIGN_NEON(Offset,Type,Command) \ 479 template<>\ 480 struct palign_impl<Offset,Type>\ 481 {\ 482 EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\ 483 {\ 484 if (Offset!=0)\ 485 first = Command(first, second, Offset);\ 486 }\ 487 };\ 488 489 PALIGN_NEON(0,Packet4f,vextq_f32) 490 PALIGN_NEON(1,Packet4f,vextq_f32) 491 PALIGN_NEON(2,Packet4f,vextq_f32) 492 PALIGN_NEON(3,Packet4f,vextq_f32) 493 PALIGN_NEON(0,Packet4i,vextq_s32) 494 PALIGN_NEON(1,Packet4i,vextq_s32) 495 PALIGN_NEON(2,Packet4i,vextq_s32) 496 PALIGN_NEON(3,Packet4i,vextq_s32) 497 498 #undef PALIGN_NEON 499 500 EIGEN_DEVICE_FUNC inline void 501 ptranspose(PacketBlock<Packet4f,4>& kernel) { 502 float32x4x2_t tmp1 = vzipq_f32(kernel.packet[0], kernel.packet[1]); 503 float32x4x2_t tmp2 = vzipq_f32(kernel.packet[2], kernel.packet[3]); 504 505 kernel.packet[0] = vcombine_f32(vget_low_f32(tmp1.val[0]), vget_low_f32(tmp2.val[0])); 506 kernel.packet[1] = vcombine_f32(vget_high_f32(tmp1.val[0]), vget_high_f32(tmp2.val[0])); 507 kernel.packet[2] = vcombine_f32(vget_low_f32(tmp1.val[1]), vget_low_f32(tmp2.val[1])); 508 kernel.packet[3] = vcombine_f32(vget_high_f32(tmp1.val[1]), vget_high_f32(tmp2.val[1])); 509 } 510 511 EIGEN_DEVICE_FUNC inline void 512 ptranspose(PacketBlock<Packet4i,4>& kernel) { 513 int32x4x2_t tmp1 = vzipq_s32(kernel.packet[0], kernel.packet[1]); 514 int32x4x2_t tmp2 = vzipq_s32(kernel.packet[2], kernel.packet[3]); 515 kernel.packet[0] = vcombine_s32(vget_low_s32(tmp1.val[0]), vget_low_s32(tmp2.val[0])); 516 kernel.packet[1] = vcombine_s32(vget_high_s32(tmp1.val[0]), vget_high_s32(tmp2.val[0])); 517 kernel.packet[2] = vcombine_s32(vget_low_s32(tmp1.val[1]), vget_low_s32(tmp2.val[1])); 518 kernel.packet[3] = vcombine_s32(vget_high_s32(tmp1.val[1]), vget_high_s32(tmp2.val[1])); 519 } 520 521 //---------- double ---------- 522 523 // Clang 3.5 in the iOS toolchain has an ICE triggered by NEON intrisics for double. 524 // Confirmed at least with __apple_build_version__ = 6000054. 525 #ifdef __apple_build_version__ 526 // Let's hope that by the time __apple_build_version__ hits the 601* range, the bug will be fixed. 527 // https://gist.github.com/yamaya/2924292 suggests that the 3 first digits are only updated with 528 // major toolchain updates. 529 #define EIGEN_APPLE_DOUBLE_NEON_BUG (__apple_build_version__ < 6010000) 530 #else 531 #define EIGEN_APPLE_DOUBLE_NEON_BUG 0 532 #endif 533 534 #if EIGEN_ARCH_ARM64 && !EIGEN_APPLE_DOUBLE_NEON_BUG 535 536 // Bug 907: workaround missing declarations of the following two functions in the ADK 537 // Defining these functions as templates ensures that if these intrinsics are 538 // already defined in arm_neon.h, then our workaround doesn't cause a conflict 539 // and has lower priority in overload resolution. 540 template <typename T> 541 uint64x2_t vreinterpretq_u64_f64(T a) 542 { 543 return (uint64x2_t) a; 544 } 545 546 template <typename T> 547 float64x2_t vreinterpretq_f64_u64(T a) 548 { 549 return (float64x2_t) a; 550 } 551 552 typedef float64x2_t Packet2d; 553 typedef float64x1_t Packet1d; 554 555 template<> struct packet_traits<double> : default_packet_traits 556 { 557 typedef Packet2d type; 558 typedef Packet2d half; 559 enum { 560 Vectorizable = 1, 561 AlignedOnScalar = 1, 562 size = 2, 563 HasHalfPacket=0, 564 565 HasDiv = 1, 566 // FIXME check the Has* 567 HasSin = 0, 568 HasCos = 0, 569 HasLog = 0, 570 HasExp = 0, 571 HasSqrt = 0 572 }; 573 }; 574 575 template<> struct unpacket_traits<Packet2d> { typedef double type; enum {size=2, alignment=Aligned16}; typedef Packet2d half; }; 576 577 template<> EIGEN_STRONG_INLINE Packet2d pset1<Packet2d>(const double& from) { return vdupq_n_f64(from); } 578 579 template<> EIGEN_STRONG_INLINE Packet2d plset<Packet2d>(const double& a) 580 { 581 const double countdown_raw[] = {0.0,1.0}; 582 const Packet2d countdown = vld1q_f64(countdown_raw); 583 return vaddq_f64(pset1<Packet2d>(a), countdown); 584 } 585 template<> EIGEN_STRONG_INLINE Packet2d padd<Packet2d>(const Packet2d& a, const Packet2d& b) { return vaddq_f64(a,b); } 586 587 template<> EIGEN_STRONG_INLINE Packet2d psub<Packet2d>(const Packet2d& a, const Packet2d& b) { return vsubq_f64(a,b); } 588 589 template<> EIGEN_STRONG_INLINE Packet2d pnegate(const Packet2d& a) { return vnegq_f64(a); } 590 591 template<> EIGEN_STRONG_INLINE Packet2d pconj(const Packet2d& a) { return a; } 592 593 template<> EIGEN_STRONG_INLINE Packet2d pmul<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmulq_f64(a,b); } 594 595 template<> EIGEN_STRONG_INLINE Packet2d pdiv<Packet2d>(const Packet2d& a, const Packet2d& b) { return vdivq_f64(a,b); } 596 597 #ifdef __ARM_FEATURE_FMA 598 // See bug 936. See above comment about FMA for float. 599 template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vfmaq_f64(c,a,b); } 600 #else 601 template<> EIGEN_STRONG_INLINE Packet2d pmadd(const Packet2d& a, const Packet2d& b, const Packet2d& c) { return vmlaq_f64(c,a,b); } 602 #endif 603 604 template<> EIGEN_STRONG_INLINE Packet2d pmin<Packet2d>(const Packet2d& a, const Packet2d& b) { return vminq_f64(a,b); } 605 606 template<> EIGEN_STRONG_INLINE Packet2d pmax<Packet2d>(const Packet2d& a, const Packet2d& b) { return vmaxq_f64(a,b); } 607 608 // Logical Operations are not supported for float, so we have to reinterpret casts using NEON intrinsics 609 template<> EIGEN_STRONG_INLINE Packet2d pand<Packet2d>(const Packet2d& a, const Packet2d& b) 610 { 611 return vreinterpretq_f64_u64(vandq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b))); 612 } 613 614 template<> EIGEN_STRONG_INLINE Packet2d por<Packet2d>(const Packet2d& a, const Packet2d& b) 615 { 616 return vreinterpretq_f64_u64(vorrq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b))); 617 } 618 619 template<> EIGEN_STRONG_INLINE Packet2d pxor<Packet2d>(const Packet2d& a, const Packet2d& b) 620 { 621 return vreinterpretq_f64_u64(veorq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b))); 622 } 623 624 template<> EIGEN_STRONG_INLINE Packet2d pandnot<Packet2d>(const Packet2d& a, const Packet2d& b) 625 { 626 return vreinterpretq_f64_u64(vbicq_u64(vreinterpretq_u64_f64(a),vreinterpretq_u64_f64(b))); 627 } 628 629 template<> EIGEN_STRONG_INLINE Packet2d pload<Packet2d>(const double* from) { EIGEN_DEBUG_ALIGNED_LOAD return vld1q_f64(from); } 630 631 template<> EIGEN_STRONG_INLINE Packet2d ploadu<Packet2d>(const double* from) { EIGEN_DEBUG_UNALIGNED_LOAD return vld1q_f64(from); } 632 633 template<> EIGEN_STRONG_INLINE Packet2d ploaddup<Packet2d>(const double* from) 634 { 635 return vld1q_dup_f64(from); 636 } 637 template<> EIGEN_STRONG_INLINE void pstore<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_ALIGNED_STORE vst1q_f64(to, from); } 638 639 template<> EIGEN_STRONG_INLINE void pstoreu<double>(double* to, const Packet2d& from) { EIGEN_DEBUG_UNALIGNED_STORE vst1q_f64(to, from); } 640 641 template<> EIGEN_DEVICE_FUNC inline Packet2d pgather<double, Packet2d>(const double* from, Index stride) 642 { 643 Packet2d res = pset1<Packet2d>(0.0); 644 res = vsetq_lane_f64(from[0*stride], res, 0); 645 res = vsetq_lane_f64(from[1*stride], res, 1); 646 return res; 647 } 648 template<> EIGEN_DEVICE_FUNC inline void pscatter<double, Packet2d>(double* to, const Packet2d& from, Index stride) 649 { 650 to[stride*0] = vgetq_lane_f64(from, 0); 651 to[stride*1] = vgetq_lane_f64(from, 1); 652 } 653 template<> EIGEN_STRONG_INLINE void prefetch<double>(const double* addr) { EIGEN_ARM_PREFETCH(addr); } 654 655 // FIXME only store the 2 first elements ? 656 template<> EIGEN_STRONG_INLINE double pfirst<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(a, 0); } 657 658 template<> EIGEN_STRONG_INLINE Packet2d preverse(const Packet2d& a) { return vcombine_f64(vget_high_f64(a), vget_low_f64(a)); } 659 660 template<> EIGEN_STRONG_INLINE Packet2d pabs(const Packet2d& a) { return vabsq_f64(a); } 661 662 #if EIGEN_COMP_CLANG && defined(__apple_build_version__) 663 // workaround ICE, see bug 907 664 template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) + vget_high_f64(a))[0]; } 665 #else 666 template<> EIGEN_STRONG_INLINE double predux<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) + vget_high_f64(a), 0); } 667 #endif 668 669 template<> EIGEN_STRONG_INLINE Packet2d preduxp<Packet2d>(const Packet2d* vecs) 670 { 671 float64x2_t trn1, trn2; 672 673 // NEON zip performs interleaving of the supplied vectors. 674 // We perform two interleaves in a row to acquire the transposed vector 675 trn1 = vzip1q_f64(vecs[0], vecs[1]); 676 trn2 = vzip2q_f64(vecs[0], vecs[1]); 677 678 // Do the addition of the resulting vectors 679 return vaddq_f64(trn1, trn2); 680 } 681 // Other reduction functions: 682 // mul 683 #if EIGEN_COMP_CLANG && defined(__apple_build_version__) 684 template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return (vget_low_f64(a) * vget_high_f64(a))[0]; } 685 #else 686 template<> EIGEN_STRONG_INLINE double predux_mul<Packet2d>(const Packet2d& a) { return vget_lane_f64(vget_low_f64(a) * vget_high_f64(a), 0); } 687 #endif 688 689 // min 690 template<> EIGEN_STRONG_INLINE double predux_min<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpminq_f64(a, a), 0); } 691 692 // max 693 template<> EIGEN_STRONG_INLINE double predux_max<Packet2d>(const Packet2d& a) { return vgetq_lane_f64(vpmaxq_f64(a, a), 0); } 694 695 // this PALIGN_NEON business is to work around a bug in LLVM Clang 3.0 causing incorrect compilation errors, 696 // see bug 347 and this LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=11074 697 #define PALIGN_NEON(Offset,Type,Command) \ 698 template<>\ 699 struct palign_impl<Offset,Type>\ 700 {\ 701 EIGEN_STRONG_INLINE static void run(Type& first, const Type& second)\ 702 {\ 703 if (Offset!=0)\ 704 first = Command(first, second, Offset);\ 705 }\ 706 };\ 707 708 PALIGN_NEON(0,Packet2d,vextq_f64) 709 PALIGN_NEON(1,Packet2d,vextq_f64) 710 #undef PALIGN_NEON 711 712 EIGEN_DEVICE_FUNC inline void 713 ptranspose(PacketBlock<Packet2d,2>& kernel) { 714 float64x2_t trn1 = vzip1q_f64(kernel.packet[0], kernel.packet[1]); 715 float64x2_t trn2 = vzip2q_f64(kernel.packet[0], kernel.packet[1]); 716 717 kernel.packet[0] = trn1; 718 kernel.packet[1] = trn2; 719 } 720 #endif // EIGEN_ARCH_ARM64 721 722 } // end namespace internal 723 724 } // end namespace Eigen 725 726 #endif // EIGEN_PACKET_MATH_NEON_H 727