1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // ARM-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(ArmAdd) \ 16 V(ArmAnd) \ 17 V(ArmBic) \ 18 V(ArmClz) \ 19 V(ArmCmp) \ 20 V(ArmCmn) \ 21 V(ArmTst) \ 22 V(ArmTeq) \ 23 V(ArmOrr) \ 24 V(ArmEor) \ 25 V(ArmSub) \ 26 V(ArmRsb) \ 27 V(ArmMul) \ 28 V(ArmMla) \ 29 V(ArmMls) \ 30 V(ArmSmull) \ 31 V(ArmSmmul) \ 32 V(ArmSmmla) \ 33 V(ArmUmull) \ 34 V(ArmSdiv) \ 35 V(ArmUdiv) \ 36 V(ArmMov) \ 37 V(ArmMvn) \ 38 V(ArmBfc) \ 39 V(ArmUbfx) \ 40 V(ArmSbfx) \ 41 V(ArmSxtb) \ 42 V(ArmSxth) \ 43 V(ArmSxtab) \ 44 V(ArmSxtah) \ 45 V(ArmUxtb) \ 46 V(ArmUxth) \ 47 V(ArmUxtab) \ 48 V(ArmRbit) \ 49 V(ArmUxtah) \ 50 V(ArmAddPair) \ 51 V(ArmSubPair) \ 52 V(ArmMulPair) \ 53 V(ArmLslPair) \ 54 V(ArmLsrPair) \ 55 V(ArmAsrPair) \ 56 V(ArmVcmpF32) \ 57 V(ArmVaddF32) \ 58 V(ArmVsubF32) \ 59 V(ArmVmulF32) \ 60 V(ArmVmlaF32) \ 61 V(ArmVmlsF32) \ 62 V(ArmVdivF32) \ 63 V(ArmVabsF32) \ 64 V(ArmVnegF32) \ 65 V(ArmVsqrtF32) \ 66 V(ArmVcmpF64) \ 67 V(ArmVaddF64) \ 68 V(ArmVsubF64) \ 69 V(ArmVmulF64) \ 70 V(ArmVmlaF64) \ 71 V(ArmVmlsF64) \ 72 V(ArmVdivF64) \ 73 V(ArmVmodF64) \ 74 V(ArmVabsF64) \ 75 V(ArmVnegF64) \ 76 V(ArmVsqrtF64) \ 77 V(ArmVrintmF32) \ 78 V(ArmVrintmF64) \ 79 V(ArmVrintpF32) \ 80 V(ArmVrintpF64) \ 81 V(ArmVrintzF32) \ 82 V(ArmVrintzF64) \ 83 V(ArmVrintaF64) \ 84 V(ArmVrintnF32) \ 85 V(ArmVrintnF64) \ 86 V(ArmVcvtF32F64) \ 87 V(ArmVcvtF64F32) \ 88 V(ArmVcvtF32S32) \ 89 V(ArmVcvtF32U32) \ 90 V(ArmVcvtF64S32) \ 91 V(ArmVcvtF64U32) \ 92 V(ArmVcvtS32F32) \ 93 V(ArmVcvtU32F32) \ 94 V(ArmVcvtS32F64) \ 95 V(ArmVcvtU32F64) \ 96 V(ArmVmovU32F32) \ 97 V(ArmVmovF32U32) \ 98 V(ArmVmovLowU32F64) \ 99 V(ArmVmovLowF64U32) \ 100 V(ArmVmovHighU32F64) \ 101 V(ArmVmovHighF64U32) \ 102 V(ArmVmovF64U32U32) \ 103 V(ArmVmovU32U32F64) \ 104 V(ArmVldrF32) \ 105 V(ArmVstrF32) \ 106 V(ArmVldrF64) \ 107 V(ArmVstrF64) \ 108 V(ArmFloat32Max) \ 109 V(ArmFloat64Max) \ 110 V(ArmFloat32Min) \ 111 V(ArmFloat64Min) \ 112 V(ArmFloat64SilenceNaN) \ 113 V(ArmLdrb) \ 114 V(ArmLdrsb) \ 115 V(ArmStrb) \ 116 V(ArmLdrh) \ 117 V(ArmLdrsh) \ 118 V(ArmStrh) \ 119 V(ArmLdr) \ 120 V(ArmStr) \ 121 V(ArmPush) \ 122 V(ArmPoke) 123 124 // Addressing modes represent the "shape" of inputs to an instruction. 125 // Many instructions support multiple addressing modes. Addressing modes 126 // are encoded into the InstructionCode of the instruction and tell the 127 // code generator after register allocation which assembler method to call. 128 #define TARGET_ADDRESSING_MODE_LIST(V) \ 129 V(Offset_RI) /* [%r0 + K] */ \ 130 V(Offset_RR) /* [%r0 + %r1] */ \ 131 V(Operand2_I) /* K */ \ 132 V(Operand2_R) /* %r0 */ \ 133 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 134 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 135 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 136 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 137 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 138 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 139 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 140 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 141 142 } // namespace compiler 143 } // namespace internal 144 } // namespace v8 145 146 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 147