1 /*
2  * Copyright (C) 2014 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_
18 #define ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_
19 
20 #include "constants_mips64.h"
21 #include "debug/dwarf/register.h"
22 #include "utils/managed_register.h"
23 
24 namespace art {
25 namespace mips64 {
26 
27 const int kNumberOfGpuRegIds = kNumberOfGpuRegisters;
28 const int kNumberOfGpuAllocIds = kNumberOfGpuRegisters;
29 
30 const int kNumberOfFpuRegIds = kNumberOfFpuRegisters;
31 const int kNumberOfFpuAllocIds = kNumberOfFpuRegisters;
32 
33 const int kNumberOfVecRegIds = kNumberOfVectorRegisters;
34 const int kNumberOfVecAllocIds = kNumberOfVectorRegisters;
35 
36 const int kNumberOfRegIds = kNumberOfGpuRegIds + kNumberOfFpuRegIds + kNumberOfVecRegIds;
37 const int kNumberOfAllocIds = kNumberOfGpuAllocIds + kNumberOfFpuAllocIds + kNumberOfVecAllocIds;
38 
39 // Register ids map:
40 //   [0..R[  core registers (enum GpuRegister)
41 //   [R..F[  floating-point registers (enum FpuRegister)
42 //   [F..W[  MSA vector registers (enum VectorRegister)
43 // where
44 //   R = kNumberOfGpuRegIds
45 //   F = R + kNumberOfFpuRegIds
46 //   W = F + kNumberOfVecRegIds
47 
48 // An instance of class 'ManagedRegister' represents a single Mips64 register.
49 // A register can be one of the following:
50 //  * core register (enum GpuRegister)
51 //  * floating-point register (enum FpuRegister)
52 //  * MSA vector register (enum VectorRegister)
53 //
54 // 'ManagedRegister::NoRegister()' provides an invalid register.
55 // There is a one-to-one mapping between ManagedRegister and register id.
56 class Mips64ManagedRegister : public ManagedRegister {
57  public:
AsGpuRegister()58   constexpr GpuRegister AsGpuRegister() const {
59     CHECK(IsGpuRegister());
60     return static_cast<GpuRegister>(id_);
61   }
62 
AsFpuRegister()63   constexpr FpuRegister AsFpuRegister() const {
64     CHECK(IsFpuRegister());
65     return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds);
66   }
67 
AsVectorRegister()68   constexpr VectorRegister AsVectorRegister() const {
69     CHECK(IsVectorRegister());
70     return static_cast<VectorRegister>(id_ - (kNumberOfGpuRegIds + kNumberOfFpuRegisters));
71   }
72 
AsOverlappingFpuRegister()73   constexpr FpuRegister AsOverlappingFpuRegister() const {
74     CHECK(IsValidManagedRegister());
75     return static_cast<FpuRegister>(AsVectorRegister());
76   }
77 
AsOverlappingVectorRegister()78   constexpr VectorRegister AsOverlappingVectorRegister() const {
79     CHECK(IsValidManagedRegister());
80     return static_cast<VectorRegister>(AsFpuRegister());
81   }
82 
IsGpuRegister()83   constexpr bool IsGpuRegister() const {
84     CHECK(IsValidManagedRegister());
85     return (0 <= id_) && (id_ < kNumberOfGpuRegIds);
86   }
87 
IsFpuRegister()88   constexpr bool IsFpuRegister() const {
89     CHECK(IsValidManagedRegister());
90     const int test = id_ - kNumberOfGpuRegIds;
91     return (0 <= test) && (test < kNumberOfFpuRegIds);
92   }
93 
IsVectorRegister()94   constexpr bool IsVectorRegister() const {
95     CHECK(IsValidManagedRegister());
96     const int test = id_ - (kNumberOfGpuRegIds + kNumberOfFpuRegIds);
97     return (0 <= test) && (test < kNumberOfVecRegIds);
98   }
99 
100   void Print(std::ostream& os) const;
101 
102   // Returns true if the two managed-registers ('this' and 'other') overlap.
103   // Either managed-register may be the NoRegister. If both are the NoRegister
104   // then false is returned.
105   bool Overlaps(const Mips64ManagedRegister& other) const;
106 
FromGpuRegister(GpuRegister r)107   static constexpr Mips64ManagedRegister FromGpuRegister(GpuRegister r) {
108     CHECK_NE(r, kNoGpuRegister);
109     return FromRegId(r);
110   }
111 
FromFpuRegister(FpuRegister r)112   static constexpr Mips64ManagedRegister FromFpuRegister(FpuRegister r) {
113     CHECK_NE(r, kNoFpuRegister);
114     return FromRegId(r + kNumberOfGpuRegIds);
115   }
116 
FromVectorRegister(VectorRegister r)117   static constexpr Mips64ManagedRegister FromVectorRegister(VectorRegister r) {
118     CHECK_NE(r, kNoVectorRegister);
119     return FromRegId(r + kNumberOfGpuRegIds + kNumberOfFpuRegIds);
120   }
121 
122  private:
IsValidManagedRegister()123   constexpr bool IsValidManagedRegister() const {
124     return (0 <= id_) && (id_ < kNumberOfRegIds);
125   }
126 
RegId()127   constexpr int RegId() const {
128     CHECK(!IsNoRegister());
129     return id_;
130   }
131 
AllocId()132   int AllocId() const {
133     CHECK(IsValidManagedRegister());
134     CHECK_LT(id_, kNumberOfAllocIds);
135     return id_;
136   }
137 
138   int AllocIdLow() const;
139   int AllocIdHigh() const;
140 
141   friend class ManagedRegister;
142 
Mips64ManagedRegister(int reg_id)143   explicit constexpr Mips64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {}
144 
FromRegId(int reg_id)145   static constexpr Mips64ManagedRegister FromRegId(int reg_id) {
146     Mips64ManagedRegister reg(reg_id);
147     CHECK(reg.IsValidManagedRegister());
148     return reg;
149   }
150 };
151 
152 std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg);
153 
154 }  // namespace mips64
155 
AsMips64()156 constexpr inline mips64::Mips64ManagedRegister ManagedRegister::AsMips64() const {
157   mips64::Mips64ManagedRegister reg(id_);
158   CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister());
159   return reg;
160 }
161 
162 }  // namespace art
163 
164 #endif  // ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_
165