| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 94 registers_.push_back(new mips64::GpuRegister(mips64::A0)); in SetUpHelpers()
127 secondary_register_names_.emplace(mips64::GpuRegister(mips64::A0), "a0"); in SetUpHelpers()
264 (Base::GetAssembler()->*f)(mips64::A0, &label); in BranchCondOneRegHelper()
293 (Base::GetAssembler()->*f)(mips64::A0, mips64::A1, &label); in BranchCondTwoRegsHelper()
889 __ Beqc(mips64::A0, mips64::A1, &label); in TEST_F()
1599 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A0, 0); in TEST_F()
1600 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0); in TEST_F()
1601 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1); in TEST_F()
1602 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 256); in TEST_F()
1603 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1000); in TEST_F()
[all …]
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| D | managed_register_mips64_test.cc | 52 reg = Mips64ManagedRegister::FromGpuRegister(A0); in TEST()
57 EXPECT_EQ(A0, reg.AsGpuRegister()); in TEST()
221 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
282 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
300 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
318 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
336 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
354 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
372 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
390 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(A0))); in TEST()
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| D | assembler_mips64.cc | 3243 Move(A0, exception->scratch_.AsGpuRegister()); in EmitExceptionPoll()
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 61 registers_.push_back(new mips::Register(mips::A0)); in SetUpHelpers()
94 secondary_register_names_.emplace(mips::Register(mips::A0), "a0"); in SetUpHelpers()
193 (Base::GetAssembler()->*f)(mips::A0, &label); in BranchCondOneRegHelper()
222 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label); in BranchCondTwoRegsHelper()
928 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, -0x8000); in TEST_F()
929 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0); in TEST_F()
930 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FF8); in TEST_F()
931 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFB); in TEST_F()
932 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFC); in TEST_F()
933 __ LoadFromOffset(mips::kLoadDoubleword, mips::A0, mips::A2, +0x7FFF); in TEST_F()
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| D | assembler_mips32r6_test.cc | 91 registers_.push_back(new mips::Register(mips::A0)); in SetUpHelpers()
124 secondary_register_names_.emplace(mips::Register(mips::A0), "a0"); in SetUpHelpers()
224 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label); in BranchCondTwoRegsHelper()
505 __ LoadDFromOffset(mips::F0, mips::A0, -0x8000); in TEST_F()
506 __ LoadDFromOffset(mips::F0, mips::A0, +0); in TEST_F()
507 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FF8); in TEST_F()
508 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFB); in TEST_F()
509 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFC); in TEST_F()
510 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFF); in TEST_F()
511 __ LoadDFromOffset(mips::F0, mips::A0, -0xFFF0); in TEST_F()
[all …]
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| D | assembler_mips.cc | 3778 Move(A0, exception->scratch_.AsCoreRegister()); in EmitExceptionPoll()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 145 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value()); in CreateTrampoline()
148 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value()); in CreateTrampoline()
177 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); in CreateTrampoline()
180 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value()); in CreateTrampoline()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 37 static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 };
45 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
113 return MipsManagedRegister::FromCoreRegister(A0); in MethodRegister()
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| /art/runtime/arch/mips64/ |
| D | context_mips64.cc | 32 gprs_[A0] = &arg0_; in Reset()
76 gprs_[A0] = nullptr; in SmashCallerSaves()
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| D | context_mips64.h | 82 SetGPR(A0, new_arg0_value); in SetArg0()
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| D | registers_mips64.h | 34 A0 = 4, // Arguments. enumerator
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| D | fault_handler_mips64.cc | 56 *out_method = reinterpret_cast<ArtMethod*>(sc->sc_regs[mips64::A0]); in GetMethodAndReturnPcAndSp()
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| D | quick_method_frame_info_mips64.h | 42 (1 << art::mips64::A0) | (1 << art::mips64::A1) | (1 << art::mips64::A2) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 34 A0 = 4, // Arguments. enumerator
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| D | context_mips.h | 82 SetGPR(A0, new_arg0_value); in SetArg0()
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| D | fault_handler_mips.cc | 55 *out_method = reinterpret_cast<ArtMethod*>(sc->sc_regs[mips::A0]); in GetMethodAndReturnPcAndSp()
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| D | context_mips.cc | 32 gprs_[A0] = &arg0_; in Reset()
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| D | quick_method_frame_info_mips.h | 40 (1 << art::mips::A0) | (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) |
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| D | quick_entrypoints_mips.S | 940 li $t6, 0 # t6 = gpr_index = 0 (corresponds to A2; A0 and A1 are skipped)
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 30 A0, A1, A2, A3, A4, A5, A6, A7
98 return Mips64ManagedRegister::FromGpuRegister(A0); in MethodRegister()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 44 { A0, A1, A2, A3, A4, A5, A6, A7 };
113 return Location::RegisterLocation(A0); in GetFieldIndexLocation()
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| D | optimizing_cfi_test.cc | 242 __ Beqz(mips::A0, &target); in TEST_F()
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| D | code_generator_mips.h | 46 { A0, A1, A2, A3 };
115 return Location::RegisterLocation(A0); in GetFieldIndexLocation()
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| D | intrinsics_mips64.cc | 104 Location::RegisterLocation(A0)); in EmitNativeCode()
106 codegen->GenerateVirtualCall(invoke_->AsInvokeVirtual(), Location::RegisterLocation(A0)); in EmitNativeCode()
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| D | intrinsics_mips.cc | 115 Location::RegisterLocation(A0)); in EmitNativeCode()
117 codegen->GenerateVirtualCall(invoke_->AsInvokeVirtual(), Location::RegisterLocation(A0)); in EmitNativeCode()
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