| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 62 registers_.push_back(new mips::Register(mips::A1)); in SetUpHelpers()
95 secondary_register_names_.emplace(mips::Register(mips::A1), "a1"); in SetUpHelpers()
203 (Base::GetAssembler()->*f)(mips::A1, &label); in BranchCondOneRegHelper()
222 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label); in BranchCondTwoRegsHelper()
771 __ Addiu32(mips::A1, mips::A2, -0x8000); in TEST_F()
772 __ Addiu32(mips::A1, mips::A2, +0); in TEST_F()
773 __ Addiu32(mips::A1, mips::A2, +0x7FFF); in TEST_F()
774 __ Addiu32(mips::A1, mips::A2, -0x10000); in TEST_F()
775 __ Addiu32(mips::A1, mips::A2, -0x8001); in TEST_F()
776 __ Addiu32(mips::A1, mips::A2, +0x8000); in TEST_F()
[all …]
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| D | assembler_mips32r6_test.cc | 92 registers_.push_back(new mips::Register(mips::A1)); in SetUpHelpers()
125 secondary_register_names_.emplace(mips::Register(mips::A1), "a1"); in SetUpHelpers()
224 (Base::GetAssembler()->*f)(mips::A0, mips::A1, &label); in BranchCondTwoRegsHelper()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 95 registers_.push_back(new mips64::GpuRegister(mips64::A1)); in SetUpHelpers()
128 secondary_register_names_.emplace(mips64::GpuRegister(mips64::A1), "a1"); in SetUpHelpers()
274 (Base::GetAssembler()->*f)(mips64::A1, &label); in BranchCondOneRegHelper()
293 (Base::GetAssembler()->*f)(mips64::A0, mips64::A1, &label); in BranchCondTwoRegsHelper()
889 __ Beqc(mips64::A0, mips64::A1, &label); in TEST_F()
1112 __ LoadLiteral(mips64::A1, mips64::kLoadDoubleword, literal1); in TEST_F()
1145 __ LoadLiteral(mips64::A1, mips64::kLoadDoubleword, literal1); in TEST_F()
1600 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 0); in TEST_F()
1601 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 1); in TEST_F()
1602 __ LoadFromOffset(mips64::kLoadSignedByte, mips64::A0, mips64::A1, 256); in TEST_F()
[all …]
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| D | managed_register_mips64_test.cc | 205 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
213 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
218 Mips64ManagedRegister reg_A1 = Mips64ManagedRegister::FromGpuRegister(A1); in TEST()
222 EXPECT_TRUE(reg_A1.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
230 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
239 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
249 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
259 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
269 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(A1))); in TEST()
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 35 A1 = 5, enumerator
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| D | quick_method_frame_info_mips.h | 34 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) | (1 << art::mips::T0) |
40 (1 << art::mips::A0) | (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) |
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| D | context_mips.cc | 75 gprs_[A1] = nullptr; in SmashCallerSaves()
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| D | quick_entrypoints_mips.S | 940 li $t6, 0 # t6 = gpr_index = 0 (corresponds to A2; A0 and A1 are skipped)
1496 # an even-numbered register, hence A1 may be skipped
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| /art/runtime/arch/mips64/ |
| D | quick_method_frame_info_mips64.h | 35 (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) |
42 (1 << art::mips64::A0) | (1 << art::mips64::A1) | (1 << art::mips64::A2) |
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| D | registers_mips64.h | 35 A1 = 5, enumerator
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| D | context_mips64.cc | 75 gprs_[A1] = nullptr; in SmashCallerSaves()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 37 static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 };
45 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 33 { A1, A2, A3, A4, A5, A6, A7 };
44 { A0, A1, A2, A3, A4, A5, A6, A7 };
110 return Location::RegisterLocation(A1); in GetObjectLocation()
122 : Location::RegisterLocation(A1); in GetSetValueLocation()
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| D | code_generator_mips.h | 35 { A1, A2, A3, T0, T1 };
46 { A0, A1, A2, A3 };
112 return Location::RegisterLocation(A1); in GetObjectLocation()
125 : (is_instance ? Location::RegisterLocation(A2) : Location::RegisterLocation(A1)); in GetSetValueLocation()
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| D | optimizing_cfi_test.cc | 272 __ Beqc(mips64::A1, mips64::A2, &target); in TEST_F()
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| D | code_generator_mips.cc | 103 if (reg == A1 || reg == A3) { in GetNextLocation()
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 30 A0, A1, A2, A3, A4, A5, A6, A7
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