Searched refs:AsDRegister (Results 1 – 11 of 11) sorted by relevance
| /art/compiler/utils/arm64/ |
| D | managed_register_arm64.cc | 56 no = static_cast<int>(AsDRegister()); in RegNo()
94 os << "DRegister: " << static_cast<int>(AsDRegister()); in Print()
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| D | managed_register_arm64.h | 69 constexpr DRegister AsDRegister() const { in AsDRegister() function
93 return static_cast<SRegister>(AsDRegister()); in AsOverlappingSRegister()
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| D | jni_macro_assembler_arm64.cc | 141 StoreDToOffset(src.AsDRegister(), SP, offs.Int32Value()); in Store()
278 ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset)); in Load()
356 ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister())); in Move()
700 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode()); in BuildFrame()
736 StoreDToOffset(reg.AsDRegister(), SP, offset); in BuildFrame()
756 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode()); in RemoveFrame()
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| D | managed_register_arm64_test.cc | 176 EXPECT_EQ(D0, reg.AsDRegister()); in TEST()
188 EXPECT_EQ(D1, reg.AsDRegister()); in TEST()
200 EXPECT_EQ(D20, reg.AsDRegister()); in TEST()
212 EXPECT_EQ(D31, reg.AsDRegister()); in TEST()
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| /art/compiler/utils/mips/ |
| D | managed_register_mips.h | 100 constexpr DRegister AsDRegister() const { in AsDRegister() function
107 DRegister d_reg = AsDRegister(); in AsOverlappingDRegisterLow()
113 DRegister d_reg = AsDRegister(); in AsOverlappingDRegisterHigh()
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| D | managed_register_mips.cc | 86 os << "DRegister: " << static_cast<int>(AsDRegister()); in Print()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm.h | 114 constexpr DRegister AsDRegister() const { in AsDRegister() function
126 DRegister d_reg = AsDRegister(); in AsOverlappingDRegisterLow()
132 DRegister d_reg = AsDRegister(); in AsOverlappingDRegisterHigh()
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| D | managed_register_arm.cc | 86 os << "DRegister: " << static_cast<int>(AsDRegister()); in Print()
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| D | jni_macro_assembler_arm.cc | 138 __ StoreDToOffset(reg.AsDRegister(), SP, offset); in BuildFrame()
208 __ StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value()); in Store()
305 assembler->LoadDFromOffset(dst.AsDRegister(), src_register, src_offset); in EmitLoad()
371 __ vmovd(dst.AsDRegister(), src.AsDRegister()); in Move()
375 __ vmovdrr(dst.AsDRegister(), src.AsRegisterPairLow(), src.AsRegisterPairHigh()); in Move()
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| D | managed_register_arm_test.cc | 133 EXPECT_EQ(D0, reg.AsDRegister()); in TEST()
145 EXPECT_EQ(D1, reg.AsDRegister()); in TEST()
157 EXPECT_EQ(D6, reg.AsDRegister()); in TEST()
169 EXPECT_EQ(D14, reg.AsDRegister()); in TEST()
181 EXPECT_EQ(D15, reg.AsDRegister()); in TEST()
194 EXPECT_EQ(D16, reg.AsDRegister()); in TEST()
203 EXPECT_EQ(D18, reg.AsDRegister()); in TEST()
212 EXPECT_EQ(D30, reg.AsDRegister()); in TEST()
221 EXPECT_EQ(D31, reg.AsDRegister()); in TEST()
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 100 result |= (1 << r.AsArm64().AsDRegister()); in CalculateFpCalleeSpillMask()
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