Home
last modified time | relevance | path

Searched refs:GetRegister (Results 1 – 19 of 19) sorted by relevance

/art/compiler/optimizing/
Dregister_allocator_linear_scan.cc40 return GetHighForLowRegister(low->GetRegister()) != low->GetHighInterval()->GetRegister(); in IsLowOfUnalignedPairInterval()
146 DCHECK(interval->GetRegister() == reg); in BlockRegister()
460 codegen_->DumpFloatingPointRegister(stream, interval->GetRegister()); in DumpInterval()
462 codegen_->DumpCoreRegister(stream, interval->GetRegister()); in DumpInterval()
573 ? Location::RegisterLocation(current->GetRegister()) in LinearScan()
574 : Location::FpuRegisterLocation(current->GetRegister())); in LinearScan()
577 current->GetHighInterval()->SetRegister(GetHighForLowRegister(current->GetRegister())); in LinearScan()
591 free_until[interval->GetRegister()] = kMaxLifetimePosition; in FreeIfNotCoverAt()
594 free_until[interval->GetHighInterval()->GetRegister()] = kMaxLifetimePosition; in FreeIfNotCoverAt()
599 free_until[interval->GetRegister()] = interval->FirstUseAfter(position); in FreeIfNotCoverAt()
[all …]
Dregister_allocator_test.cc336 ASSERT_NE(phi_interval->GetRegister(), loop_update->GetRegister()); in Loop3()
340 ASSERT_EQ(phi_interval->GetRegister(), ret->InputAt(0)->GetLiveInterval()->GetRegister()); in Loop3()
580 ASSERT_EQ(input1->GetLiveInterval()->GetRegister(), 0); in PhiHint()
581 ASSERT_EQ(input2->GetLiveInterval()->GetRegister(), 0); in PhiHint()
582 ASSERT_EQ(phi->GetLiveInterval()->GetRegister(), 0); in PhiHint()
600 ASSERT_EQ(input1->GetLiveInterval()->GetRegister(), 2); in PhiHint()
601 ASSERT_EQ(input2->GetLiveInterval()->GetRegister(), 2); in PhiHint()
602 ASSERT_EQ(phi->GetLiveInterval()->GetRegister(), 2); in PhiHint()
620 ASSERT_EQ(input1->GetLiveInterval()->GetRegister(), 2); in PhiHint()
621 ASSERT_EQ(input2->GetLiveInterval()->GetRegister(), 2); in PhiHint()
[all …]
Dregister_allocator.cc149 CHECK(codegen.HasAllocatedRegister(processing_core_registers, current->GetRegister())); in ValidateIntervals()
151 BitVector* liveness_of_register = liveness_of_values[current->GetRegister()]; in ValidateIntervals()
165 codegen.DumpCoreRegister(message, current->GetRegister()); in ValidateIntervals()
167 codegen.DumpFloatingPointRegister(message, current->GetRegister()); in ValidateIntervals()
171 && interval->GetRegister() == current->GetRegister() in ValidateIntervals()
Dssa_liveness_analysis.cc300 stream << ", register:" << GetRegister() << "("; in DumpWithContext()
302 codegen.DumpFloatingPointRegister(stream, GetRegister()); in DumpWithContext()
304 codegen.DumpCoreRegister(stream, GetRegister()); in DumpWithContext()
352 && (free_until[existing->GetRegister()] >= next_register_use)) { in FindFirstRegisterHint()
353 return existing->GetRegister(); in FindFirstRegisterHint()
488 return Location::FpuRegisterPairLocation(GetRegister(), GetHighInterval()->GetRegister()); in ToLocation()
490 return Location::FpuRegisterLocation(GetRegister()); in ToLocation()
494 return Location::RegisterPairLocation(GetRegister(), GetHighInterval()->GetRegister()); in ToLocation()
496 return Location::RegisterLocation(GetRegister()); in ToLocation()
Dregister_allocator_graph_color.cc672 ? Location::RegisterLocation(interval->GetRegister()) in AllocateRegisters()
673 : Location::FpuRegisterLocation(interval->GetRegister()); in AllocateRegisters()
679 ? Location::RegisterLocation(high->GetRegister()) in AllocateRegisters()
680 : Location::FpuRegisterLocation(high->GetRegister()); in AllocateRegisters()
1045 DCHECK(interval->GetRegister() == reg); in BlockRegister()
1082 InterferenceNode* physical_node = physical_nodes[to->GetInterval()->GetRegister()]; in AddPotentialInterference()
1084 DCHECK_EQ(to->GetInterval()->GetRegister(), physical_node->GetInterval()->GetRegister()); in AddPotentialInterference()
1098 physical_nodes[to->GetInterval()->GetHighInterval()->GetRegister()]; in AddPotentialInterference()
1099 DCHECK_EQ(to->GetInterval()->GetHighInterval()->GetRegister(), in AddPotentialInterference()
1100 high_node->GetInterval()->GetRegister()); in AddPotentialInterference()
[all …]
Dparallel_move_resolver.h72 int GetRegister() const { return reg_; } in GetRegister() function
Dregister_allocation_resolver.cc209 locations->SetTempAt(temp_index, Location::RegisterLocation(temp->GetRegister())); in Resolve()
215 temp->GetRegister(), temp->GetHighInterval()->GetRegister()); in Resolve()
218 locations->SetTempAt(temp_index, Location::FpuRegisterLocation(temp->GetRegister())); in Resolve()
Dssa_liveness_analysis.h449 int GetRegister() const { return register_; } in GetRegister() function
862 && interval->GetRegister() == GetRegister()) { in IsUsingInputRegister()
892 && interval->GetRegister() == GetRegister()) { in CanUseInputRegister()
Dcode_generator_x86.cc5777 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in MoveMemoryToMemory32()
5786 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in MoveMemoryToMemory64()
5884 Register temp = static_cast<Register>(ensure_scratch.GetRegister()); in EmitMove()
5941 __ movl(static_cast<Register>(ensure_scratch.GetRegister()), Address(ESP, mem + stack_offset)); in Exchange()
5943 __ movl(reg, static_cast<Register>(ensure_scratch.GetRegister())); in Exchange()
5950 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in Exchange32()
5961 Register suggested_scratch = ensure_scratch1.GetRegister() == EAX ? EBX : EAX; in Exchange()
5963 this, ensure_scratch1.GetRegister(), suggested_scratch, codegen_->GetNumberOfCoreRegisters()); in Exchange()
5967 __ movl(static_cast<Register>(ensure_scratch1.GetRegister()), Address(ESP, mem1 + stack_offset)); in Exchange()
5968 __ movl(static_cast<Register>(ensure_scratch2.GetRegister()), Address(ESP, mem2 + stack_offset)); in Exchange()
[all …]
Dcode_generator_x86_64.cc5345 __ movl(CpuRegister(ensure_scratch.GetRegister()), in Exchange32()
5349 CpuRegister(ensure_scratch.GetRegister())); in Exchange32()
5370 __ movq(CpuRegister(ensure_scratch.GetRegister()), in Exchange64()
5374 CpuRegister(ensure_scratch.GetRegister())); in Exchange64()
Dcode_generator_arm64.cc2501 Register rhs_reg = dst.IsX() ? rhs.GetRegister().X() : rhs.GetRegister().W(); in HandleShift()
Dcode_generator_mips64.cc1049 GpuRegister(ensure_scratch.GetRegister()), in Exchange()
1057 GpuRegister(ensure_scratch.GetRegister()), in Exchange()
Dcode_generator_arm.cc6551 __ LoadFromOffset(kLoadWord, static_cast<Register>(ensure_scratch.GetRegister()), in Exchange()
6554 __ StoreToOffset(kStoreWord, static_cast<Register>(ensure_scratch.GetRegister()), in Exchange()
Dcode_generator_mips.cc1219 Register(ensure_scratch.GetRegister()), in Exchange()
1227 Register(ensure_scratch.GetRegister()), in Exchange()
Dcode_generator_arm_vixl.cc6606 vixl32::Register temp2(ensure_scratch.GetRegister()); in Exchange()
/art/compiler/utils/arm/
Dassembler_thumb2.cc1222 if (so.IsRegister() && IsHighRegister(so.GetRegister()) && !can_contain_high_register) { in Is32BitDataProcessing()
1454 rn = so.GetRegister(); in Emit16BitDataProcessing()
1497 rn = so.GetRegister(); in Emit16BitDataProcessing()
1499 CHECK_EQ(rd, so.GetRegister()); in Emit16BitDataProcessing()
1507 rn = so.GetRegister(); in Emit16BitDataProcessing()
1515 rn = so.GetRegister(); in Emit16BitDataProcessing()
1522 rn = so.GetRegister(); in Emit16BitDataProcessing()
1576 rn = so.GetRegister(); in Emit16BitDataProcessing()
1645 Register rm = so.GetRegister(); in Emit16BitAddSub()
1665 immediate = static_cast<uint32_t>(so.GetRegister()); in Emit16BitAddSub()
[all …]
Dassembler_arm.h187 Register GetRegister() const { in GetRegister() function
279 Register GetRegister() const { in GetRegister() function
/art/runtime/
Dstack.cc352 uintptr_t ptr_val = GetRegister(reg, is_float); in GetRegisterIfAccessible()
427 uintptr_t ptr_val_lo = GetRegister(reg_lo, is_float); in GetRegisterPairIfAccessible()
428 uintptr_t ptr_val_hi = GetRegister(reg_hi, is_float); in GetRegisterPairIfAccessible()
Dstack.h825 uintptr_t GetRegister(uint32_t reg, bool is_float) const { in GetRegister() function