| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 101 reg = Mips64ManagedRegister::FromGpuRegister(RA); in TEST()
106 EXPECT_EQ(RA, reg.AsGpuRegister()); in TEST()
284 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
302 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
320 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
338 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
356 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
374 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
392 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
410 EXPECT_FALSE(reg.Overlaps(Mips64ManagedRegister::FromGpuRegister(RA))); in TEST()
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| D | assembler_mips64.cc | 686 Jalr(RA, rs); in Jalr()
2778 StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); in BuildFrame()
2779 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
2825 LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); in RemoveFrame()
2826 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
2832 Jr(RA); in RemoveFrame()
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| D | assembler_mips64_test.cc | 121 registers_.push_back(new mips64::GpuRegister(mips64::RA)); in SetUpHelpers()
154 secondary_register_names_.emplace(mips64::GpuRegister(mips64::RA), "ra"); in SetUpHelpers()
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| /art/runtime/arch/mips/ |
| D | registers_mips.cc | 31 if (rhs >= ZERO && rhs <= RA) { in operator <<()
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| D | registers_mips.h | 61 RA = 31, // Return address. enumerator
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| D | fault_handler_mips.cc | 87 sc->sc_regs[mips::RA] = sc->sc_pc + 4; // RA needs to point to gc map location in Action()
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| D | quick_method_frame_info_mips.h | 29 (1u << art::mips::RA);
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| D | quick_entrypoints_mips.S | 653 sw $ra, 0($t0) # Store RA per the compiler ABI
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 61 RA = 31, // Return address. enumerator
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| D | fault_handler_mips64.cc | 89 sc->sc_regs[mips64::RA] = sc->sc_pc + 4; // RA needs to point to gc map location in Action()
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| D | quick_method_frame_info_mips64.h | 29 (1 << art::mips64::RA);
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| D | quick_entrypoints_mips64.S | 1839 jal artInstrumentationMethodEntryFromCode # (Method*, Object*, Thread*, RA)
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 52 uint32_t result = 1 << RA; in CalculateCoreCalleeSpillMask()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 63 uint32_t result = 1 << RA; in CalculateCoreCalleeSpillMask()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 882 Jalr(RA, rs); in Jalr()
2443 return ((delay_slot.gpr_ins_mask_ | delay_slot.gpr_outs_mask_) & (1u << RA)) == 0; in CanHaveDelayedInstruction()
2849 Push(RA); in EmitBranch()
2854 Addu(AT, AT, RA); in EmitBranch()
2855 Lw(RA, SP, 0); in EmitBranch()
2869 Push(RA); in EmitBranch()
2874 Addu(AT, AT, RA); in EmitBranch()
2875 Lw(RA, SP, 0); in EmitBranch()
2888 Addu(AT, AT, RA); in EmitBranch()
3320 StoreToOffset(kStoreWord, RA, SP, stack_offset); in BuildFrame()
[all …]
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| D | assembler_mips32r6_test.cc | 118 registers_.push_back(new mips::Register(mips::RA)); in SetUpHelpers()
151 secondary_register_names_.emplace(mips::Register(mips::RA), "ra"); in SetUpHelpers()
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| D | assembler_mips_test.cc | 88 registers_.push_back(new mips::Register(mips::RA)); in SetUpHelpers()
121 secondary_register_names_.emplace(mips::Register(mips::RA), "ra"); in SetUpHelpers()
2510 __ Move(mips::T0, mips::RA); in TEST_F()
2513 __ Lw(mips::RA, mips::T0, 0); in TEST_F()
2519 __ Sw(mips::RA, mips::T0, 0); in TEST_F()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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| D | code_generator_mips.h | 57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| D | code_generator_mips.cc | 1033 AddAllocatedRegister(Location::RegisterLocation(RA)); in CodeGeneratorMIPS()
1275 CHECK_EQ(core_spill_mask_, 1u << RA); in GenerateFrameEntry()
1354 __ Jr(RA); in GenerateFrameExit()
1358 __ Jr(RA); in GenerateFrameExit()
1363 __ Jr(RA); in GenerateFrameExit()
1688 __ Addu(out, out, (base == ZERO) ? RA : base); in EmitPcRelativeAddressPlaceholderHigh()
1783 blocked_core_registers_[RA] = true; in SetupBlockedRegisters()
8525 __ Move(reg, RA); in VisitMipsComputeBaseMethodAddress()
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| D | code_generator_mips64.cc | 974 AddAllocatedRegister(Location::RegisterLocation(RA)); in CodeGeneratorMIPS64()
1158 __ Jic(RA, 0); in GenerateFrameExit()
1611 blocked_core_registers_[RA] = true; in SetupBlockedRegisters()
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